diff options
Diffstat (limited to 'arch/arm/cpu')
103 files changed, 2741 insertions, 1869 deletions
diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 8873fb719..93f429cc5 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -22,6 +22,7 @@ */ #include <common.h> +#include <div64.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/io.h> @@ -30,16 +31,17 @@ static u32 mx31_decode_pll(u32 reg, u32 infreq) { u32 mfi = GET_PLL_MFI(reg); - u32 mfn = GET_PLL_MFN(reg); + s32 mfn = GET_PLL_MFN(reg); u32 mfd = GET_PLL_MFD(reg); u32 pd = GET_PLL_PD(reg); mfi = mfi <= 5 ? 5 : mfi; + mfn = mfn >= 512 ? mfn - 1024 : mfn; mfd += 1; pd += 1; - return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) / - (mfd * pd)) << 10; + return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), + mfd * pd); } static u32 mx31_get_mpl_dpdgck_clk(void) @@ -47,9 +49,9 @@ static u32 mx31_get_mpl_dpdgck_clk(void) u32 infreq; if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) - infreq = CONFIG_MX31_CLK32 * 1024; + infreq = MXC_CLK32 * 1024; else - infreq = CONFIG_MX31_HCLK_FREQ; + infreq = MXC_HCLK; return mx31_decode_pll(readl(CCM_MPCTL), infreq); } diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index 72081a8bd..36266da5a 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> #include <div64.h> #include <watchdog.h> #include <asm/io.h> @@ -53,28 +54,27 @@ DECLARE_GLOBAL_DATA_PTR; static inline unsigned long long tick_to_time(unsigned long long tick) { tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_MX31_CLK32); + do_div(tick, MXC_CLK32); return tick; } static inline unsigned long long time_to_tick(unsigned long long time) { - time *= CONFIG_MX31_CLK32; + time *= MXC_CLK32; do_div(time, CONFIG_SYS_HZ); return time; } static inline unsigned long long us_to_tick(unsigned long long us) { - us = us * CONFIG_MX31_CLK32 + 999999; + us = us * MXC_CLK32 + 999999; do_div(us, 1000000); return us; } #else /* ~2% error */ -#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) \ - / CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32) +#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) +#define US_PER_TICK (1000000 / MXC_CLK32) static inline unsigned long long tick_to_time(unsigned long long tick) { @@ -128,7 +128,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ @@ -159,7 +159,7 @@ void __udelay(unsigned long usec) */ ulong get_tbclk(void) { - return CONFIG_MX31_CLK32; + return MXC_CLK32; } void reset_cpu(ulong addr) diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index 986b1f946..ef65176ee 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -24,12 +24,16 @@ */ #include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#ifdef CONFIG_FSL_ESDHC +#include <fsl_esdhc.h> +#endif #include <netdev.h> #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) @@ -126,15 +130,17 @@ static int get_ahb_div(u32 pdr0) static u32 decode_pll(u32 reg, u32 infreq) { u32 mfi = (reg >> 10) & 0xf; - u32 mfn = reg & 0x3f; - u32 mfd = (reg >> 16) & 0x3f; + s32 mfn = reg & 0x3ff; + u32 mfd = (reg >> 16) & 0x3ff; u32 pd = (reg >> 26) & 0xf; mfi = mfi <= 5 ? 5 : mfi; + mfn = mfn >= 512 ? mfn - 1024 : mfn; mfd += 1; pd += 1; - return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; + return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), + mfd * pd); } static u32 get_mcu_main_clk(void) @@ -143,9 +149,7 @@ static u32 get_mcu_main_clk(void) struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); - fi *= - decode_pll(readl(&ccm->mpctl), - CONFIG_MX35_HCLK_FREQ); + fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK); return fi / (arm_div * fd); } @@ -168,17 +172,14 @@ static u32 get_ipg_per_clk(void) u32 pdr4 = readl(&ccm->pdr4); u32 div; if (pdr0 & MXC_CCM_PDR0_PER_SEL) { - div = (CCM_GET_DIVIDER(pdr4, - MXC_CCM_PDR4_PER0_PRDF_MASK, - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * - (CCM_GET_DIVIDER(pdr4, + div = CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_PER0_PODF_MASK, - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1; } else { div = CCM_GET_DIVIDER(pdr0, MXC_CCM_PDR0_PER_PODF_MASK, MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; - freq /= get_ahb_div(pdr0); + div *= get_ahb_div(pdr0); } return freq / div; } @@ -190,25 +191,20 @@ u32 imx_get_uartclk(void) (struct ccm_regs *)IMX_CCM_BASE; u32 pdr4 = readl(&ccm->pdr4); - if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) { + if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) freq = get_mcu_main_clk(); - } else { - freq = decode_pll(readl(&ccm->ppctl), - CONFIG_MX35_HCLK_FREQ); - } - freq /= ((CCM_GET_DIVIDER(pdr4, - MXC_CCM_PDR4_UART_PRDF_MASK, - MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * - (CCM_GET_DIVIDER(pdr4, + else + freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK); + freq /= CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_UART_PODF_MASK, - MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); + MXC_CCM_PDR4_UART_PODF_OFFSET) + 1; return freq; } -unsigned int mxc_get_main_clock(enum mxc_main_clocks clk) +unsigned int mxc_get_main_clock(enum mxc_main_clock clk) { u32 nfc_pdf, hsp_podf; - u32 pll, ret_val = 0, usb_prdf, usb_podf; + u32 pll, ret_val = 0, usb_podf; struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; @@ -252,16 +248,13 @@ unsigned int mxc_get_main_clock(enum mxc_main_clocks clk) ret_val = pll / (nfc_pdf + 1); break; case USB_CLK: - usb_prdf = (reg4 >> 25) & 0x7; - usb_podf = (reg4 >> 22) & 0x7; - if (reg4 & 0x200) { + usb_podf = (reg4 >> 22) & 0x3F; + if (reg4 & 0x200) pll = get_mcu_main_clk(); - } else { - pll = decode_pll(readl(&ccm->ppctl), - CONFIG_MX35_HCLK_FREQ); - } + else + pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK); - ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1)); + ret_val = pll / (usb_podf + 1); break; default: printf("Unknown clock: %d\n", clk); @@ -270,7 +263,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clocks clk) return ret_val; } -unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk) +unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) { u32 ret_val = 0, pdf, pre_pdf, clk_sel; struct ccm_regs *ccm = @@ -284,18 +277,16 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk) case UART2_BAUD: case UART3_BAUD: clk_sel = mpdr3 & (1 << 14); - pre_pdf = (mpdr4 >> 13) & 0x7; - pdf = (mpdr4 >> 10) & 0x7; + pdf = (mpdr4 >> 10) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case SSI1_BAUD: pre_pdf = (mpdr2 >> 24) & 0x7; pdf = mpdr2 & 0x3F; clk_sel = mpdr2 & (1 << 6); ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; case SSI2_BAUD: @@ -303,16 +294,14 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk) pdf = (mpdr2 >> 8) & 0x3F; clk_sel = mpdr2 & (1 << 6); ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; case CSI_BAUD: clk_sel = mpdr2 & (1 << 7); - pre_pdf = (mpdr2 >> 16) & 0x7; - pdf = (mpdr2 >> 19) & 0x7; + pdf = (mpdr2 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case MSHC_CLK: pre_pdf = readl(&ccm->pdr1); @@ -320,39 +309,33 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk) pdf = (pre_pdf >> 22) & 0x3F; pre_pdf = (pre_pdf >> 28) & 0x7; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; case ESDHC1_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = mpdr3 & 0x7; - pdf = (mpdr3>>3) & 0x7; + pdf = mpdr3 & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case ESDHC2_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = (mpdr3 >> 8) & 0x7; - pdf = (mpdr3 >> 11) & 0x7; + pdf = (mpdr3 >> 8) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case ESDHC3_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = (mpdr3 >> 16) & 0x7; - pdf = (mpdr3 >> 19) & 0x7; + pdf = (mpdr3 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case SPDIF_CLK: clk_sel = mpdr3 & 0x400000; pre_pdf = (mpdr3 >> 29) & 0x7; pdf = (mpdr3 >> 23) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; default: @@ -463,7 +446,6 @@ int print_cpuinfo(void) * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() */ - int cpu_eth_init(bd_t *bis) { int rc = -ENODEV; @@ -475,6 +457,17 @@ int cpu_eth_init(bd_t *bis) return rc; } +#ifdef CONFIG_FSL_ESDHC +/* + * Initializes on-chip MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) +{ + return fsl_esdhc_mmc_init(bis); +} +#endif + int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC diff --git a/arch/arm/cpu/arm1136/mx35/iomux.c b/arch/arm/cpu/arm1136/mx35/iomux.c index f93191dae..a302575ed 100644 --- a/arch/arm/cpu/arm1136/mx35/iomux.c +++ b/arch/arm/cpu/arm1136/mx35/iomux.c @@ -44,8 +44,6 @@ enum iomux_reg_addr { #define MUX_INPUT_NUM_MUX \ (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1) -#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2) - /* * Request ownership for an IO pin. This function has to be the first one * being called before that pin is used. diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c index 04937a1df..9680b7fde 100644 --- a/arch/arm/cpu/arm1136/mx35/timer.c +++ b/arch/arm/cpu/arm1136/mx35/timer.c @@ -27,6 +27,7 @@ #include <asm/io.h> #include <div64.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> DECLARE_GLOBAL_DATA_PTR; @@ -37,43 +38,52 @@ DECLARE_GLOBAL_DATA_PTR; /* General purpose timers bitfields */ #define GPTCR_SWR (1<<15) /* Software reset */ #define GPTCR_FRR (1<<9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ -#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ +#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ #define GPTCR_TEN (1) /* Timer enable */ -#define TIMER_FREQ_HZ mxc_get_clock(MXC_IPG_CLK) - +/* + * "time" is measured in 1 / CONFIG_SYS_HZ seconds, + * "tick" is internal timer period + */ +/* ~0.4% error - measured with stop-watch on 100s boot-delay */ static inline unsigned long long tick_to_time(unsigned long long tick) { tick *= CONFIG_SYS_HZ; - do_div(tick, TIMER_FREQ_HZ); + do_div(tick, MXC_CLK32); return tick; } -static inline unsigned long long us_to_tick(unsigned long long usec) +static inline unsigned long long us_to_tick(unsigned long long us) { - usec *= TIMER_FREQ_HZ; - do_div(usec, 1000000); + us = us * MXC_CLK32 + 999999; + do_div(us, 1000000); - return usec; + return us; } +/* + * nothing really to do with interrupts, just starts up a counter. + * The 32KHz 32-bit timer overruns in 134217 seconds + */ int timer_init(void) { int i; struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; + struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR; /* setup GP Timer 1 */ writel(GPTCR_SWR, &gpt->ctrl); - for (i = 0; i < 100; i++) - writel(0, &gpt->ctrl); /* We have no udelay by now */ - writel(0, &gpt->pre); - /* Freerun Mode, PERCLK1 input */ - writel(readl(&gpt->ctrl) | - GPTCR_CLKSOURCE_IPG | GPTCR_TEN, - &gpt->ctrl); + writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1); + + for (i = 0; i < 100; i++) + writel(0, &gpt->ctrl); /* We have no udelay by now */ + writel(0, &gpt->pre); /* prescaler = 1 */ + /* Freerun Mode, 32KHz input */ + writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, + &gpt->ctrl); + writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl); return 0; } @@ -101,7 +111,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ @@ -132,5 +142,5 @@ void __udelay(unsigned long usec) */ ulong get_tbclk(void) { - return TIMER_FREQ_HZ; + return MXC_CLK32; } diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/cpu/arm1176/bcm2835/Makefile new file mode 100644 index 000000000..4ea6d6b89 --- /dev/null +++ b/arch/arm/cpu/arm1176/bcm2835/Makefile @@ -0,0 +1,37 @@ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# version 2 as published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +SOBJS := lowlevel_init.o +COBJS := reset.o timer.o + +SRCS := $(SOBJS:.o=.c) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm1176/bcm2835/config.mk b/arch/arm/cpu/arm1176/bcm2835/config.mk new file mode 100644 index 000000000..b87ce244c --- /dev/null +++ b/arch/arm/cpu/arm1176/bcm2835/config.mk @@ -0,0 +1,19 @@ +# +# (C) Copyright 2012 Stephen Warren +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# version 2 as published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# Don't attempt to override the target CPU/ABI options; +# the Raspberry Pi toolchain does the right thing by default. +PLATFORM_RELFLAGS := $(filter-out -msoft-float,$(PLATFORM_RELFLAGS)) +PLATFORM_CPPFLAGS := $(filter-out -march=armv5t,$(PLATFORM_CPPFLAGS)) diff --git a/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S b/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S new file mode 100644 index 000000000..c7b084328 --- /dev/null +++ b/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S @@ -0,0 +1,19 @@ +/* + * (C) Copyright 2012 Stephen Warren + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +.globl lowlevel_init +lowlevel_init: + mov pc, lr diff --git a/arch/arm/cpu/arm1176/bcm2835/reset.c b/arch/arm/cpu/arm1176/bcm2835/reset.c new file mode 100644 index 000000000..8c37ad9fd --- /dev/null +++ b/arch/arm/cpu/arm1176/bcm2835/reset.c @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2012 Stephen Warren + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/wdog.h> + +#define RESET_TIMEOUT 10 + +void reset_cpu(ulong addr) +{ + struct bcm2835_wdog_regs *regs = + (struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR; + uint32_t rstc; + + rstc = readl(®s->rstc); + rstc &= ~BCM2835_WDOG_RSTC_WRCFG_MASK; + rstc |= BCM2835_WDOG_RSTC_WRCFG_FULL_RESET; + + writel(BCM2835_WDOG_PASSWORD | RESET_TIMEOUT, ®s->wdog); + writel(BCM2835_WDOG_PASSWORD | rstc, ®s->rstc); +} diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/cpu/arm1176/bcm2835/timer.c new file mode 100644 index 000000000..d232d7e06 --- /dev/null +++ b/arch/arm/cpu/arm1176/bcm2835/timer.c @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2012 Stephen Warren + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/timer.h> + +int timer_init(void) +{ + return 0; +} + +ulong get_timer(ulong base) +{ + struct bcm2835_timer_regs *regs = + (struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR; + + return readl(®s->clo) - base; +} + +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} + +void __udelay(unsigned long usec) +{ + ulong endtime; + signed long diff; + + endtime = get_timer(0) + usec; + + do { + ulong now = get_timer(0); + diff = endtime - now; + } while (diff >= 0); +} diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c index c0fd114e1..532a90b54 100644 --- a/arch/arm/cpu/arm1176/cpu.c +++ b/arch/arm/cpu/arm1176/cpu.c @@ -65,3 +65,10 @@ static void cache_flush (void) /* mem barrier to sync things */ asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0)); } + +int arch_cpu_init(void) +{ + icache_enable(); + + return 0; +} diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c index 974f2880a..ce7b3c9c2 100644 --- a/arch/arm/cpu/arm720t/cpu.c +++ b/arch/arm/cpu/arm720t/cpu.c @@ -51,6 +51,8 @@ int cleanup_before_linux (void) /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No cleanup before linux for IntegratorAP/CM720T as yet */ +#elif defined(CONFIG_TEGRA) + /* No cleanup before linux for tegra as yet */ #else #error No cleanup_before_linux() defined for this CPU type #endif diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index 464dd3046..c2f898f2c 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -180,6 +180,9 @@ int timer_init (void) PUT32(T0TC, 0); PUT32(T0TCR, 1); /* enable timer0 */ +#elif defined(CONFIG_TEGRA) + /* No timer routines for tegra as yet */ + lastdec = 0; #else #error No timer_init() defined for this CPU type #endif @@ -282,6 +285,8 @@ void __udelay (unsigned long usec) #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No timer routines for IntegratorAP/CM720T as yet */ +#elif defined(CONFIG_TEGRA) + /* No timer routines for tegra as yet */ #else #error Timer routines not defined for this CPU type #endif diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 3b97e804a..2f914e9b4 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -51,6 +51,16 @@ _start: b reset ldr pc, _irq ldr pc, _fiq +#ifdef CONFIG_SPL_BUILD +_undefined_instruction: .word _undefined_instruction +_software_interrupt: .word _software_interrupt +_prefetch_abort: .word _prefetch_abort +_data_abort: .word _data_abort +_not_used: .word _not_used +_irq: .word _irq +_fiq: .word _fiq +_pad: .word 0x12345678 /* now 16*4=64 */ +#else _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort @@ -58,6 +68,8 @@ _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq +_pad: .word 0x12345678 /* now 16*4=64 */ +#endif /* CONFIG_SPL_BUILD */ .balignl 16,0xdeadbeef @@ -77,7 +89,11 @@ _fiq: .word fiq .globl _TEXT_BASE _TEXT_BASE: +#ifdef CONFIG_SPL_BUILD + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. @@ -167,6 +183,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs @@ -398,6 +415,8 @@ lock_loop: ldr r0, VPBDIV_ADR mov r1, #0x01 /* VPB clock is same as process clock */ str r1, [r0] +#elif defined(CONFIG_TEGRA) + /* No cpu_init_crit for tegra as yet */ #else #error No cpu_init_crit() defined for current CPU type #endif @@ -413,7 +432,7 @@ lock_loop: str r1, [r0] #endif -#ifndef CONFIG_LPC2292 +#if !defined(CONFIG_LPC2292) && !defined(CONFIG_TEGRA) mov ip, lr /* * before relocating, we have to setup RAM timing @@ -427,6 +446,7 @@ lock_loop: mov pc, lr +#ifndef CONFIG_SPL_BUILD /* ************************************************************************* * @@ -589,6 +609,7 @@ fiq: bl do_fiq #endif +#endif /* CONFIG_SPL_BUILD */ #if defined(CONFIG_NETARM) .align 5 @@ -620,6 +641,8 @@ reset_cpu: .globl reset_cpu reset_cpu: mov pc, r0 +#elif defined(CONFIG_TEGRA) + /* No specific reset actions for tegra as yet */ #else #error No reset_cpu() defined for current CPU type #endif diff --git a/arch/arm/cpu/arm720t/tegra20/Makefile b/arch/arm/cpu/arm720t/tegra20/Makefile new file mode 100644 index 000000000..6e484756d --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra20/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2010,2011 Nvidia Corporation. +# +# (C) Copyright 2000-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS-y += cpu.o +COBJS-$(CONFIG_SPL_BUILD) += spl.o + +SRCS := $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/imx-common/speed.c b/arch/arm/cpu/arm720t/tegra20/board.h index 80989c498..61b91c005 100644 --- a/arch/arm/cpu/armv7/imx-common/speed.c +++ b/arch/arm/cpu/arm720t/tegra20/board.h @@ -1,9 +1,6 @@ /* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * (C) Copyright 2010-2011 + * NVIDIA Corporation <www.nvidia.com> * * See file CREDITS for list of people who contributed to this * project. @@ -24,22 +21,5 @@ * MA 02111-1307 USA */ -#include <common.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> - -#ifdef CONFIG_FSL_ESDHC -DECLARE_GLOBAL_DATA_PTR; -#endif - -int get_clocks(void) -{ -#ifdef CONFIG_FSL_ESDHC -#ifdef CONFIG_FSL_USDHC - gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); -#else - gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK); -#endif -#endif - return 0; -} +void board_init_uart_f(void); +void gpio_config_uart(void); diff --git a/arch/arm/cpu/arm720t/tegra20/config.mk b/arch/arm/cpu/arm720t/tegra20/config.mk new file mode 100644 index 000000000..62a31d8a6 --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra20/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation <www.nvidia.com> +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +USE_PRIVATE_LIBGCC = yes diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/arm720t/tegra20/cpu.c index 1aad3879e..ddf8d979f 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/arm720t/tegra20/cpu.c @@ -22,54 +22,17 @@ */ #include <asm/io.h> -#include <asm/arch/tegra2.h> -#include <asm/arch/ap20.h> +#include <asm/arch/tegra20.h> #include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> -#include <asm/arch/fuse.h> -#include <asm/arch/gp_padctrl.h> #include <asm/arch/pmc.h> #include <asm/arch/pinmux.h> #include <asm/arch/scu.h> -#include <asm/arch/warmboot.h> #include <common.h> - -int tegra_get_chip_type(void) -{ - struct apb_misc_gp_ctlr *gp; - struct fuse_regs *fuse = (struct fuse_regs *)TEGRA2_FUSE_BASE; - uint tegra_sku_id, rev; - - /* - * This is undocumented, Chip ID is bits 15:8 of the register - * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for - * Tegra30 - */ - gp = (struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE; - rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; - - tegra_sku_id = readl(&fuse->sku_info) & 0xff; - - switch (rev) { - case CHIPID_TEGRA2: - switch (tegra_sku_id) { - case SKU_ID_T20: - return TEGRA_SOC_T20; - case SKU_ID_T25SE: - case SKU_ID_AP25: - case SKU_ID_T25: - case SKU_ID_AP25E: - case SKU_ID_T25E: - return TEGRA_SOC_T25; - } - break; - } - /* unknown sku id */ - return TEGRA_SOC_UNKNOWN; -} +#include "cpu.h" /* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */ -static int ap20_cpu_is_cortexa9(void) +int ap20_cpu_is_cortexa9(void) { u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0); return id == (PG_UP_TAG_0_PID_CPU & 0xff); @@ -77,10 +40,8 @@ static int ap20_cpu_is_cortexa9(void) void init_pllx(void) { - struct clk_rst_ctlr *clkrst = - (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - struct clk_pll_simple *pll = - &clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE]; + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU]; u32 reg; /* If PLLX is already enabled, just return */ @@ -144,14 +105,14 @@ static void enable_cpu_clock(int enable) static int is_cpu_powered(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; } static void remove_cpu_io_clamps(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; /* Remove the clamps on the CPU I/O signals */ @@ -165,7 +126,7 @@ static void remove_cpu_io_clamps(void) static void powerup_cpu(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; int timeout = IO_STABILIZATION_DELAY; @@ -196,7 +157,7 @@ static void powerup_cpu(void) static void enable_cpu_power_rail(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; reg = readl(&pmc->pmc_cntrl); @@ -295,94 +256,3 @@ void halt_avp(void) FLOW_CTLR_HALT_COP_EVENTS); } } - -void enable_scu(void) -{ - struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; - u32 reg; - - /* If SCU already setup/enabled, return */ - if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE) - return; - - /* Invalidate all ways for all processors */ - writel(0xFFFF, &scu->scu_inv_all); - - /* Enable SCU - bit 0 */ - reg = readl(&scu->scu_ctrl); - reg |= SCU_CTRL_ENABLE; - writel(reg, &scu->scu_ctrl); -} - -static u32 get_odmdata(void) -{ - /* - * ODMDATA is stored in the BCT in IRAM by the BootROM. - * The BCT start and size are stored in the BIT in IRAM. - * Read the data @ bct_start + (bct_size - 12). This works - * on T20 and T30 BCTs, which are locked down. If this changes - * in new chips (T114, etc.), we can revisit this algorithm. - */ - - u32 bct_start, odmdata; - - bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR); - odmdata = readl(bct_start + BCT_ODMDATA_OFFSET); - - return odmdata; -} - -void init_pmc_scratch(void) -{ - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; - u32 odmdata; - int i; - - /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ - for (i = 0; i < 23; i++) - writel(0, &pmc->pmc_scratch1+i); - - /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ - odmdata = get_odmdata(); - writel(odmdata, &pmc->pmc_scratch20); - -#ifdef CONFIG_TEGRA2_LP0 - /* save Sdram params to PMC 2, 4, and 24 for WB0 */ - warmboot_save_sdram_params(); -#endif -} - -void tegra2_start(void) -{ - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - - /* If we are the AVP, start up the first Cortex-A9 */ - if (!ap20_cpu_is_cortexa9()) { - /* enable JTAG */ - writel(0xC0, &pmt->pmt_cfg_ctl); - - /* - * If we are ARM7 - give it a different stack. We are about to - * start up the A9 which will want to use this one. - */ - asm volatile("mov sp, %0\n" - : : "r"(AVP_EARLY_BOOT_STACK_LIMIT)); - - start_cpu((u32)_start); - halt_avp(); - /* not reached */ - } - - /* Init PMC scratch memory */ - init_pmc_scratch(); - - enable_scu(); - - /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #0x41\n" - "mcr p15, 0, r0, c1, c0, 1\n"); - - /* FIXME: should have ap20's L2 disabled too? */ -} diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.h b/arch/arm/cpu/arm720t/tegra20/cpu.h new file mode 100644 index 000000000..6804cd7a3 --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra20/cpu.h @@ -0,0 +1,100 @@ +/* + * (C) Copyright 2010-2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <asm/types.h> + +/* Stabilization delays, in usec */ +#define PLL_STABILIZATION_DELAY (300) +#define IO_STABILIZATION_DELAY (1000) + +#define NVBL_PLLP_KHZ (216000) + +#define PLLX_ENABLED (1 << 30) +#define CCLK_BURST_POLICY 0x20008888 +#define SUPER_CCLK_DIVIDER 0x80000000 + +/* Calculate clock fractional divider value from ref and target frequencies */ +#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) + +/* Calculate clock frequency value from reference and clock divider value */ +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) + +/* AVP/CPU ID */ +#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ +#define PG_UP_TAG_0 0x0 + +#define CORESIGHT_UNLOCK 0xC5ACCE55; + +/* AP20-Specific Base Addresses */ + +/* AP20 Base physical address of SDRAM. */ +#define AP20_BASE_PA_SDRAM 0x00000000 +/* AP20 Base physical address of internal SRAM. */ +#define AP20_BASE_PA_SRAM 0x40000000 +/* AP20 Size of internal SRAM (256KB). */ +#define AP20_BASE_PA_SRAM_SIZE 0x00040000 +/* AP20 Base physical address of flash. */ +#define AP20_BASE_PA_NOR_FLASH 0xD0000000 +/* AP20 Base physical address of boot information table. */ +#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM + +/* + * Super-temporary stacks for EXTREMELY early startup. The values chosen for + * these addresses must be valid on ALL SOCs because this value is used before + * we are able to differentiate between the SOC types. + * + * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its + * stack is placed below the AVP stack. Once the CPU stack has been moved, + * the AVP is free to use the IRAM the CPU stack previously occupied if + * it should need to do so. + * + * NOTE: In multi-processor CPU complex configurations, each processor will have + * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a + * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a + * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous + * CPU. + */ + +/* Common AVP early boot stack limit */ +#define AVP_EARLY_BOOT_STACK_LIMIT \ + (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2)) +/* Common AVP early boot stack size */ +#define AVP_EARLY_BOOT_STACK_SIZE 0x1000 +/* Common CPU early boot stack limit */ +#define CPU_EARLY_BOOT_STACK_LIMIT \ + (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE) +/* Common CPU early boot stack size */ +#define CPU_EARLY_BOOT_STACK_SIZE 0x1000 + +#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) +#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) +#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) + +#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) +#define FLOW_MODE_STOP 2 +#define HALT_COP_EVENT_JTAG (1 << 28) +#define HALT_COP_EVENT_IRQ_1 (1 << 11) +#define HALT_COP_EVENT_FIQ_1 (1 << 9) + +void start_cpu(u32 reset_vector); +int ap20_cpu_is_cortexa9(void); +void halt_avp(void) __attribute__ ((noreturn)); diff --git a/arch/arm/cpu/arm720t/tegra20/spl.c b/arch/arm/cpu/arm720t/tegra20/spl.c new file mode 100644 index 000000000..6c16dce29 --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra20/spl.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2012 + * NVIDIA Inc, <www.nvidia.com> + * + * Allen Martin <amartin@nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> +#include <nand.h> +#include <mmc.h> +#include <fat.h> +#include <version.h> +#include <i2c.h> +#include <image.h> +#include <malloc.h> +#include <linux/compiler.h> +#include "board.h" +#include "cpu.h" + +#include <asm/io.h> +#include <asm/arch/tegra20.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/pmc.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/scu.h> +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Define global data structure pointer to it*/ +static gd_t gdata __attribute__ ((section(".data"))); +static bd_t bdata __attribute__ ((section(".data"))); + +inline void hang(void) +{ + puts("### ERROR ### Please RESET the board ###\n"); + for (;;) + ; +} + +void board_init_f(ulong dummy) +{ + board_init_uart_f(); + + /* Initialize periph GPIOs */ +#ifdef CONFIG_SPI_UART_SWITCH + gpio_early_init_uart(); +#else + gpio_config_uart(); +#endif + + /* + * We call relocate_code() with relocation target same as the + * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting + * skipped. Instead, only .bss initialization will happen. That's + * all we need + */ + debug(">>board_init_f()\n"); + relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE); +} + +/* This requires UART clocks to be enabled */ +static void preloader_console_init(void) +{ + const char *u_boot_rev = U_BOOT_VERSION; + + gd = &gdata; + gd->bd = &bdata; + gd->flags |= GD_FLG_RELOC; + gd->baudrate = CONFIG_BAUDRATE; + + serial_init(); /* serial communications setup */ + + gd->have_console = 1; + + /* Avoid a second "U-Boot" coming from this string */ + u_boot_rev = &u_boot_rev[7]; + + printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE, + U_BOOT_TIME); +} + +void board_init_r(gd_t *id, ulong dummy) +{ + struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + + /* enable JTAG */ + writel(0xC0, &pmt->pmt_cfg_ctl); + + debug(">>spl:board_init_r()\n"); + + mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START, + CONFIG_SYS_SPL_MALLOC_SIZE); + +#ifdef CONFIG_SPL_BOARD_INIT + spl_board_init(); +#endif + + clock_early_init(); + serial_init(); + preloader_console_init(); + + start_cpu((u32)CONFIG_SYS_TEXT_BASE); + halt_avp(); + /* not reached */ +} + +int board_usb_init(const void *blob) +{ + return 0; +} diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile index f333753c7..346e58fae 100644 --- a/arch/arm/cpu/arm926ejs/at91/Makefile +++ b/arch/arm/cpu/arm926ejs/at91/Makefile @@ -35,6 +35,7 @@ COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o +COBJS-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o COBJS-$(CONFIG_AT91_EFLASH) += eflash.o COBJS-$(CONFIG_AT91_LED) += led.o COBJS-y += clock.o diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c index 62f76fa8e..19ec615c7 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -158,6 +158,10 @@ void at91_spi1_hw_init(unsigned long cs_mask) #ifdef CONFIG_MACB void at91_macb_hw_init(void) { + /* Enable EMAC clock */ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */ at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */ at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ERX0 */ diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c new file mode 100644 index 000000000..6d77219d0 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c @@ -0,0 +1,232 @@ +/* + * Copyright (C) 2012 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/io.h> + +unsigned int get_chip_id(void) +{ + /* The 0x40 is the offset of cidr in DBGU */ + return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK; +} + +unsigned int get_extension_chip_id(void) +{ + /* The 0x44 is the offset of exid in DBGU */ + return readl(ATMEL_BASE_DBGU + 0x44); +} + +unsigned int has_emac1() +{ + return cpu_is_at91sam9x25(); +} + +unsigned int has_emac0() +{ + return !(cpu_is_at91sam9g15()); +} + +unsigned int has_lcdc() +{ + return cpu_is_at91sam9g15() || cpu_is_at91sam9g35() + || cpu_is_at91sam9x35(); +} + +char *get_cpu_name() +{ + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_at91sam9x5()) { + switch (extension_id) { + case ARCH_EXID_AT91SAM9G15: + return CONFIG_SYS_AT91_G15_CPU_NAME; + case ARCH_EXID_AT91SAM9G25: + return CONFIG_SYS_AT91_G25_CPU_NAME; + case ARCH_EXID_AT91SAM9G35: + return CONFIG_SYS_AT91_G35_CPU_NAME; + case ARCH_EXID_AT91SAM9X25: + return CONFIG_SYS_AT91_X25_CPU_NAME; + case ARCH_EXID_AT91SAM9X35: + return CONFIG_SYS_AT91_X35_CPU_NAME; + default: + return CONFIG_SYS_AT91_UNKNOWN_CPU; + } + } else { + return CONFIG_SYS_AT91_UNKNOWN_CPU; + } +} + +void at91_seriald_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ + + writel(1 << ATMEL_ID_SYS, &pmc->pcer); +} + +void at91_serial0_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */ + + writel(1 << ATMEL_ID_USART0, &pmc->pcer); +} + +void at91_serial1_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */ + + writel(1 << ATMEL_ID_USART1, &pmc->pcer); +} + +void at91_serial2_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */ + at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */ + + writel(1 << ATMEL_ID_USART2, &pmc->pcer); +} + +#ifdef CONFIG_ATMEL_SPI +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + + if (cs_mask & (1 << 0)) + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); + if (cs_mask & (1 << 1)) + at91_set_b_periph(AT91_PIO_PORTA, 7, 0); + if (cs_mask & (1 << 2)) + at91_set_b_periph(AT91_PIO_PORTA, 1, 0); + if (cs_mask & (1 << 3)) + at91_set_b_periph(AT91_PIO_PORTB, 3, 0); + if (cs_mask & (1 << 4)) + at91_set_pio_output(AT91_PIO_PORTA, 14, 0); + if (cs_mask & (1 << 5)) + at91_set_pio_output(AT91_PIO_PORTA, 7, 0); + if (cs_mask & (1 << 6)) + at91_set_pio_output(AT91_PIO_PORTA, 1, 0); + if (cs_mask & (1 << 7)) + at91_set_pio_output(AT91_PIO_PORTB, 3, 0); +} + +void at91_spi1_hw_init(unsigned long cs_mask) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ + at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ + at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); + + if (cs_mask & (1 << 0)) + at91_set_b_periph(AT91_PIO_PORTA, 8, 0); + if (cs_mask & (1 << 1)) + at91_set_b_periph(AT91_PIO_PORTA, 0, 0); + if (cs_mask & (1 << 2)) + at91_set_b_periph(AT91_PIO_PORTA, 31, 0); + if (cs_mask & (1 << 3)) + at91_set_b_periph(AT91_PIO_PORTA, 30, 0); + if (cs_mask & (1 << 4)) + at91_set_pio_output(AT91_PIO_PORTA, 8, 0); + if (cs_mask & (1 << 5)) + at91_set_pio_output(AT91_PIO_PORTA, 0, 0); + if (cs_mask & (1 << 6)) + at91_set_pio_output(AT91_PIO_PORTA, 31, 0); + if (cs_mask & (1 << 7)) + at91_set_pio_output(AT91_PIO_PORTA, 30, 0); +} +#endif + +#ifdef CONFIG_MACB +void at91_macb_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + if (has_emac0()) { + /* Enable EMAC0 clock */ + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + /* EMAC0 pins setup */ + at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */ + } + + if (has_emac1()) { + /* Enable EMAC1 clock */ + writel(1 << ATMEL_ID_EMAC1, &pmc->pcer); + /* EMAC1 pins setup */ + at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */ + at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */ + at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */ + at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */ + at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */ + at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */ + at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */ + at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */ + at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */ + at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */ + } + +#ifndef CONFIG_RMII + /* Only emac0 support MII */ + if (has_emac0()) { + at91_set_b_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ + at91_set_b_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ + at91_set_b_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ + at91_set_b_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ + at91_set_b_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ + at91_set_b_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ + at91_set_b_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ + at91_set_b_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ + } +#endif +} +#endif diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c index a7085deac..dc5c6c4b0 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -154,7 +154,8 @@ int at91_clock_init(unsigned long main_clock) * For now, assume this parentage won't change. */ mckr = readl(&pmc->mckr); -#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \ + || defined(CONFIG_AT91SAM9X5) /* plla divisor by 2 */ gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); #endif @@ -168,7 +169,14 @@ int at91_clock_init(unsigned long main_clock) freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; if (mckr & AT91_PMC_MCKR_MDIV_MASK) freq /= 2; /* processor clock division */ -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \ + || defined(CONFIG_AT91SAM9X5) + /* mdiv <==> divisor + * 0 <==> 1 + * 1 <==> 2 + * 2 <==> 4 + * 3 <==> 3 + */ gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4) ? freq / 3 diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/cpu/arm926ejs/at91/cpu.c index c47fb31e9..5cf4fad0b 100644 --- a/arch/arm/cpu/arm926ejs/at91/cpu.c +++ b/arch/arm/cpu/arm926ejs/at91/cpu.c @@ -71,29 +71,3 @@ int print_cpuinfo(void) return 0; } #endif - -#ifdef CONFIG_BOOTCOUNT_LIMIT -/* - * We combine the BOOTCOUNT_MAGIC and bootcount in one 32-bit register. - * This is done so we need to use only one of the four GPBR registers. - */ -void bootcount_store (ulong a) -{ - at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; - - writel((BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff), - &gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]); -} - -ulong bootcount_load (void) -{ - at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; - - ulong val = readl(&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]); - if ((val & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) - return 0; - else - return val & 0x0000ffff; -} - -#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index da7efac08..c91928e71 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS-y += cpu.o misc.o timer.o psc.o pinmux.o +COBJS-y += cpu.o misc.o timer.o psc.o pinmux.o reset.o COBJS-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM365) += dm365.o @@ -42,8 +42,6 @@ COBJS-$(CONFIG_SOC_DM365) += dm365_lowlevel.o COBJS-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o endif -SOBJS = reset.o - ifndef CONFIG_SKIP_LOWLEVEL_INIT SOBJS += lowlevel_init.o endif diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 6cb857aef..b31add8de 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -117,6 +117,17 @@ int clk_get(enum davinci_clk_ids id) out: return pll_out; } + +int set_cpu_clk_info(void) +{ + gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; + /* DDR PHY uses an x2 input clock */ + gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : + (clk_get(DAVINCI_DDR_CLKID) / 1000000); + gd->bd->bi_dsp_freq = 0; + return 0; +} + #else /* CONFIG_SOC_DA8XX */ static unsigned pll_div(volatile void *pllbase, unsigned offset) @@ -187,16 +198,9 @@ unsigned int davinci_clk_get(unsigned int div) return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000; } #endif -#endif /* !CONFIG_SOC_DA8XX */ int set_cpu_clk_info(void) { -#ifdef CONFIG_SOC_DA8XX - gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; - /* DDR PHY uses an x2 input clock */ - gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000; -#else - unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE; #if defined(CONFIG_SOC_DM365) pllbase = DAVINCI_PLL_CNTRL1_BASE; @@ -215,10 +219,12 @@ int set_cpu_clk_info(void) pllbase = DAVINCI_PLL_CNTRL0_BASE; #endif gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2; -#endif + return 0; } +#endif /* !CONFIG_SOC_DA8XX */ + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c index df7d6a24b..ff2e2e33d 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c @@ -190,13 +190,21 @@ int da850_ddr_setup(void) setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); - - setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); } - + setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); - clrbits_le32(&davinci_syscfg1_regs->ddr_slew, - (1 << DDR_SLEW_CMOSEN_BIT)); + + if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) { + /* DDR2 */ + clrbits_le32(&davinci_syscfg1_regs->ddr_slew, + (1 << DDR_SLEW_DDR_PDENA_BIT) | + (1 << DDR_SLEW_CMOSEN_BIT)); + } else { + /* MOBILE DDR */ + setbits_le32(&davinci_syscfg1_regs->ddr_slew, + (1 << DDR_SLEW_DDR_PDENA_BIT) | + (1 << DDR_SLEW_CMOSEN_BIT)); + } /* * SDRAM Configuration Register (SDCR): @@ -216,7 +224,11 @@ int da850_ddr_setup(void) writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); /* write memory configuration and timing */ - writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2); + if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) { + /* MOBILE DDR only*/ + writel(CONFIG_SYS_DA850_DDR2_SDBCR2, + &dv_ddr2_regs_ctrl->sdbcr2); + } writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); @@ -240,7 +252,7 @@ int da850_ddr_setup(void) /* disable self refresh */ clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, - DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN); + DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN); writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); return 0; diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c index fa07fb591..133265e5b 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c @@ -35,6 +35,11 @@ const struct pinmux_config spi1_pins_scs0[] = { }; /* UART pin muxer settings */ +const struct pinmux_config uart0_pins_txrx[] = { + { pinmux(3), 2, 4 }, /* UART0_RXD */ + { pinmux(3), 2, 5 }, /* UART0_TXD */ +}; + const struct pinmux_config uart1_pins_txrx[] = { { pinmux(4), 2, 6 }, /* UART1_RXD */ { pinmux(4), 2, 7 }, /* UART1_TXD */ @@ -169,3 +174,14 @@ const struct pinmux_config emifa_pins_nor[] = { { pinmux(12), 1, 6 }, /* EMA_A[1] */ { pinmux(12), 1, 7 }, /* EMA_A[0] */ }; + +/* MMC0 pin muxer settings */ +const struct pinmux_config mmc0_pins[] = { + { pinmux(10), 2, 0 }, /* MMCSD0_CLK */ + { pinmux(10), 2, 1 }, /* MMCSD0_CMD */ + { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */ + { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */ + { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */ + { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */ + /* DA850 supports only 4-bit mode, remaining pins are not configured */ +}; diff --git a/arch/arm/cpu/arm926ejs/davinci/psc.c b/arch/arm/cpu/arm926ejs/davinci/psc.c index 3e925181e..2ffb42abc 100644 --- a/arch/arm/cpu/arm926ejs/davinci/psc.c +++ b/arch/arm/cpu/arm926ejs/davinci/psc.c @@ -128,6 +128,11 @@ void lpsc_syncreset(unsigned int id) lpsc_transition(id, 0x01); } +void lpsc_disable(unsigned int id) +{ + lpsc_transition(id, 0x0); +} + /* Not all DaVinci chips have a DSP power domain. */ #ifdef CONFIG_SOC_DM644X diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.S b/arch/arm/cpu/arm926ejs/davinci/reset.S deleted file mode 100644 index ba0a7c3b4..000000000 --- a/arch/arm/cpu/arm926ejs/davinci/reset.S +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Processor reset using WDT for TI TMS320DM644x SoC. - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * ----------------------------------------------------- - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -.globl reset_cpu -reset_cpu: - ldr r0, WDT_TGCR - mov r1, $0x08 - str r1, [r0] - ldr r1, [r0] - orr r1, r1, $0x03 - str r1, [r0] - mov r1, $0 - ldr r0, WDT_TIM12 - str r1, [r0] - ldr r0, WDT_TIM34 - str r1, [r0] - ldr r0, WDT_PRD12 - str r1, [r0] - ldr r0, WDT_PRD34 - str r1, [r0] - ldr r0, WDT_TCR - ldr r1, [r0] - orr r1, r1, $0x40 - str r1, [r0] - ldr r0, WDT_WDTCR - ldr r1, [r0] - orr r1, r1, $0x4000 - str r1, [r0] - ldr r1, WDTCR_VAL1 - str r1, [r0] - ldr r1, WDTCR_VAL2 - str r1, [r0] - /* Write an invalid value to the WDKEY field to trigger - * an immediate watchdog reset */ - mov r1, $0x4000 - str r1, [r0] - nop - nop - nop - nop -reset_cpu_loop: - b reset_cpu_loop - -WDT_TGCR: - .word 0x01c21c24 -WDT_TIM12: - .word 0x01c21c10 -WDT_TIM34: - .word 0x01c21c14 -WDT_PRD12: - .word 0x01c21c18 -WDT_PRD34: - .word 0x01c21c1c -WDT_TCR: - .word 0x01c21c20 -WDT_WDTCR: - .word 0x01c21c28 -WDTCR_VAL1: - .word 0xa5c64000 -WDTCR_VAL2: - .word 0xda7e4000 diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.c b/arch/arm/cpu/arm926ejs/davinci/reset.c new file mode 100644 index 000000000..968fb035c --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/reset.c @@ -0,0 +1,33 @@ +/* + * Processor reset using WDT. + * + * Copyright (C) 2012 Dmitry Bondar <bond@inmys.ru> + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/timer_defs.h> +#include <asm/arch/hardware.h> + +void reset_cpu(unsigned long a) +{ + struct davinci_timer *const wdttimer = + (struct davinci_timer *)DAVINCI_TIMER1_BASE; + writel(0x08, &wdttimer->tgcr); + writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr); + writel(0, &wdttimer->tim12); + writel(0, &wdttimer->tim34); + writel(0, &wdttimer->prd12); + writel(0, &wdttimer->prd34); + writel(readl(&wdttimer->tcr) | 0x40, &wdttimer->tcr); + writel(readl(&wdttimer->wdtcr) | 0x4000, &wdttimer->wdtcr); + writel(0xa5c64000, &wdttimer->wdtcr); + writel(0xda7e4000, &wdttimer->wdtcr); + writel(0x4000, &wdttimer->wdtcr); + while (1) + /*nothing*/; +} diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c index 74632e516..03c85c87f 100644 --- a/arch/arm/cpu/arm926ejs/davinci/spl.c +++ b/arch/arm/cpu/arm926ejs/davinci/spl.c @@ -28,6 +28,7 @@ #include <ns16550.h> #include <malloc.h> #include <spi_flash.h> +#include <mmc.h> #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT @@ -74,12 +75,7 @@ void board_init_f(ulong dummy) void board_init_r(gd_t *id, ulong dummy) { -#ifdef CONFIG_SPL_NAND_LOAD - nand_init(); - puts("Nand boot...\n"); - nand_boot(); -#endif -#ifdef CONFIG_SPL_SPI_LOAD +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN); @@ -90,7 +86,19 @@ void board_init_r(gd_t *id, ulong dummy) serial_init(); /* serial communications setup */ gd->have_console = 1; +#endif + +#ifdef CONFIG_SPL_NAND_LOAD + nand_init(); + puts("Nand boot...\n"); + nand_boot(); +#endif +#ifdef CONFIG_SPL_SPI_LOAD puts("SPI boot...\n"); spi_boot(); #endif +#ifdef CONFIG_SPL_MMC_LOAD + puts("MMC boot...\n"); + spl_mmc_load(); +#endif } diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index 8b07dae2b..90e584ac5 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -64,7 +64,7 @@ static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) static ulong imx_get_mpllclk(void) { struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - ulong fref = 24000000; + ulong fref = MXC_HCLK; return imx_decode_pll(readl(&ccm->mpctl), fref); } @@ -186,6 +186,14 @@ int print_cpuinfo(void) } #endif +void enable_caches(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +#endif +} + int cpu_eth_init(bd_t *bis) { #if defined(CONFIG_FEC_MXC) diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c index 1cfd02b23..4dc4041c0 100644 --- a/arch/arm/cpu/arm926ejs/mx25/timer.c +++ b/arch/arm/cpu/arm926ejs/mx25/timer.c @@ -40,6 +40,7 @@ #include <div64.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> DECLARE_GLOBAL_DATA_PTR; @@ -55,28 +56,27 @@ DECLARE_GLOBAL_DATA_PTR; static inline unsigned long long tick_to_time(unsigned long long tick) { tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_MX25_CLK32); + do_div(tick, MXC_CLK32); return tick; } static inline unsigned long long time_to_tick(unsigned long long time) { - time *= CONFIG_MX25_CLK32; + time *= MXC_CLK32; do_div(time, CONFIG_SYS_HZ); return time; } static inline unsigned long long us_to_tick(unsigned long long us) { - us = us * CONFIG_MX25_CLK32 + 999999; + us = us * MXC_CLK32 + 999999; do_div(us, 1000000); return us; } #else /* ~2% error */ -#define TICK_PER_TIME ((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \ - CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / CONFIG_MX25_CLK32) +#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) +#define US_PER_TICK (1000000 / MXC_CLK32) static inline unsigned long long tick_to_time(unsigned long long tick) { @@ -144,7 +144,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ @@ -177,6 +177,6 @@ ulong get_tbclk(void) { ulong tbclk; - tbclk = CONFIG_MX25_CLK32; + tbclk = MXC_CLK32; return tbclk; } diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c index 65c481378..41bb84bb6 100644 --- a/arch/arm/cpu/arm926ejs/mx27/generic.c +++ b/arch/arm/cpu/arm926ejs/mx27/generic.c @@ -24,6 +24,7 @@ #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> +#include <asm/arch/gpio.h> #ifdef CONFIG_MXC_MMC #include <asm/arch/mxcmmc.h> #endif @@ -209,7 +210,7 @@ int cpu_mmc_init(bd_t *bis) void imx_gpio_mode(int gpio_mode) { - struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE; + struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE; unsigned int pin = gpio_mode & GPIO_PIN_MASK; unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; @@ -228,11 +229,11 @@ void imx_gpio_mode(int gpio_mode) /* Data direction */ if (gpio_mode & GPIO_OUT) { - writel(readl(®s->port[port].ddir) | 1 << pin, - ®s->port[port].ddir); + writel(readl(®s->port[port].gpio_dir) | 1 << pin, + ®s->port[port].gpio_dir); } else { - writel(readl(®s->port[port].ddir) & ~(1 << pin), - ®s->port[port].ddir); + writel(readl(®s->port[port].gpio_dir) & ~(1 << pin), + ®s->port[port].gpio_dir); } /* Primary / alternate function */ diff --git a/arch/arm/cpu/arm926ejs/mx28/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index 674a3af1b..eeecf89f8 100644 --- a/arch/arm/cpu/arm926ejs/mx28/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS = clock.o mx28.o iomux.o timer.o +COBJS = clock.o mxs.o iomux.o timer.o ifdef CONFIG_SPL_BUILD COBJS += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o diff --git a/arch/arm/cpu/arm926ejs/mx28/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index 0439f9c0e..bfea6abeb 100644 --- a/arch/arm/cpu/arm926ejs/mx28/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -43,8 +43,8 @@ static uint32_t mx28_get_pclk(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; uint32_t clkctrl, clkseq, div; uint8_t clkfrac, frac; @@ -75,8 +75,8 @@ static uint32_t mx28_get_pclk(void) static uint32_t mx28_get_hclk(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; uint32_t div; uint32_t clkctrl; @@ -93,8 +93,8 @@ static uint32_t mx28_get_hclk(void) static uint32_t mx28_get_emiclk(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; uint32_t clkctrl, clkseq, div; uint8_t clkfrac, frac; @@ -118,8 +118,8 @@ static uint32_t mx28_get_emiclk(void) static uint32_t mx28_get_gpmiclk(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; uint32_t clkctrl, clkseq, div; uint8_t clkfrac, frac; @@ -145,8 +145,8 @@ static uint32_t mx28_get_gpmiclk(void) */ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; uint32_t div; int io_reg; @@ -178,8 +178,8 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq) */ static uint32_t mx28_get_ioclk(enum mxs_ioclock io) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; uint8_t ret; int io_reg; @@ -199,15 +199,15 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io) */ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; uint32_t clk, clkreg; if (ssp > MXC_SSPCLK3) return; clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp * sizeof(struct mx28_register_32)); + (ssp * sizeof(struct mxs_register_32)); clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE); while (readl(clkreg) & CLKCTRL_SSP_CLKGATE) @@ -243,8 +243,8 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) */ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; uint32_t clkreg; uint32_t clk, tmp; @@ -256,7 +256,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp) return XTAL_FREQ_KHZ; clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp * sizeof(struct mx28_register_32)); + (ssp * sizeof(struct mxs_register_32)); tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK; @@ -273,12 +273,12 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp) */ void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq) { - struct mx28_ssp_regs *ssp_regs; + struct mxs_ssp_regs *ssp_regs; const uint32_t sspclk = mx28_get_sspclk(bus); uint32_t reg; uint32_t divide, rate, tgtclk; - ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000)); + ssp_regs = (struct mxs_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000)); /* * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), diff --git a/arch/arm/cpu/arm926ejs/mx28/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c index 12916b6d6..73f144690 100644 --- a/arch/arm/cpu/arm926ejs/mx28/iomux.c +++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c @@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) { u32 reg, ofs, bp, bm; void *iomux_base = (void *)MXS_PINCTRL_BASE; - struct mx28_register_32 *mxs_reg; + struct mxs_register_32 *mxs_reg; /* muxsel */ ofs = 0x100; @@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) /* vol */ if (PAD_VOL_VALID(pad)) { bp = PAD_PIN(pad) % 8 * 4 + 2; - mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs); + mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs); if (PAD_VOL(pad)) writel(1 << bp, &mxs_reg->reg_set); else @@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) ofs = PULL_OFFSET; ofs += PAD_BANK(pad) * 0x10; bp = PAD_PIN(pad); - mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs); + mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs); if (PAD_PULL(pad)) writel(1 << bp, &mxs_reg->reg_set); else diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index ff2577209..6ce8019b8 100644 --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR; /* 1 second delay should be plenty of time for block reset. */ #define RESET_MAX_TIMEOUT 1000000 -#define MX28_BLOCK_SFTRST (1 << 31) -#define MX28_BLOCK_CLKGATE (1 << 30) +#define MXS_BLOCK_SFTRST (1 << 31) +#define MXS_BLOCK_CLKGATE (1 << 30) /* Lowlevel init isn't used on i.MX28, so just have a dummy here */ inline void lowlevel_init(void) {} @@ -51,10 +51,10 @@ void reset_cpu(ulong ignored) __attribute__((noreturn)); void reset_cpu(ulong ignored) { - struct mx28_rtc_regs *rtc_regs = - (struct mx28_rtc_regs *)MXS_RTC_BASE; - struct mx28_lcdif_regs *lcdif_regs = - (struct mx28_lcdif_regs *)MXS_LCDIF_BASE; + struct mxs_rtc_regs *rtc_regs = + (struct mxs_rtc_regs *)MXS_RTC_BASE; + struct mxs_lcdif_regs *lcdif_regs = + (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; /* * Shut down the LCD controller as it interferes with BootROM boot mode @@ -81,7 +81,8 @@ void enable_caches(void) #endif } -int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout) +int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned + int timeout) { while (--timeout) { if ((readl(®->reg) & mask) == mask) @@ -92,7 +93,8 @@ int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout) return !timeout; } -int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout) +int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned + int timeout) { while (--timeout) { if ((readl(®->reg) & mask) == 0) @@ -103,34 +105,34 @@ int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout) return !timeout; } -int mx28_reset_block(struct mx28_register_32 *reg) +int mxs_reset_block(struct mxs_register_32 *reg) { /* Clear SFTRST */ - writel(MX28_BLOCK_SFTRST, ®->reg_clr); + writel(MXS_BLOCK_SFTRST, ®->reg_clr); - if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) + if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) return 1; /* Clear CLKGATE */ - writel(MX28_BLOCK_CLKGATE, ®->reg_clr); + writel(MXS_BLOCK_CLKGATE, ®->reg_clr); /* Set SFTRST */ - writel(MX28_BLOCK_SFTRST, ®->reg_set); + writel(MXS_BLOCK_SFTRST, ®->reg_set); /* Wait for CLKGATE being set */ - if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) + if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) return 1; /* Clear SFTRST */ - writel(MX28_BLOCK_SFTRST, ®->reg_clr); + writel(MXS_BLOCK_SFTRST, ®->reg_clr); - if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) + if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) return 1; /* Clear CLKGATE */ - writel(MX28_BLOCK_CLKGATE, ®->reg_clr); + writel(MXS_BLOCK_CLKGATE, ®->reg_clr); - if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) + if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) return 1; return 0; @@ -155,8 +157,8 @@ int arch_misc_init(void) int arch_cpu_init(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; extern uint32_t _start; mx28_fixup_vt((uint32_t)&_start); @@ -188,14 +190,48 @@ int arch_cpu_init(void) } #if defined(CONFIG_DISPLAY_CPUINFO) +static const char *get_cpu_type(void) +{ + struct mxs_digctl_regs *digctl_regs = + (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; + + switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) { + case HW_DIGCTL_CHIPID_MX28: + return "28"; + default: + return "??"; + } +} + +static const char *get_cpu_rev(void) +{ + struct mxs_digctl_regs *digctl_regs = + (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; + uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF; + + switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) { + case HW_DIGCTL_CHIPID_MX28: + switch (rev) { + case 0x1: + return "1.2"; + default: + return "??"; + } + default: + return "??"; + } +} + int print_cpuinfo(void) { - struct mx28_spl_data *data = (struct mx28_spl_data *) - ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); + struct mxs_spl_data *data = (struct mxs_spl_data *) + ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); - printf("Freescale i.MX28 family at %d MHz\n", - mxc_get_clock(MXC_ARM_CLK) / 1000000); - printf("BOOT: %s\n", mx28_boot_modes[data->boot_mode_idx].mode); + printf("CPU: Freescale i.MX%s rev%s at %d MHz\n", + get_cpu_type(), + get_cpu_rev(), + mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode); return 0; } #endif @@ -212,11 +248,11 @@ int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) /* * Initializes on-chip ethernet controllers. */ -#ifdef CONFIG_CMD_NET +#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET) int cpu_eth_init(bd_t *bis) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; /* Turn on ENET clocks */ clrbits_le32(&clkctrl_regs->hw_clkctrl_enet, @@ -257,15 +293,15 @@ void mx28_adjust_mac(int dev_id, unsigned char *mac) #define MXS_OCOTP_MAX_TIMEOUT 1000000 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { - struct mx28_ocotp_regs *ocotp_regs = - (struct mx28_ocotp_regs *)MXS_OCOTP_BASE; + struct mxs_ocotp_regs *ocotp_regs = + (struct mxs_ocotp_regs *)MXS_OCOTP_BASE; uint32_t data; memset(mac, 0, 6); writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); - if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, + if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, MXS_OCOTP_MAX_TIMEOUT)) { printf("MXS FEC: Can't get MAC from OCOTP\n"); return; @@ -286,13 +322,13 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) } #endif -int mx28_dram_init(void) +int mxs_dram_init(void) { - struct mx28_spl_data *data = (struct mx28_spl_data *) - ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); + struct mxs_spl_data *data = (struct mxs_spl_data *) + ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); if (data->mem_dram_size == 0) { - printf("MX28:\n" + printf("MXS:\n" "Error, the RAM size passed up from SPL is 0!\n"); hang(); } diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h index e3a4493fb..2ddc5bc0c 100644 --- a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h +++ b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h @@ -28,18 +28,18 @@ void early_delay(int delay); -void mx28_power_init(void); +void mxs_power_init(void); #ifdef CONFIG_SPL_MX28_PSWITCH_WAIT -void mx28_power_wait_pswitch(void); +void mxs_power_wait_pswitch(void); #else -static inline void mx28_power_wait_pswitch(void) { } +static inline void mxs_power_wait_pswitch(void) { } #endif -void mx28_mem_init(void); -uint32_t mx28_mem_get_size(void); +void mxs_mem_init(void); +uint32_t mxs_mem_get_size(void); -void mx28_lradc_init(void); -void mx28_lradc_enable_batt_measurement(void); +void mxs_lradc_init(void); +void mxs_lradc_enable_batt_measurement(void); #endif /* __M28_INIT_H__ */ diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index a6dfca3f5..ad66c57c5 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -26,12 +26,11 @@ #include <common.h> #include <config.h> #include <asm/io.h> -#include <asm/arch/iomux-mx28.h> #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include "mx28_init.h" +#include "mxs_init.h" /* * This delay function is intended to be used only in early stage of boot, where @@ -39,12 +38,14 @@ * takes a few seconds to roll. The boot doesn't take that long, so to keep the * code simple, it doesn't take rolling into consideration. */ -#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0 void early_delay(int delay) { - uint32_t st = readl(HW_DIGCTRL_MICROSECONDS); + struct mxs_digctl_regs *digctl_regs = + (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; + + uint32_t st = readl(&digctl_regs->hw_digctl_microseconds); st += delay; - while (st > readl(HW_DIGCTRL_MICROSECONDS)) + while (st > readl(&digctl_regs->hw_digctl_microseconds)) ; } @@ -58,7 +59,7 @@ const iomux_cfg_t iomux_boot[] = { MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, }; -uint8_t mx28_get_bootmode_index(void) +uint8_t mxs_get_bootmode_index(void) { uint8_t bootmode = 0; int i; @@ -83,31 +84,31 @@ uint8_t mx28_get_bootmode_index(void) bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4; bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; - for (i = 0; i < ARRAY_SIZE(mx28_boot_modes); i++) { - masked = bootmode & mx28_boot_modes[i].boot_mask; - if (masked == mx28_boot_modes[i].boot_pads) + for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) { + masked = bootmode & mxs_boot_modes[i].boot_mask; + if (masked == mxs_boot_modes[i].boot_pads) break; } return i; } -void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, +void mxs_common_spl_init(const iomux_cfg_t *iomux_setup, const unsigned int iomux_size) { - struct mx28_spl_data *data = (struct mx28_spl_data *) - ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); - uint8_t bootmode = mx28_get_bootmode_index(); + struct mxs_spl_data *data = (struct mxs_spl_data *) + ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); + uint8_t bootmode = mxs_get_bootmode_index(); mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size); - mx28_power_init(); + mxs_power_init(); - mx28_mem_init(); - data->mem_dram_size = mx28_mem_get_size(); + mxs_mem_init(); + data->mem_dram_size = mxs_mem_get_size(); data->boot_mode_idx = bootmode; - mx28_power_wait_pswitch(); + mxs_power_wait_pswitch(); } /* Support aparatus */ diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c index 88a603c11..d90f0a131 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c @@ -28,11 +28,11 @@ #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include "mx28_init.h" +#include "mxs_init.h" -void mx28_lradc_init(void) +void mxs_lradc_init(void) { - struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE; + struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE; writel(LRADC_CTRL0_SFTRST, ®s->hw_lradc_ctrl0_clr); writel(LRADC_CTRL0_CLKGATE, ®s->hw_lradc_ctrl0_clr); @@ -49,9 +49,9 @@ void mx28_lradc_init(void) LRADC_CTRL4_LRADC6SELECT_CHANNEL10); } -void mx28_lradc_enable_batt_measurement(void) +void mxs_lradc_enable_batt_measurement(void) { - struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE; + struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE; /* Check if the channel is present at all. */ if (!(readl(®s->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT)) diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index e17a4d7c7..e693145b9 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -26,12 +26,11 @@ #include <common.h> #include <config.h> #include <asm/io.h> -#include <asm/arch/iomux-mx28.h> #include <asm/arch/imx-regs.h> -#include "mx28_init.h" +#include "mxs_init.h" -uint32_t dram_vals[] = { +static uint32_t mx28_dram_vals[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -82,26 +81,26 @@ uint32_t dram_vals[] = { 0x00000000, 0x00010001 }; -void __mx28_adjust_memory_params(uint32_t *dram_vals) +void __mxs_adjust_memory_params(uint32_t *dram_vals) { } -void mx28_adjust_memory_params(uint32_t *dram_vals) - __attribute__((weak, alias("__mx28_adjust_memory_params"))); +void mxs_adjust_memory_params(uint32_t *dram_vals) + __attribute__((weak, alias("__mxs_adjust_memory_params"))); -void init_m28_200mhz_ddr2(void) +void init_mx28_200mhz_ddr2(void) { int i; - mx28_adjust_memory_params(dram_vals); + mxs_adjust_memory_params(mx28_dram_vals); - for (i = 0; i < ARRAY_SIZE(dram_vals); i++) - writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); + for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++) + writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i)); } -void mx28_mem_init_clock(void) +void mxs_mem_init_clock(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; /* Gate EMI clock */ writeb(CLKCTRL_FRAC_CLKGATE, @@ -129,10 +128,10 @@ void mx28_mem_init_clock(void) early_delay(10000); } -void mx28_mem_setup_cpu_and_hbus(void) +void mxs_mem_setup_cpu_and_hbus(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz * and ungate CPU clock */ @@ -161,10 +160,10 @@ void mx28_mem_setup_cpu_and_hbus(void) early_delay(15000); } -void mx28_mem_setup_vdda(void) +void mxs_mem_setup_vdda(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | @@ -172,10 +171,10 @@ void mx28_mem_setup_vdda(void) &power_regs->hw_power_vddactrl); } -void mx28_mem_setup_vddd(void) +void mxs_mem_setup_vddd(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) | (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) | @@ -183,7 +182,7 @@ void mx28_mem_setup_vddd(void) &power_regs->hw_power_vdddctrl); } -uint32_t mx28_mem_get_size(void) +uint32_t mxs_mem_get_size(void) { uint32_t sz, da; uint32_t *vt = (uint32_t *)0x20; @@ -202,12 +201,12 @@ uint32_t mx28_mem_get_size(void) return sz; } -void mx28_mem_init(void) +void mxs_mem_init(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - struct mx28_pinctrl_regs *pinctrl_regs = - (struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_pinctrl_regs *pinctrl_regs = + (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; /* Set DDR2 mode */ writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, @@ -219,9 +218,9 @@ void mx28_mem_init(void) early_delay(11000); - mx28_mem_init_clock(); + mxs_mem_init_clock(); - mx28_mem_setup_vdda(); + mxs_mem_setup_vdda(); /* * Configure the DRAM registers @@ -230,7 +229,7 @@ void mx28_mem_init(void) /* Clear START bit from DRAM_CTL16 */ clrbits_le32(MXS_DRAM_BASE + 0x40, 1); - init_m28_200mhz_ddr2(); + init_mx28_200mhz_ddr2(); /* Clear SREFRESH bit from DRAM_CTL17 */ clrbits_le32(MXS_DRAM_BASE + 0x44, 1); @@ -242,9 +241,9 @@ void mx28_mem_init(void) while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) ; - mx28_mem_setup_vddd(); + mxs_mem_setup_vddd(); early_delay(10000); - mx28_mem_setup_cpu_and_hbus(); + mxs_mem_setup_cpu_and_hbus(); } diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 4b09b0c3b..4b917bd18 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -28,22 +28,22 @@ #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include "mx28_init.h" +#include "mxs_init.h" -void mx28_power_clock2xtal(void) +void mxs_power_clock2xtal(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; /* Set XTAL as CPU reference clock */ writel(CLKCTRL_CLKSEQ_BYPASS_CPU, &clkctrl_regs->hw_clkctrl_clkseq_set); } -void mx28_power_clock2pll(void) +void mxs_power_clock2pll(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0, CLKCTRL_PLL0CTRL0_POWER); @@ -52,10 +52,10 @@ void mx28_power_clock2pll(void) CLKCTRL_CLKSEQ_BYPASS_CPU); } -void mx28_power_clear_auto_restart(void) +void mxs_power_clear_auto_restart(void) { - struct mx28_rtc_regs *rtc_regs = - (struct mx28_rtc_regs *)MXS_RTC_BASE; + struct mxs_rtc_regs *rtc_regs = + (struct mxs_rtc_regs *)MXS_RTC_BASE; writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr); while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST) @@ -85,10 +85,10 @@ void mx28_power_clear_auto_restart(void) ; } -void mx28_power_set_linreg(void) +void mxs_power_set_linreg(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; /* Set linear regulator 25mV below switching converter */ clrsetbits_le32(&power_regs->hw_power_vdddctrl, @@ -104,10 +104,10 @@ void mx28_power_set_linreg(void) POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW); } -int mx28_get_batt_volt(void) +int mxs_get_batt_volt(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t volt = readl(&power_regs->hw_power_battmonitor); volt &= POWER_BATTMONITOR_BATT_VAL_MASK; volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; @@ -115,16 +115,16 @@ int mx28_get_batt_volt(void) return volt; } -int mx28_is_batt_ready(void) +int mxs_is_batt_ready(void) { - return (mx28_get_batt_volt() >= 3600); + return (mxs_get_batt_volt() >= 3600); } -int mx28_is_batt_good(void) +int mxs_is_batt_good(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - uint32_t volt = mx28_get_batt_volt(); + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; + uint32_t volt = mxs_get_batt_volt(); if ((volt >= 2400) && (volt <= 4300)) return 1; @@ -145,7 +145,7 @@ int mx28_is_batt_good(void) early_delay(500000); - volt = mx28_get_batt_volt(); + volt = mxs_get_batt_volt(); if (volt >= 3500) return 0; @@ -160,10 +160,10 @@ int mx28_is_batt_good(void) return 0; } -void mx28_power_setup_5v_detect(void) +void mxs_power_setup_5v_detect(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; /* Start 5V detection */ clrsetbits_le32(&power_regs->hw_power_5vctrl, @@ -172,10 +172,10 @@ void mx28_power_setup_5v_detect(void) POWER_5VCTRL_PWRUP_VBUS_CMPS); } -void mx28_src_power_init(void) +void mxs_src_power_init(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; /* Improve efficieny and reduce transient ripple */ writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST | @@ -203,10 +203,10 @@ void mx28_src_power_init(void) clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); } -void mx28_power_init_4p2_params(void) +void mxs_power_init_4p2_params(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; /* Setup 4P2 parameters */ clrsetbits_le32(&power_regs->hw_power_dcdc4p2, @@ -227,10 +227,10 @@ void mx28_power_init_4p2_params(void) 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); } -void mx28_enable_4p2_dcdc_input(int xfer) +void mxs_enable_4p2_dcdc_input(int xfer) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo; uint32_t prev_5v_brnout, prev_5v_droop; @@ -323,10 +323,10 @@ void mx28_enable_4p2_dcdc_input(int xfer) POWER_CTRL_ENIRQ_VDD5V_DROOP); } -void mx28_power_init_4p2_regulator(void) +void mxs_power_init_4p2_regulator(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp, tmp2; setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2); @@ -346,7 +346,7 @@ void mx28_power_init_4p2_regulator(void) * gradually to avoid large inrush current from the 5V cable which can * cause transients/problems */ - mx28_enable_4p2_dcdc_input(0); + mxs_enable_4p2_dcdc_input(0); if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { /* @@ -407,17 +407,17 @@ void mx28_power_init_4p2_regulator(void) writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); } -void mx28_power_init_dcdc_4p2_source(void) +void mxs_power_init_dcdc_4p2_source(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; if (!(readl(&power_regs->hw_power_dcdc4p2) & POWER_DCDC4P2_ENABLE_DCDC)) { hang(); } - mx28_enable_4p2_dcdc_input(1); + mxs_enable_4p2_dcdc_input(1); if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { clrbits_le32(&power_regs->hw_power_dcdc4p2, @@ -429,10 +429,10 @@ void mx28_power_init_dcdc_4p2_source(void) } } -void mx28_power_enable_4p2(void) +void mxs_power_enable_4p2(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t vdddctrl, vddactrl, vddioctrl; uint32_t tmp; @@ -451,11 +451,11 @@ void mx28_power_enable_4p2(void) setbits_le32(&power_regs->hw_power_vddioctrl, POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); - mx28_power_init_4p2_params(); - mx28_power_init_4p2_regulator(); + mxs_power_init_4p2_params(); + mxs_power_init_4p2_regulator(); /* Shutdown battery (none present) */ - if (!mx28_is_batt_ready()) { + if (!mxs_is_batt_ready()) { clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); writel(POWER_CTRL_DCDC4P2_BO_IRQ, @@ -464,7 +464,7 @@ void mx28_power_enable_4p2(void) &power_regs->hw_power_ctrl_clr); } - mx28_power_init_dcdc_4p2_source(); + mxs_power_init_dcdc_4p2_source(); writel(vdddctrl, &power_regs->hw_power_vdddctrl); early_delay(20); @@ -488,10 +488,10 @@ void mx28_power_enable_4p2(void) &power_regs->hw_power_charge_clr); } -void mx28_boot_valid_5v(void) +void mxs_boot_valid_5v(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; /* * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V @@ -508,22 +508,22 @@ void mx28_boot_valid_5v(void) writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ, &power_regs->hw_power_ctrl_clr); - mx28_power_enable_4p2(); + mxs_power_enable_4p2(); } -void mx28_powerdown(void) +void mxs_powerdown(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset); writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, &power_regs->hw_power_reset); } -void mx28_batt_boot(void) +void mxs_batt_boot(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC); @@ -542,7 +542,7 @@ void mx28_batt_boot(void) clrsetbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); - mx28_power_set_linreg(); + mxs_power_set_linreg(); clrbits_le32(&power_regs->hw_power_vdddctrl, POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG); @@ -564,10 +564,10 @@ void mx28_batt_boot(void) 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); } -void mx28_handle_5v_conflict(void) +void mxs_handle_5v_conflict(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp; setbits_le32(&power_regs->hw_power_vddioctrl, @@ -577,52 +577,56 @@ void mx28_handle_5v_conflict(void) tmp = readl(&power_regs->hw_power_sts); if (tmp & POWER_STS_VDDIO_BO) { - mx28_powerdown(); + /* + * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes + * unreliable + */ + mxs_powerdown(); break; } if (tmp & POWER_STS_VDD5V_GT_VDDIO) { - mx28_boot_valid_5v(); + mxs_boot_valid_5v(); break; } else { - mx28_powerdown(); + mxs_powerdown(); break; } if (tmp & POWER_STS_PSWITCH_MASK) { - mx28_batt_boot(); + mxs_batt_boot(); break; } } } -void mx28_5v_boot(void) +void mxs_5v_boot(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; /* * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID, * but their implementation always returns 1 so we omit it here. */ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - mx28_boot_valid_5v(); + mxs_boot_valid_5v(); return; } early_delay(1000); if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - mx28_boot_valid_5v(); + mxs_boot_valid_5v(); return; } - mx28_handle_5v_conflict(); + mxs_handle_5v_conflict(); } -void mx28_init_batt_bo(void) +void mxs_init_batt_bo(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; /* Brownout at 3V */ clrsetbits_le32(&power_regs->hw_power_battmonitor, @@ -633,10 +637,10 @@ void mx28_init_batt_bo(void) writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); } -void mx28_switch_vddd_to_dcdc_source(void) +void mxs_switch_vddd_to_dcdc_source(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; clrsetbits_le32(&power_regs->hw_power_vdddctrl, POWER_VDDDCTRL_LINREG_OFFSET_MASK, @@ -647,51 +651,48 @@ void mx28_switch_vddd_to_dcdc_source(void) POWER_VDDDCTRL_DISABLE_STEPPING); } -void mx28_power_configure_power_source(void) +void mxs_power_configure_power_source(void) { int batt_ready, batt_good; - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; - struct mx28_lradc_regs *lradc_regs = - (struct mx28_lradc_regs *)MXS_LRADC_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; + struct mxs_lradc_regs *lradc_regs = + (struct mxs_lradc_regs *)MXS_LRADC_BASE; - mx28_src_power_init(); - - batt_ready = mx28_is_batt_ready(); + mxs_src_power_init(); if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - batt_good = mx28_is_batt_good(); + batt_ready = mxs_is_batt_ready(); if (batt_ready) { /* 5V source detected, good battery detected. */ - mx28_batt_boot(); + mxs_batt_boot(); } else { - if (batt_good) { - /* 5V source detected, low battery detceted. */ - } else { + batt_good = mxs_is_batt_good(); + if (!batt_good) { /* 5V source detected, bad battery detected. */ writel(LRADC_CONVERSION_AUTOMATIC, &lradc_regs->hw_lradc_conversion_clr); clrbits_le32(&power_regs->hw_power_battmonitor, POWER_BATTMONITOR_BATT_VAL_MASK); } - mx28_5v_boot(); + mxs_5v_boot(); } } else { /* 5V not detected, booting from battery. */ - mx28_batt_boot(); + mxs_batt_boot(); } - mx28_power_clock2pll(); + mxs_power_clock2pll(); - mx28_init_batt_bo(); + mxs_init_batt_bo(); - mx28_switch_vddd_to_dcdc_source(); + mxs_switch_vddd_to_dcdc_source(); } -void mx28_enable_output_rail_protection(void) +void mxs_enable_output_rail_protection(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr); @@ -706,17 +707,17 @@ void mx28_enable_output_rail_protection(void) POWER_VDDIOCTRL_PWDN_BRNOUT); } -int mx28_get_vddio_power_source_off(void) +int mxs_get_vddio_power_source_off(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp; if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { tmp = readl(&power_regs->hw_power_vddioctrl); if (tmp & POWER_VDDIOCTRL_DISABLE_FET) { if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == - POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) { return 1; } } @@ -724,7 +725,7 @@ int mx28_get_vddio_power_source_off(void) if (!(readl(&power_regs->hw_power_5vctrl) & POWER_5VCTRL_ENABLE_DCDC)) { if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == - POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) { return 1; } } @@ -734,10 +735,10 @@ int mx28_get_vddio_power_source_off(void) } -int mx28_get_vddd_power_source_off(void) +int mxs_get_vddd_power_source_off(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp; tmp = readl(&power_regs->hw_power_vdddctrl); @@ -765,21 +766,21 @@ int mx28_get_vddd_power_source_off(void) return 0; } -void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) +void mxs_power_set_vddio(uint32_t new_target, uint32_t new_brownout) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t cur_target, diff, bo_int = 0; uint32_t powered_by_linreg = 0; - new_brownout = new_target - new_brownout; + new_brownout = (new_target - new_brownout + 25) / 50; cur_target = readl(&power_regs->hw_power_vddioctrl); cur_target &= POWER_VDDIOCTRL_TRG_MASK; cur_target *= 50; /* 50 mV step*/ cur_target += 2800; /* 2800 mV lowest */ - powered_by_linreg = mx28_get_vddio_power_source_off(); + powered_by_linreg = mxs_get_vddio_power_source_off(); if (new_target > cur_target) { if (powered_by_linreg) { @@ -858,25 +859,25 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) } clrsetbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDDCTRL_BO_OFFSET_MASK, - new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); + POWER_VDDIOCTRL_BO_OFFSET_MASK, + new_brownout << POWER_VDDIOCTRL_BO_OFFSET_OFFSET); } -void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) +void mxs_power_set_vddd(uint32_t new_target, uint32_t new_brownout) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t cur_target, diff, bo_int = 0; uint32_t powered_by_linreg = 0; - new_brownout = new_target - new_brownout; + new_brownout = (new_target - new_brownout + 12) / 25; cur_target = readl(&power_regs->hw_power_vdddctrl); cur_target &= POWER_VDDDCTRL_TRG_MASK; cur_target *= 25; /* 25 mV step*/ cur_target += 800; /* 800 mV lowest */ - powered_by_linreg = mx28_get_vddd_power_source_off(); + powered_by_linreg = mxs_get_vddd_power_source_off(); if (new_target > cur_target) { if (powered_by_linreg) { bo_int = readl(&power_regs->hw_power_vdddctrl); @@ -959,31 +960,31 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); } -void mx28_setup_batt_detect(void) +void mxs_setup_batt_detect(void) { - mx28_lradc_init(); - mx28_lradc_enable_batt_measurement(); + mxs_lradc_init(); + mxs_lradc_enable_batt_measurement(); early_delay(10); } -void mx28_power_init(void) +void mxs_power_init(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; - mx28_power_clock2xtal(); - mx28_power_clear_auto_restart(); - mx28_power_set_linreg(); - mx28_power_setup_5v_detect(); + mxs_power_clock2xtal(); + mxs_power_clear_auto_restart(); + mxs_power_set_linreg(); + mxs_power_setup_5v_detect(); - mx28_setup_batt_detect(); + mxs_setup_batt_detect(); - mx28_power_configure_power_source(); - mx28_enable_output_rail_protection(); + mxs_power_configure_power_source(); + mxs_enable_output_rail_protection(); - mx28_power_set_vddio(3300, 3150); + mxs_power_set_vddio(3300, 3150); - mx28_power_set_vddd(1350, 1200); + mxs_power_set_vddd(1350, 1200); writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ | @@ -996,10 +997,10 @@ void mx28_power_init(void) } #ifdef CONFIG_SPL_MX28_PSWITCH_WAIT -void mx28_power_wait_pswitch(void) +void mxs_power_wait_pswitch(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK)) ; diff --git a/arch/arm/cpu/arm926ejs/mx28/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index e572b786b..7ccd33717 100644 --- a/arch/arm/cpu/arm926ejs/mx28/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -180,14 +180,6 @@ _reset: orr r0,r0,#0xd3 msr cpsr,r0 - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - bl board_init_ll /* @@ -207,40 +199,6 @@ _reset: pop {r0-r12,r14} bx lr -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ - bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ - orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ - orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ - mcr p15, 0, r0, c1, c0, 0 - - mov pc, lr /* back to my caller */ - - .align 5 -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - _hang: ldr sp, _TEXT_BASE /* switch to abort stack */ 1: diff --git a/arch/arm/cpu/arm926ejs/mx28/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c index 5b73f4a2b..4ed75e604 100644 --- a/arch/arm/cpu/arm926ejs/mx28/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@ -62,11 +62,11 @@ static inline unsigned long us_to_tick(unsigned long us) int timer_init(void) { - struct mx28_timrot_regs *timrot_regs = - (struct mx28_timrot_regs *)MXS_TIMROT_BASE; + struct mxs_timrot_regs *timrot_regs = + (struct mxs_timrot_regs *)MXS_TIMROT_BASE; /* Reset Timers and Rotary Encoder module */ - mx28_reset_block(&timrot_regs->hw_timrot_rotctrl_reg); + mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg); /* Set fixed_count to 0 */ writel(0, &timrot_regs->hw_timrot_fixed_count0); @@ -84,8 +84,8 @@ int timer_init(void) unsigned long long get_ticks(void) { - struct mx28_timrot_regs *timrot_regs = - (struct mx28_timrot_regs *)MXS_TIMROT_BASE; + struct mxs_timrot_regs *timrot_regs = + (struct mxs_timrot_regs *)MXS_TIMROT_BASE; /* Current tick value */ uint32_t now = readl(&timrot_regs->hw_timrot_running_count0); diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd new file mode 100644 index 000000000..c60615a45 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd @@ -0,0 +1,14 @@ +sources { + u_boot_spl="spl/u-boot-spl.bin"; + u_boot="u-boot.bin"; +} + +section (0) { + load u_boot_spl > 0x0000; + load ivt (entry = 0x0014) > 0x8000; + hab call 0x8000; + + load u_boot > 0x40000100; + load ivt (entry = 0x40000100) > 0x8000; + hab call 0x8000; +} diff --git a/arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index 0fccd5296..f8ea38c03 100644 --- a/arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -37,7 +37,7 @@ SECTIONS . = ALIGN(4); .text : { - arch/arm/cpu/arm926ejs/mx28/start.o (.text) + arch/arm/cpu/arm926ejs/mxs/start.o (.text) *(.text) } diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index 792b11dfc..c3948d38f 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -292,7 +292,9 @@ int arch_misc_init(void) writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00); writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04); writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50); + writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00); writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04); + writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c); /* initialize timer */ timer_init_r(); diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 6b2addca1..4fdbee4bc 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -32,8 +32,12 @@ COBJS += cache_v7.o COBJS += cpu.o COBJS += syslib.o +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),) +SOBJS += lowlevel_init.o +endif + SRCS := $(START:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START := $(addprefix $(obj),$(START)) all: $(obj).depend $(START) $(LIB) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 71309a7f4..ecc26717c 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -17,22 +17,100 @@ */ #include <common.h> +#include <errno.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> #include <asm/arch/omap.h> #include <asm/arch/ddr_defs.h> #include <asm/arch/clock.h> +#include <asm/arch/gpio.h> #include <asm/arch/mmc_host_def.h> -#include <asm/arch/common_def.h> +#include <asm/arch/sys_proto.h> #include <asm/io.h> #include <asm/omap_common.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> DECLARE_GLOBAL_DATA_PTR; struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; +static const struct gpio_bank gpio_bank_am33xx[4] = { + { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX }, +}; + +const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; + +/* MII mode defines */ +#define MII_MODE_ENABLE 0x0 +#define RGMII_MODE_ENABLE 0xA + +/* GPIO that controls power to DDR on EVM-SK */ +#define GPIO_DDR_VTT_EN 7 + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static struct am335x_baseboard_id __attribute__((section (".data"))) header; + +static inline int board_is_bone(void) +{ + return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); +} + +static inline int board_is_evm_sk(void) +{ + return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); +} + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + puts("Could not probe the EEPROM; something fundamentally " + "wrong on the I2C bus.\n"); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, + sizeof(header))) { + puts("Could not read the EEPROM; something fundamentally" + " wrong on the I2C bus.\n"); + return -EIO; + } + + if (header.magic != 0xEE3355AA) { + /* + * read the eeprom using i2c again, + * but use only a 1 byte address + */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, + (uchar *)&header, sizeof(header))) { + puts("Could not read the EEPROM; something " + "fundamentally wrong on the I2C bus.\n"); + return -EIO; + } + + if (header.magic != 0xEE3355AA) { + printf("Incorrect magic number (0x%x) in EEPROM\n", + header.magic); + return -EINVAL; + } + } + + return 0; +} + /* UART Defines */ #ifdef CONFIG_SPL_BUILD #define UART_RESET (0x1 << 1) @@ -40,21 +118,17 @@ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; #define UART_SMART_IDLE_EN (0x1 << 0x3) #endif -#ifdef CONFIG_SPL_BUILD -/* Initialize timer */ -static void init_timer(void) +/* + * Determine what type of DDR we have. + */ +static short inline board_memory_type(void) { - /* Reset the Timer */ - writel(0x2, (&timer_base->tscir)); + /* The following boards are known to use DDR3. */ + if (board_is_evm_sk()) + return EMIF_REG_SDRAM_TYPE_DDR3; - /* Wait until the reset is done */ - while (readl(&timer_base->tiocp_cfg) & 1) - ; - - /* Start the Timer */ - writel(0x1, (&timer_base->tclr)); + return EMIF_REG_SDRAM_TYPE_DDR2; } -#endif /* * early system init of muxing and clocks. @@ -92,22 +166,38 @@ void s_init(void) regVal |= UART_SMART_IDLE_EN; writel(regVal, &uart_base->uartsyscfg); - /* Initialize the Timer */ - init_timer(); - preloader_console_init(); - config_ddr(); -#endif + /* Initalize the board header */ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); - /* Enable MMC0 */ - enable_mmc0_pin_mux(); + enable_board_pin_mux(&header); + if (board_is_evm_sk()) { + /* + * EVM SK 1.2A and later use gpio0_7 to enable DDR3. + * This is safe enough to do on older revs. + */ + gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(GPIO_DDR_VTT_EN, 1); + } + + config_ddr(board_memory_type()); +#endif } #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0); + int ret; + + ret = omap_mmc_init(0, 0, 0); + if (ret) + return ret; + + return omap_mmc_init(1, 0, 0); } #endif @@ -116,3 +206,93 @@ void setup_clocks_for_console(void) /* Not yet implemented */ return; } + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = AM335X_CPSW_MDIO_BASE, + .cpsw_base = AM335X_CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + debug("<ethaddr> not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + else + return -1; + } + + if (board_is_bone()) { + writel(MII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = + PHY_INTERFACE_MODE_MII; + } else { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = + PHY_INTERFACE_MODE_RGMII; + } + + return cpsw_register(&cpsw_data); +} +#endif diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index bbb9c1353..2b19506a3 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -24,6 +24,7 @@ #define PRCM_MOD_EN 0x2 #define PRCM_FORCE_WAKEUP 0x2 +#define PRCM_FUNCTL 0x0 #define PRCM_EMIF_CLK_ACTIVITY BIT(2) #define PRCM_L3_GCLK_ACTIVITY BIT(4) @@ -38,7 +39,7 @@ #define CLK_MODE_SEL 0x7 #define CLK_MODE_MASK 0xfffffff8 #define CLK_DIV_SEL 0xFFFFFFE0 - +#define CPGMAC0_IDLE 0x30000 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; @@ -70,6 +71,10 @@ static void enable_interface_clocks(void) writel(PRCM_MOD_EN, &cmper->l4hsclkctrl); while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN) ; + + writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl); + while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN) + ; } /* @@ -118,6 +123,36 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl); while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN) ; + + /* gpio1 module */ + writel(PRCM_MOD_EN, &cmper->gpio1clkctrl); + while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN) + ; + + /* gpio2 module */ + writel(PRCM_MOD_EN, &cmper->gpio2clkctrl); + while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN) + ; + + /* gpio3 module */ + writel(PRCM_MOD_EN, &cmper->gpio3clkctrl); + while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN) + ; + + /* i2c1 */ + writel(PRCM_MOD_EN, &cmper->i2c1clkctrl); + while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN) + ; + + /* Ethernet */ + writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl); + while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL) + ; + + /* spi0 */ + writel(PRCM_MOD_EN, &cmper->spi0clkctrl); + while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN) + ; } static void mpu_pll_config(void) @@ -216,7 +251,7 @@ static void per_pll_config(void) ; } -static void ddr_pll_config(void) +void ddr_pll_config(unsigned int ddrpll_m) { u32 clkmode, clksel, div_m2; @@ -234,7 +269,7 @@ static void ddr_pll_config(void) ; clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N); + clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N); writel(clksel, &cmwkup->clkseldpllddr); div_m2 = div_m2 & CLK_DIV_SEL; @@ -255,11 +290,6 @@ void enable_emif_clocks(void) writel(PRCM_MOD_EN, &cmper->emiffwclkctrl); /* Enable EMIF0 Clock */ writel(PRCM_MOD_EN, &cmper->emifclkctrl); - /* Poll for emif_gclk & L3_G clock are active */ - while ((readl(&cmper->l3clkstctrl) & (PRCM_EMIF_CLK_ACTIVITY | - PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY | - PRCM_L3_GCLK_ACTIVITY)) - ; /* Poll if module is functional */ while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN) ; @@ -273,7 +303,6 @@ void pll_init() mpu_pll_config(); core_pll_config(); per_pll_config(); - ddr_pll_config(); /* Enable the required interconnect clocks */ enable_interface_clocks(); diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index ed982c11e..fd9fc4a72 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -17,13 +17,15 @@ http://www.ti.com/ #include <asm/arch/cpu.h> #include <asm/arch/ddr_defs.h> +#include <asm/arch/sys_proto.h> #include <asm/io.h> +#include <asm/emif.h> /** * Base address for EMIF instances */ -static struct emif_regs *emif_reg = { - (struct emif_regs *)EMIF4_0_CFG_BASE}; +static struct emif_reg_struct *emif_reg = { + (struct emif_reg_struct *)EMIF4_0_CFG_BASE}; /** * Base address for DDR instance @@ -39,109 +41,79 @@ static struct ddr_cmdtctrl *ioctrl_reg = { (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR}; /** - * As a convention, all functions here return 0 on success - * -1 on failure. - */ - -/** * Configure SDRAM */ -int config_sdram(struct sdram_config *cfg) +void config_sdram(const struct emif_regs *regs) { - writel(cfg->sdrcr, &emif_reg->sdrcr); - writel(cfg->sdrcr2, &emif_reg->sdrcr2); - writel(cfg->refresh, &emif_reg->sdrrcr); - writel(cfg->refresh_sh, &emif_reg->sdrrcsr); - - return 0; + writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); + if (regs->zq_config){ + writel(regs->zq_config, &emif_reg->emif_zq_config); + writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + } + writel(regs->sdram_config, &emif_reg->emif_sdram_config); } /** * Set SDRAM timings */ -int set_sdram_timings(struct sdram_timing *t) +void set_sdram_timings(const struct emif_regs *regs) { - writel(t->time1, &emif_reg->sdrtim1); - writel(t->time1_sh, &emif_reg->sdrtim1sr); - writel(t->time2, &emif_reg->sdrtim2); - writel(t->time2_sh, &emif_reg->sdrtim2sr); - writel(t->time3, &emif_reg->sdrtim3); - writel(t->time3_sh, &emif_reg->sdrtim3sr); - - return 0; + writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1); + writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw); + writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2); + writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw); + writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3); + writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw); } /** * Configure DDR PHY */ -int config_ddr_phy(struct ddr_phy_control *p) +void config_ddr_phy(const struct emif_regs *regs) { - writel(p->reg, &emif_reg->ddrphycr); - writel(p->reg_sh, &emif_reg->ddrphycsr); - - return 0; + writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw); } /** * Configure DDR CMD control registers */ -int config_cmd_ctrl(struct cmd_control *cmd) +void config_cmd_ctrl(const struct cmd_control *cmd) { writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio); - writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce); - writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay); writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff); writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout); writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio); - writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce); - writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay); writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff); writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout); writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio); - writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce); - writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay); writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff); writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout); - - return 0; } /** * Configure DDR DATA registers */ -int config_ddr_data(int macrono, struct ddr_data *data) +void config_ddr_data(int macrono, const struct ddr_data *data) { writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0); - writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1); - writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0); - writel(data->datawdsratio1, &ddr_reg[macrono]->dt0wdsratio1); - writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0); - writel(data->datawiratio1, &ddr_reg[macrono]->dt0wiratio1); writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0); - writel(data->datagiratio1, &ddr_reg[macrono]->dt0giratio1); - writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0); - writel(data->datafwsratio1, &ddr_reg[macrono]->dt0fwsratio1); - writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0); - writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1); - + writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0); writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0); - - return 0; } -int config_io_ctrl(struct ddr_ioctrl *ioctrl) +void config_io_ctrl(unsigned long val) { - writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl); - writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl); - writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl); - writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl); - writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl); - - return 0; + writel(val, &ioctrl_reg->cm0ioctl); + writel(val, &ioctrl_reg->cm1ioctl); + writel(val, &ioctrl_reg->cm2ioctl); + writel(val, &ioctrl_reg->dt0ioctl); + writel(val, &ioctrl_reg->dt1ioctl); } diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 2f4164df8..b2d7c0d95 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -21,15 +21,12 @@ #include <asm/arch/ddr_defs.h> #include <asm/arch/hardware.h> #include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> #include <asm/io.h> +#include <asm/emif.h> DECLARE_GLOBAL_DATA_PTR; -struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR; -struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR; -struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; - - int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ @@ -47,58 +44,80 @@ void dram_init_banksize(void) #ifdef CONFIG_SPL_BUILD -static void data_macro_config(int dataMacroNum) -{ - struct ddr_data data; +static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR; +static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; - data.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) - |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)); - data.datardsratio1 = DDR2_RD_DQS>>2; - data.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) - |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)); - data.datawdsratio1 = DDR2_WR_DQS>>2; - data.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) - |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)); - data.datawiratio1 = DDR2_PHY_WRLVL>>2; - data.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) - |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)); - data.datagiratio1 = DDR2_PHY_GATELVL>>2; - data.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) - |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)); - data.datafwsratio1 = DDR2_PHY_FIFO_WE>>2; - data.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) - |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)); - data.datawrsratio1 = DDR2_PHY_WR_DATA>>2; - data.datadldiff0 = PHY_DLL_LOCK_DIFF; +static const struct ddr_data ddr2_data = { + .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) + |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)), + .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) + |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)), + .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) + |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)), + .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) + |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)), + .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) + |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), + .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) + |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), + .datauserank0delay = DDR2_PHY_RANK0_DELAY, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; - config_ddr_data(dataMacroNum, &data); -} +static const struct cmd_control ddr2_cmd_ctrl_data = { + .cmd0csratio = DDR2_RATIO, + .cmd0dldiff = DDR2_DLL_LOCK_DIFF, + .cmd0iclkout = DDR2_INVERT_CLKOUT, -static void cmd_macro_config(void) -{ - struct cmd_control cmd; + .cmd1csratio = DDR2_RATIO, + .cmd1dldiff = DDR2_DLL_LOCK_DIFF, + .cmd1iclkout = DDR2_INVERT_CLKOUT, - cmd.cmd0csratio = DDR2_RATIO; - cmd.cmd0csforce = CMD_FORCE; - cmd.cmd0csdelay = CMD_DELAY; - cmd.cmd0dldiff = DDR2_DLL_LOCK_DIFF; - cmd.cmd0iclkout = DDR2_INVERT_CLKOUT; + .cmd2csratio = DDR2_RATIO, + .cmd2dldiff = DDR2_DLL_LOCK_DIFF, + .cmd2iclkout = DDR2_INVERT_CLKOUT, +}; - cmd.cmd1csratio = DDR2_RATIO; - cmd.cmd1csforce = CMD_FORCE; - cmd.cmd1csdelay = CMD_DELAY; - cmd.cmd1dldiff = DDR2_DLL_LOCK_DIFF; - cmd.cmd1iclkout = DDR2_INVERT_CLKOUT; +static const struct emif_regs ddr2_emif_reg_data = { + .sdram_config = DDR2_EMIF_SDCFG, + .ref_ctrl = DDR2_EMIF_SDREF, + .sdram_tim1 = DDR2_EMIF_TIM1, + .sdram_tim2 = DDR2_EMIF_TIM2, + .sdram_tim3 = DDR2_EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY, +}; - cmd.cmd2csratio = DDR2_RATIO; - cmd.cmd2csforce = CMD_FORCE; - cmd.cmd2csdelay = CMD_DELAY; - cmd.cmd2dldiff = DDR2_DLL_LOCK_DIFF; - cmd.cmd2iclkout = DDR2_INVERT_CLKOUT; +static const struct ddr_data ddr3_data = { + .datardsratio0 = DDR3_RD_DQS, + .datawdsratio0 = DDR3_WR_DQS, + .datafwsratio0 = DDR3_PHY_FIFO_WE, + .datawrsratio0 = DDR3_PHY_WR_DATA, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; - config_cmd_ctrl(&cmd); +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = DDR3_RATIO, + .cmd0dldiff = DDR3_DLL_LOCK_DIFF, + .cmd0iclkout = DDR3_INVERT_CLKOUT, -} + .cmd1csratio = DDR3_RATIO, + .cmd1dldiff = DDR3_DLL_LOCK_DIFF, + .cmd1iclkout = DDR3_INVERT_CLKOUT, + + .cmd2csratio = DDR3_RATIO, + .cmd2dldiff = DDR3_DLL_LOCK_DIFF, + .cmd2iclkout = DDR3_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = DDR3_EMIF_SDCFG, + .ref_ctrl = DDR3_EMIF_SDREF, + .sdram_tim1 = DDR3_EMIF_TIM1, + .sdram_tim2 = DDR3_EMIF_TIM2, + .sdram_tim3 = DDR3_EMIF_TIM3, + .zq_config = DDR3_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY, +}; static void config_vtp(void) { @@ -115,87 +134,46 @@ static void config_vtp(void) ; } -static void config_emif_ddr2(void) +void config_ddr(short ddr_type) { - int i; - int ret; - struct sdram_config cfg; - struct sdram_timing tmg; - struct ddr_phy_control phyc; - - /*Program EMIF0 CFG Registers*/ - phyc.reg = EMIF_READ_LATENCY; - phyc.reg_sh = EMIF_READ_LATENCY; - phyc.reg2 = EMIF_READ_LATENCY; - - tmg.time1 = EMIF_TIM1; - tmg.time1_sh = EMIF_TIM1; - tmg.time2 = EMIF_TIM2; - tmg.time2_sh = EMIF_TIM2; - tmg.time3 = EMIF_TIM3; - tmg.time3_sh = EMIF_TIM3; - - cfg.sdrcr = EMIF_SDCFG; - cfg.sdrcr2 = EMIF_SDCFG; - cfg.refresh = 0x00004650; - cfg.refresh_sh = 0x00004650; - - /* Program EMIF instance */ - ret = config_ddr_phy(&phyc); - if (ret < 0) - printf("Couldn't configure phyc\n"); + int ddr_pll, ioctrl_val; + const struct emif_regs *emif_regs; + const struct ddr_data *ddr_data; + const struct cmd_control *cmd_ctrl_data; - ret = config_sdram(&cfg); - if (ret < 0) - printf("Couldn't configure SDRAM\n"); - - ret = set_sdram_timings(&tmg); - if (ret < 0) - printf("Couldn't configure timings\n"); - - /* Delay */ - for (i = 0; i < 5000; i++) - ; - - cfg.refresh = EMIF_SDREF; - cfg.refresh_sh = EMIF_SDREF; - cfg.sdrcr = EMIF_SDCFG; - cfg.sdrcr2 = EMIF_SDCFG; - - ret = config_sdram(&cfg); - if (ret < 0) - printf("Couldn't configure SDRAM\n"); -} - -void config_ddr(void) -{ - int data_macro_0 = 0; - int data_macro_1 = 1; - struct ddr_ioctrl ioctrl; + if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) { + ddr_pll = 266; + cmd_ctrl_data = &ddr2_cmd_ctrl_data; + ddr_data = &ddr2_data; + ioctrl_val = DDR2_IOCTRL_VALUE; + emif_regs = &ddr2_emif_reg_data; + } else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) { + ddr_pll = 303; + cmd_ctrl_data = &ddr3_cmd_ctrl_data; + ddr_data = &ddr3_data; + ioctrl_val = DDR3_IOCTRL_VALUE; + emif_regs = &ddr3_emif_reg_data; + } else { + puts("Unknown memory type"); + hang(); + } enable_emif_clocks(); - + ddr_pll_config(ddr_pll); config_vtp(); + config_cmd_ctrl(cmd_ctrl_data); - cmd_macro_config(); - - data_macro_config(data_macro_0); - data_macro_config(data_macro_1); + config_ddr_data(0, ddr_data); + config_ddr_data(1, ddr_data); - writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0); - writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0); + config_io_ctrl(ioctrl_val); - ioctrl.cmd1ctl = DDR_IOCTRL_VALUE; - ioctrl.cmd2ctl = DDR_IOCTRL_VALUE; - ioctrl.cmd3ctl = DDR_IOCTRL_VALUE; - ioctrl.data1ctl = DDR_IOCTRL_VALUE; - ioctrl.data2ctl = DDR_IOCTRL_VALUE; + /* Set CKE to be controlled by EMIF/DDR PHY */ + writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); - config_io_ctrl(&ioctrl); - - writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl); - writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl); - - config_emif_ddr2(); + /* Program EMIF instance */ + config_ddr_phy(emif_regs); + set_sdram_timings(emif_regs); + config_sdram(emif_regs); } #endif diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index 560c084dc..5407cb68a 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -26,8 +26,6 @@ PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # supported by more tool-chains PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5) PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7) -PF_CPPFLAGS_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,) -PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_NO_UNALIGNED) # ========================================================================= # diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index c6fa8ef13..39a80237c 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -36,13 +36,9 @@ #include <asm/system.h> #include <asm/cache.h> #include <asm/armv7.h> +#include <linux/compiler.h> -void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3) -{ -} - -void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) - __attribute__((weak, alias("save_boot_params_default"))); +void __weak cpu_cache_initialization(void){} int cleanup_before_linux(void) { @@ -81,5 +77,10 @@ int cleanup_before_linux(void) */ invalidate_dcache_all(); + /* + * Some CPU need more cache attention before starting the kernel. + */ + cpu_cache_initialization(); + return 0; } diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index f7829b2cc..4f3b451be 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq; + unsigned int freq, pll_div2_sel, fout_sel; switch (pllreg) { case APLL: @@ -115,6 +115,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg) r = readl(&clk->vpll_con0); k = readl(&clk->vpll_con1); break; + case BPLL: + r = readl(&clk->bpll_con0); + break; default: printf("Unsupported PLL (%d)\n", pllreg); return 0; @@ -125,8 +128,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg) * MPLL_CON: MIDV [25:16] * EPLL_CON: MIDV [24:16] * VPLL_CON: MIDV [24:16] + * BPLL_CON: MIDV [25:16] */ - if (pllreg == APLL || pllreg == MPLL) + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) mask = 0x3ff; else mask = 0x1ff; @@ -155,6 +159,29 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } + /* According to the user manual, in EVT1 MPLL and BPLL always gives + * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ + if (pllreg == MPLL || pllreg == BPLL) { + pll_div2_sel = readl(&clk->pll_div2_sel); + + switch (pllreg) { + case MPLL: + fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + & MPLL_FOUT_SEL_MASK; + break; + case BPLL: + fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT) + & BPLL_FOUT_SEL_MASK; + break; + default: + fout_sel = -1; + break; + } + + if (fout_sel == 0) + fout /= 2; + } + return fout; } @@ -456,6 +483,48 @@ static unsigned long exynos4_get_lcd_clk(void) return pclk; } +/* get_lcd_clk: return lcd clock frequency */ +static unsigned long exynos5_get_lcd_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long pclk, sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_LCD0 + * FIMD0_SEL [3:0] + */ + sel = readl(&clk->src_disp1_0); + sel = sel & 0xf; + + /* + * 0x6: SCLK_MPLL + * 0x7: SCLK_EPLL + * 0x8: SCLK_VPLL + */ + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + /* + * CLK_DIV_LCD0 + * FIMD0_RATIO [3:0] + */ + ratio = readl(&clk->div_disp1_0); + ratio = ratio & 0xf; + + pclk = sclk / (ratio + 1); + + return pclk; +} + void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -518,6 +587,68 @@ void exynos4_set_lcd_clk(void) writel(cfg, &clk->div_lcd0); } +void exynos5_set_lcd_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned int cfg = 0; + + /* + * CLK_GATE_BLOCK + * CLK_CAM [0] + * CLK_TV [1] + * CLK_MFC [2] + * CLK_G3D [3] + * CLK_LCD0 [4] + * CLK_LCD1 [5] + * CLK_GPS [7] + */ + cfg = readl(&clk->gate_block); + cfg |= 1 << 4; + writel(cfg, &clk->gate_block); + + /* + * CLK_SRC_LCD0 + * FIMD0_SEL [3:0] + * MDNIE0_SEL [7:4] + * MDNIE_PWM0_SEL [8:11] + * MIPI0_SEL [12:15] + * set lcd0 src clock 0x6: SCLK_MPLL + */ + cfg = readl(&clk->src_disp1_0); + cfg &= ~(0xf); + cfg |= 0x8; + writel(cfg, &clk->src_disp1_0); + + /* + * CLK_GATE_IP_LCD0 + * CLK_FIMD0 [0] + * CLK_MIE0 [1] + * CLK_MDNIE0 [2] + * CLK_DSIM0 [3] + * CLK_SMMUFIMD0 [4] + * CLK_PPMULCD0 [5] + * Gating all clocks for FIMD0 + */ + cfg = readl(&clk->gate_ip_disp1); + cfg |= 1 << 0; + writel(cfg, &clk->gate_ip_disp1); + + /* + * CLK_DIV_LCD0 + * FIMD0_RATIO [3:0] + * MDNIE0_RATIO [7:4] + * MDNIE_PWM0_RATIO [11:8] + * MDNIE_PWM_PRE_RATIO [15:12] + * MIPI0_RATIO [19:16] + * MIPI0_PRE_RATIO [23:20] + * set fimd ratio + */ + cfg &= ~(0xf); + cfg |= 0x0; + writel(cfg, &clk->div_disp1_0); +} + void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -656,13 +787,15 @@ unsigned long get_lcd_clk(void) if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else - return 0; + return exynos5_get_lcd_clk(); } void set_lcd_clk(void) { if (cpu_is_exynos4()) exynos4_set_lcd_clk(); + else + exynos5_set_lcd_clk(); } void set_mipi_clk(void) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index d28f05557..7776add9d 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -40,8 +40,8 @@ static void exynos5_uart_config(int peripheral) count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->a0; - start = 4; + bank = &gpio1->d0; + start = 0; count = 4; break; case PERIPH_ID_UART2: @@ -66,23 +66,27 @@ static int exynos5_mmc_config(int peripheral, int flags) struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); struct s5p_gpio_bank *bank, *bank_ext; - int i; + int i, start = 0, gpio_func = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: bank = &gpio1->c0; bank_ext = &gpio1->c1; + start = 0; + gpio_func = GPIO_FUNC(0x2); break; case PERIPH_ID_SDMMC1: - bank = &gpio1->c1; + bank = &gpio1->c2; bank_ext = NULL; break; case PERIPH_ID_SDMMC2: - bank = &gpio1->c2; - bank_ext = &gpio1->c3; + bank = &gpio1->c3; + bank_ext = &gpio1->c4; + start = 3; + gpio_func = GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC3: - bank = &gpio1->c3; + bank = &gpio1->c4; bank_ext = NULL; break; } @@ -92,8 +96,8 @@ static int exynos5_mmc_config(int peripheral, int flags) return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); + for (i = start; i <= (start + 3); i++) { + s5p_gpio_cfg_pin(bank_ext, i, gpio_func); s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); } diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index 4116781a3..d4bce6d4d 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -74,3 +74,24 @@ void set_usbhost_phy_ctrl(unsigned int enable) if (cpu_is_exynos5()) exynos5_set_usbhost_phy_ctrl(enable); } + +static void exynos5_dp_phy_control(unsigned int enable) +{ + unsigned int cfg; + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + cfg = readl(&power->dptx_phy_control); + if (enable) + cfg |= EXYNOS_DP_PHY_ENABLE; + else + cfg &= ~EXYNOS_DP_PHY_ENABLE; + + writel(cfg, &power->dptx_phy_control); +} + +void set_dp_phy_ctrl(unsigned int enable) +{ + if (cpu_is_exynos5()) + exynos5_dp_phy_control(enable); +} diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c index dcfcec22d..ab65b8d3a 100644 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ b/arch/arm/cpu/armv7/exynos/soc.c @@ -28,3 +28,11 @@ void reset_cpu(ulong addr) { writel(0x1, samsung_get_base_swreset()); } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/cpu/armv7/exynos/system.c b/arch/arm/cpu/armv7/exynos/system.c index 4426611d1..8424c57e9 100644 --- a/arch/arm/cpu/armv7/exynos/system.c +++ b/arch/arm/cpu/armv7/exynos/system.c @@ -62,8 +62,26 @@ static void exynos4_set_system_display(void) writel(cfg, &sysreg->display_ctrl); } +static void exynos5_set_system_display(void) +{ + struct exynos5_sysreg *sysreg = + (struct exynos5_sysreg *)samsung_get_base_sysreg(); + unsigned int cfg = 0; + + /* + * system register path set + * 0: MIE/MDNIE + * 1: FIMD Bypass + */ + cfg = readl(&sysreg->disp1blk_cfg); + cfg |= (1 << 15); + writel(cfg, &sysreg->disp1blk_cfg); +} + void set_system_display_ctrl(void) { if (cpu_is_exynos4()) exynos4_set_system_display(); + else + exynos5_set_system_display(); } diff --git a/arch/arm/cpu/armv7/highbank/Makefile b/arch/arm/cpu/armv7/highbank/Makefile index 917c3a36b..76faeb0fe 100644 --- a/arch/arm/cpu/armv7/highbank/Makefile +++ b/arch/arm/cpu/armv7/highbank/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS := timer.o bootcount.o +COBJS := timer.o SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/highbank/bootcount.c b/arch/arm/cpu/armv7/highbank/bootcount.c deleted file mode 100644 index 9ca06567a..000000000 --- a/arch/arm/cpu/armv7/highbank/bootcount.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2011 Calxeda, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <common.h> -#include <asm/io.h> - -#ifdef CONFIG_BOOTCOUNT_LIMIT -void bootcount_store(ulong a) -{ - writel((BOOTCOUNT_MAGIC & 0xffff0000) | a, CONFIG_SYS_BOOTCOUNT_ADDR); -} - -ulong bootcount_load(void) -{ - u32 tmp = readl(CONFIG_SYS_BOOTCOUNT_ADDR); - - if ((tmp & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) - return 0; - else - return tmp & 0x0000ffff; -} -#endif diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c deleted file mode 100644 index b3195dd6f..000000000 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * (C) Copyright 2007 - * Sascha Hauer, Pengutronix - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/errno.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/crm_regs.h> - -#ifdef CONFIG_FSL_ESDHC -#include <fsl_esdhc.h> -#endif - -char *get_reset_cause(void) -{ - u32 cause; - struct src *src_regs = (struct src *)SRC_BASE_ADDR; - - cause = readl(&src_regs->srsr); - writel(cause, &src_regs->srsr); - - switch (cause) { - case 0x00001: - case 0x00011: - return "POR"; - case 0x00004: - return "CSU"; - case 0x00008: - return "IPP USER"; - case 0x00010: - return "WDOG"; - case 0x00020: - return "JTAG HIGH-Z"; - case 0x00040: - return "JTAG SW"; - case 0x10000: - return "WARM BOOT"; - default: - return "unknown reset"; - } -} - -#if defined(CONFIG_DISPLAY_CPUINFO) - -static char *get_imx_type(u32 imxtype) -{ - switch (imxtype) { - case 0x63: - return "6Q"; /* Quad-core version of the mx6 */ - case 0x61: - return "6DS"; /* Dual/Solo version of the mx6 */ - case 0x60: - return "6SL"; /* Solo-Lite version of the mx6 */ - case 0x51: - return "51"; - case 0x53: - return "53"; - default: - return "unknown"; - } -} - -int print_cpuinfo(void) -{ - u32 cpurev; - - cpurev = get_cpu_rev(); - - printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", - get_imx_type((cpurev & 0xFF000) >> 12), - (cpurev & 0x000F0) >> 4, - (cpurev & 0x0000F) >> 0, - mxc_get_clock(MXC_ARM_CLK) / 1000000); - printf("Reset cause: %s\n", get_reset_cause()); - return 0; -} -#endif - -int cpu_eth_init(bd_t *bis) -{ - int rc = -ENODEV; - -#if defined(CONFIG_FEC_MXC) - rc = fecmxc_initialize(bis); -#endif - - return rc; -} - -/* - * Initializes on-chip MMC controllers. - * to override, implement board_mmc_init() - */ -int cpu_mmc_init(bd_t *bis) -{ -#ifdef CONFIG_FSL_ESDHC - return fsl_esdhc_mmc_init(bis); -#else - return 0; -#endif -} - -void reset_cpu(ulong addr) -{ - __raw_writew(4, WDOG1_BASE_ADDR); -} - -u32 get_ahb_clk(void) -{ - struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - u32 reg, ahb_podf; - - reg = __raw_readl(&imx_ccm->cbcdr); - reg &= MXC_CCM_CBCDR_AHB_PODF_MASK; - ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; - - return get_periph_clk() / (ahb_podf + 1); -} diff --git a/arch/arm/cpu/armv7/imx-common/i2c.c b/arch/arm/cpu/armv7/imx-common/i2c.c deleted file mode 100644 index da2b26f43..000000000 --- a/arch/arm/cpu/armv7/imx-common/i2c.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2012 Boundary Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/errno.h> -#include <asm/gpio.h> -#include <asm/imx-common/mxc_i2c.h> -#include <watchdog.h> - -static int force_idle_bus(void *priv) -{ - int i; - int sda, scl; - ulong elapsed, start_time; - struct i2c_pads_info *p = (struct i2c_pads_info *)priv; - int ret = 0; - - gpio_direction_input(p->sda.gp); - gpio_direction_input(p->scl.gp); - - imx_iomux_v3_setup_pad(p->sda.gpio_mode); - imx_iomux_v3_setup_pad(p->scl.gpio_mode); - - sda = gpio_get_value(p->sda.gp); - scl = gpio_get_value(p->scl.gp); - if ((sda & scl) == 1) - goto exit; /* Bus is idle already */ - - printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__, - sda, scl, p->sda.gp, p->scl.gp); - /* Send high and low on the SCL line */ - for (i = 0; i < 9; i++) { - gpio_direction_output(p->scl.gp, 0); - udelay(50); - gpio_direction_input(p->scl.gp); - udelay(50); - } - start_time = get_timer(0); - for (;;) { - sda = gpio_get_value(p->sda.gp); - scl = gpio_get_value(p->scl.gp); - if ((sda & scl) == 1) - break; - WATCHDOG_RESET(); - elapsed = get_timer(start_time); - if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */ - ret = -EBUSY; - printf("%s: failed to clear bus, sda=%d scl=%d\n", - __func__, sda, scl); - break; - } - } -exit: - imx_iomux_v3_setup_pad(p->sda.i2c_mode); - imx_iomux_v3_setup_pad(p->scl.i2c_mode); - return ret; -} - -static void * const i2c_bases[] = { - (void *)I2C1_BASE_ADDR, - (void *)I2C2_BASE_ADDR, -#ifdef I2C3_BASE_ADDR - (void *)I2C3_BASE_ADDR, -#endif -}; - -/* i2c_index can be from 0 - 2 */ -void setup_i2c(unsigned i2c_index, int speed, int slave_addr, - struct i2c_pads_info *p) -{ - if (i2c_index >= ARRAY_SIZE(i2c_bases)) - return; - /* Enable i2c clock */ - enable_i2c_clk(1, i2c_index); - /* Make sure bus is idle */ - force_idle_bus(p); - bus_i2c_init(i2c_bases[i2c_index], speed, slave_addr, - force_idle_bus, p); -} diff --git a/arch/arm/cpu/armv7/imx-common/iomux-v3.c b/arch/arm/cpu/armv7/imx-common/iomux-v3.c deleted file mode 100644 index da093fbe1..000000000 --- a/arch/arm/cpu/armv7/imx-common/iomux-v3.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Based on the iomux-v3.c from Linux kernel: - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * - * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#include <common.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/imx-common/iomux-v3.h> - -static void *base = (void *)IOMUXC_BASE_ADDR; - -/* - * configures a single pad in the iomuxer - */ -int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) -{ - u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; - u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; - u32 sel_input_ofs = - (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; - u32 sel_input = - (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; - u32 pad_ctrl_ofs = - (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; - u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; - - if (mux_ctrl_ofs) - __raw_writel(mux_mode, base + mux_ctrl_ofs); - - if (sel_input_ofs) - __raw_writel(sel_input, base + sel_input_ofs); - - if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) - __raw_writel(pad_ctrl, base + pad_ctrl_ofs); - - return 0; -} - -int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) -{ - iomux_v3_cfg_t *p = pad_list; - int i; - int ret; - - for (i = 0; i < count; i++) { - ret = imx_iomux_v3_setup_pad(*p); - if (ret) - return ret; - p++; - } - return 0; -} diff --git a/arch/arm/cpu/armv7/imx-common/timer.c b/arch/arm/cpu/armv7/imx-common/timer.c deleted file mode 100644 index 1645ff83f..000000000 --- a/arch/arm/cpu/armv7/imx-common/timer.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2007 - * Sascha Hauer, Pengutronix - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <div64.h> -#include <asm/arch/imx-regs.h> - -/* General purpose timers registers */ -struct mxc_gpt { - unsigned int control; - unsigned int prescaler; - unsigned int status; - unsigned int nouse[6]; - unsigned int counter; -}; - -static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR; - -/* General purpose timers bitfields */ -#define GPTCR_SWR (1 << 15) /* Software reset */ -#define GPTCR_FRR (1 << 9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ -#define GPTCR_TEN 1 /* Timer enable */ -#define CLK_32KHZ 32768 /* 32Khz input */ - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp (gd->tbl) -#define lastinc (gd->lastinc) - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, CLK_32KHZ); - - return tick; -} - -static inline unsigned long long us_to_tick(unsigned long long usec) -{ - usec *= CLK_32KHZ; - do_div(usec, 1000000); - - return usec; -} - -int timer_init(void) -{ - int i; - ulong val; - - /* setup GP Timer 1 */ - __raw_writel(GPTCR_SWR, &cur_gpt->control); - - /* We have no udelay by now */ - for (i = 0; i < 100; i++) - __raw_writel(0, &cur_gpt->control); - - __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ - - /* Freerun Mode, PERCLK1 input */ - i = __raw_readl(&cur_gpt->control); - __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control); - - val = __raw_readl(&cur_gpt->counter); - lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ); - timestamp = 0; - - return 0; -} - -unsigned long long get_ticks(void) -{ - ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */ - - if (now >= lastinc) { - /* - * normal mode (non roll) - * move stamp forward with absolut diff ticks - */ - timestamp += (now - lastinc); - } else { - /* we have rollover of incrementer */ - timestamp += (0xFFFFFFFF - lastinc) + now; - } - lastinc = now; - return timestamp; -} - -ulong get_timer_masked(void) -{ - /* - * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ - * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in - * 5 * 10^6 days - long enough. - */ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds AND preserve advance timstamp value */ -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = us_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - /*NOP*/; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CLK_32KHZ; -} diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S new file mode 100644 index 000000000..0d45528e9 --- /dev/null +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -0,0 +1,51 @@ +/* + * A lowlevel_init function that sets up the stack to call a C function to + * perform further init. + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Author : + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + /* + * Setup a temporary stack + */ + ldr sp, =CONFIG_SYS_INIT_SP_ADDR + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ + + /* + * Save the old lr(passed in ip) and the current lr to stack + */ + push {ip, lr} + + /* + * go setup pll, mux, memory + */ + bl s_init + pop {ip, pc} +ENDPROC(lowlevel_init) diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 683a7b53a..a40b84fee 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -36,9 +36,9 @@ /* reconfigure L2 cache aux control reg */ mov r0, #0xC0 /* tag RAM */ add r0, r0, #0x4 /* data RAM */ - orr r0, r0, #(1 << 24) /* disable write allocate delay */ - orr r0, r0, #(1 << 23) /* disable write allocate combine */ - orr r0, r0, #(1 << 22) /* disable write allocate */ + orr r0, r0, #1 << 24 /* disable write allocate delay */ + orr r0, r0, #1 << 23 /* disable write allocate combine */ + orr r0, r0, #1 << 22 /* disable write allocate */ #if defined(CONFIG_MX51) ldr r1, =0x0 @@ -46,7 +46,7 @@ cmp r3, #0x10 /* disable write combine for TO 2 and lower revs */ - orrls r0, r0, #(1 << 25) + orrls r0, r0, #1 << 25 #endif mcr 15, 1, r0, c9, c0, 2 @@ -247,9 +247,9 @@ movhi r1, #0 #else mov r1, #0 - #endif str r1, [r0, #CLKCTL_CACRR] + /* Switch ARM back to PLL 1 */ mov r1, #0 str r1, [r0, #CLKCTL_CCSR] @@ -288,9 +288,9 @@ /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR ldr r1, =0x00808145 - orr r1, r1, #(2 << 10) - orr r1, r1, #(0 << 16) - orr r1, r1, #(1 << 19) + orr r1, r1, #2 << 10 + orr r1, r1, #0 << 16 + orr r1, r1, #1 << 19 str r1, [r0, #CLKCTL_CBCDR] ldr r1, =0x00016154 @@ -331,10 +331,10 @@ ENTRY(lowlevel_init) #if defined(CONFIG_MX51) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] - orr r1, r1, #(1 << 23) + orr r1, r1, #1 << 23 str r1, [r0, #0x0] ldr r1, [r0, #0x4] - orr r1, r1, #(1 << 23) + orr r1, r1, #1 << 23 str r1, [r0, #0x4] #endif @@ -351,16 +351,16 @@ ENTRY(lowlevel_init) ENDPROC(lowlevel_init) /* Board level setting value */ -W_DP_OP_864: .word DP_OP_864 -W_DP_MFD_864: .word DP_MFD_864 -W_DP_MFN_864: .word DP_MFN_864 -W_DP_MFN_800_DIT: .word DP_MFN_800_DIT -W_DP_OP_800: .word DP_OP_800 -W_DP_MFD_800: .word DP_MFD_800 -W_DP_MFN_800: .word DP_MFN_800 -W_DP_OP_665: .word DP_OP_665 -W_DP_MFD_665: .word DP_MFD_665 -W_DP_MFN_665: .word DP_MFN_665 -W_DP_OP_216: .word DP_OP_216 -W_DP_MFD_216: .word DP_MFD_216 -W_DP_MFN_216: .word DP_MFN_216 +W_DP_OP_864: .word DP_OP_864 +W_DP_MFD_864: .word DP_MFD_864 +W_DP_MFN_864: .word DP_MFN_864 +W_DP_MFN_800_DIT: .word DP_MFN_800_DIT +W_DP_OP_800: .word DP_OP_800 +W_DP_MFD_800: .word DP_MFD_800 +W_DP_MFN_800: .word DP_MFN_800 +W_DP_OP_665: .word DP_OP_665 +W_DP_MFD_665: .word DP_MFD_665 +W_DP_MFN_665: .word DP_MFN_665 +W_DP_OP_216: .word DP_OP_216 +W_DP_MFD_216: .word DP_MFD_216 +W_DP_MFN_216: .word DP_MFN_216 diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 3f5a4f726..263658aa4 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -30,6 +30,7 @@ #include <asm/errno.h> #include <asm/io.h> +#include <asm/imx-common/boot_mode.h> #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53)) #error "CPU_TYPE not defined" @@ -71,6 +72,14 @@ u32 get_cpu_rev(void) return system_rev; } +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif + #if defined(CONFIG_FEC_MXC) void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { @@ -115,3 +124,33 @@ void set_chipselect_size(int const cs_size) writel(reg, &iomuxc_regs->gpr1); } + +#ifdef CONFIG_MX53 +void boot_mode_apply(unsigned cfg_val) +{ + writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr); +} +/* + * cfg_val will be used for + * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] + * + * If bit 28 of LPGR is set upon watchdog reset, + * bits[25:0] of LPGR will move to SBMR. + */ +const struct boot_mode soc_boot_modes[] = { + {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, + /* usb or serial download */ + {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)}, + {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)}, + {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)}, + {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)}, + {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)}, + {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)}, + /* 4 bit bus width */ + {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)}, + {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)}, + {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)}, + {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)}, + {NULL, 0}, +}; +#endif diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 84b458c7e..7380ffe46 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -29,6 +29,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#include <asm/imx-common/boot_mode.h> u32 get_cpu_rev(void) { @@ -141,3 +142,38 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) } #endif + +void boot_mode_apply(unsigned cfg_val) +{ + unsigned reg; + struct src_regs *psrc = (struct src_regs *)SRC_BASE_ADDR; + writel(cfg_val, &psrc->gpr9); + reg = readl(&psrc->gpr10); + if (cfg_val) + reg |= 1 << 28; + else + reg &= ~(1 << 28); + writel(reg, &psrc->gpr10); +} +/* + * cfg_val will be used for + * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] + * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] + * to SBMR1, which will determine the boot device. + */ +const struct boot_mode soc_boot_modes[] = { + {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, + /* reserved value should start rom usb */ + {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)}, + {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, + {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, + {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, + {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, + {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, + /* 4 bit bus width */ + {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 2a6625f1c..d37b22d98 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -29,9 +29,6 @@ SOBJS := reset.o COBJS := timer.o COBJS += utils.o -ifdef CONFIG_OMAP -COBJS += gpio.o -endif ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) COBJS += hwinit-common.o diff --git a/arch/arm/cpu/armv7/omap-common/gpio.c b/arch/arm/cpu/armv7/omap-common/gpio.c deleted file mode 100644 index fc89f2a42..000000000 --- a/arch/arm/cpu/armv7/omap-common/gpio.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * This work is derived from the linux 2.6.27 kernel source - * To fetch, use the kernel repository - * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git - * Use the v2.6.27 tag. - * - * Below is the original's header including its copyright - * - * linux/arch/arm/plat-omap/gpio.c - * - * Support functions for OMAP GPIO - * - * Copyright (C) 2003-2005 Nokia Corporation - * Written by Juha Yrjölä <juha.yrjola@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <common.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/errno.h> - -#define OMAP_GPIO_DIR_OUT 0 -#define OMAP_GPIO_DIR_IN 1 - -static inline const struct gpio_bank *get_gpio_bank(int gpio) -{ - return &omap_gpio_bank[gpio >> 5]; -} - -static inline int get_gpio_index(int gpio) -{ - return gpio & 0x1f; -} - -static inline int gpio_valid(int gpio) -{ - if (gpio < 0) - return -1; - if (gpio < 192) - return 0; - return -1; -} - -static int check_gpio(int gpio) -{ - if (gpio_valid(gpio) < 0) { - printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); - return -1; - } - return 0; -} - -static void _set_gpio_direction(const struct gpio_bank *bank, int gpio, - int is_input) -{ - void *reg = bank->base; - u32 l; - - switch (bank->method) { - case METHOD_GPIO_24XX: - reg += OMAP_GPIO_OE; - break; - default: - return; - } - l = __raw_readl(reg); - if (is_input) - l |= 1 << gpio; - else - l &= ~(1 << gpio); - __raw_writel(l, reg); -} - -/** - * Get the direction of the GPIO by reading the GPIO_OE register - * corresponding to the specified bank. - */ -static int _get_gpio_direction(const struct gpio_bank *bank, int gpio) -{ - void *reg = bank->base; - u32 v; - - switch (bank->method) { - case METHOD_GPIO_24XX: - reg += OMAP_GPIO_OE; - break; - default: - return -1; - } - - v = __raw_readl(reg); - - if (v & (1 << gpio)) - return OMAP_GPIO_DIR_IN; - else - return OMAP_GPIO_DIR_OUT; -} - -static void _set_gpio_dataout(const struct gpio_bank *bank, int gpio, - int enable) -{ - void *reg = bank->base; - u32 l = 0; - - switch (bank->method) { - case METHOD_GPIO_24XX: - if (enable) - reg += OMAP_GPIO_SETDATAOUT; - else - reg += OMAP_GPIO_CLEARDATAOUT; - l = 1 << gpio; - break; - default: - printf("omap3-gpio unknown bank method %s %d\n", - __FILE__, __LINE__); - return; - } - __raw_writel(l, reg); -} - -/** - * Set value of the specified gpio - */ -int gpio_set_value(unsigned gpio, int value) -{ - const struct gpio_bank *bank; - - if (check_gpio(gpio) < 0) - return -1; - bank = get_gpio_bank(gpio); - _set_gpio_dataout(bank, get_gpio_index(gpio), value); - - return 0; -} - -/** - * Get value of the specified gpio - */ -int gpio_get_value(unsigned gpio) -{ - const struct gpio_bank *bank; - void *reg; - int input; - - if (check_gpio(gpio) < 0) - return -1; - bank = get_gpio_bank(gpio); - reg = bank->base; - switch (bank->method) { - case METHOD_GPIO_24XX: - input = _get_gpio_direction(bank, get_gpio_index(gpio)); - switch (input) { - case OMAP_GPIO_DIR_IN: - reg += OMAP_GPIO_DATAIN; - break; - case OMAP_GPIO_DIR_OUT: - reg += OMAP_GPIO_DATAOUT; - break; - default: - return -1; - } - break; - default: - return -1; - } - return (__raw_readl(reg) - & (1 << get_gpio_index(gpio))) != 0; -} - -/** - * Set gpio direction as input - */ -int gpio_direction_input(unsigned gpio) -{ - const struct gpio_bank *bank; - - if (check_gpio(gpio) < 0) - return -1; - - bank = get_gpio_bank(gpio); - _set_gpio_direction(bank, get_gpio_index(gpio), 1); - - return 0; -} - -/** - * Set gpio direction as output - */ -int gpio_direction_output(unsigned gpio, int value) -{ - const struct gpio_bank *bank; - - if (check_gpio(gpio) < 0) - return -1; - - bank = get_gpio_bank(gpio); - _set_gpio_dataout(bank, get_gpio_index(gpio), value); - _set_gpio_direction(bank, get_gpio_index(gpio), 0); - - return 0; -} - -/** - * Request a gpio before using it. - * - * NOTE: Argument 'label' is unused. - */ -int gpio_request(unsigned gpio, const char *label) -{ - if (check_gpio(gpio) < 0) - return -1; - - return 0; -} - -/** - * Reset and free the gpio after using it. - */ -int gpio_free(unsigned gpio) -{ - return 0; -} diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index ccc6bb6b8..1ece07363 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -78,24 +78,6 @@ ENTRY(save_boot_params) bx lr ENDPROC(save_boot_params) -ENTRY(lowlevel_init) - /* - * Setup a temporary stack - */ - ldr sp, =LOW_LEVEL_SRAM_STACK - - /* - * Save the old lr(passed in ip) and the current lr to stack - */ - push {ip, lr} - - /* - * go setup pll, mux, memory - */ - bl s_init - pop {ip, pc} -ENDPROC(lowlevel_init) - ENTRY(set_pl310_ctrl_reg) PUSH {r4-r11, lr} @ save registers - ROM code may pollute @ our registers diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index 58d279e00..44d7bc360 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -170,7 +170,7 @@ int pwm_init(int pwm_id, int div, int invert) timer_rate_hz = get_pwm_clk() / ((prescaler + 1) * (div + 1)); - timer_rate_hz = timer_rate_hz / 100; + timer_rate_hz = timer_rate_hz / CONFIG_SYS_HZ; /* set count value */ offset = pwm_id * 3; diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index 359c21f5e..bb0e795e6 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -31,6 +31,8 @@ DECLARE_GLOBAL_DATA_PTR; +unsigned long get_current_tick(void); + /* macro to read the 16 bit timer */ static inline struct s5p_timer *s5p_get_base_timer(void) { @@ -44,6 +46,8 @@ int timer_init(void) pwm_config(4, 0, 0); pwm_enable(4); + reset_timer_masked(); + return 0; } @@ -72,16 +76,16 @@ void __udelay(unsigned long usec) * 3. finish normalize. */ tmo = usec / 1000; - tmo *= (CONFIG_SYS_HZ * count_value / 10); + tmo *= (CONFIG_SYS_HZ * count_value); tmo /= 1000; } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ * count_value / 10; + tmo = usec * CONFIG_SYS_HZ * count_value; tmo /= (1000 * 1000); } /* get current timestamp */ - tmp = get_timer(0); + tmp = get_current_tick(); /* if setting this fordward will roll time stamp */ /* reset "advancing" timestamp to 0, set lastinc value */ @@ -92,7 +96,7 @@ void __udelay(unsigned long usec) tmo += tmp; /* loop till event */ - while (get_timer_masked() < tmo) + while (get_current_tick() < tmo) ; /* nop */ } @@ -108,6 +112,14 @@ void reset_timer_masked(void) unsigned long get_timer_masked(void) { struct s5p_timer *const timer = s5p_get_base_timer(); + unsigned long count_value = readl(&timer->tcntb4); + + return get_current_tick() / count_value; +} + +unsigned long get_current_tick(void) +{ + struct s5p_timer *const timer = s5p_get_base_timer(); unsigned long now = readl(&timer->tcnto4); unsigned long count_value = readl(&timer->tcntb4); diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index aee27fdc4..32658eb7a 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -133,7 +133,6 @@ reset: orr r0, r0, #0xd3 msr cpsr,r0 -#if !defined(CONFIG_TEGRA2) /* * Setup vector: * (OMAP4 spl TEXT_BASE is not 32 byte aligned. @@ -149,7 +148,6 @@ reset: ldr r0, =_start mcr p15, 0, r0, c12, c0, 0 @Set VBAR #endif -#endif /* !Tegra2 */ /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT @@ -282,14 +280,14 @@ jump_2_ram: /* * Move vector table */ -#if !defined(CONFIG_TEGRA2) +#if !defined(CONFIG_TEGRA20) #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) /* Set vector address in CP15 VBAR register */ ldr r0, =_start add r0, r0, r9 mcr p15, 0, r0, c12, c0, 0 @Set VBAR #endif -#endif /* !Tegra2 */ +#endif /* !Tegra20 */ ldr r0, _board_init_r_ofs adr r1, _start @@ -307,6 +305,20 @@ ENDPROC(relocate_code) /************************************************************************* * + * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) + * __attribute__((weak)); + * + * Stack pointer is not yet initialized at this moment + * Don't save anything to stack even if compiled with -O0 + * + *************************************************************************/ +ENTRY(save_boot_params) + bx lr @ back to my caller +ENDPROC(save_boot_params) + .weak save_boot_params + +/************************************************************************* + * * cpu_init_cp15 * * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless diff --git a/arch/arm/cpu/armv7/imx-common/Makefile b/arch/arm/cpu/armv7/tegra20/Makefile index bf36be576..5f4035d79 100644 --- a/arch/arm/cpu/armv7/imx-common/Makefile +++ b/arch/arm/cpu/armv7/tegra20/Makefile @@ -1,8 +1,8 @@ # -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010,2011 Nvidia Corporation. # -# (C) Copyright 2011 Freescale Semiconductor, Inc. +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this # project. @@ -25,16 +25,16 @@ include $(TOPDIR)/config.mk -LIB = $(obj)libimx-common.o +LIB = $(obj)lib$(SOC).o -COBJS-y = iomux-v3.o timer.o cpu.o speed.o -COBJS-$(CONFIG_I2C_MXC) += i2c.o -COBJS := $(sort $(COBJS-y)) +COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o +COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) -all: $(obj).depend $(LIB) +all: $(obj).depend $(LIB) $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) diff --git a/arch/arm/cpu/armv7/tegra2/cmd_enterrcm.c b/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c index 2fcd107df..925f8414c 100644 --- a/arch/arm/cpu/armv7/tegra2/cmd_enterrcm.c +++ b/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c @@ -40,13 +40,13 @@ */ #include <common.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/pmc.h> static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; puts("Entering RCM...\n"); udelay(50000); diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra20/config.mk index 4dd8cb844..6432e754e 100644 --- a/arch/arm/cpu/armv7/tegra2/config.mk +++ b/arch/arm/cpu/armv7/tegra20/config.mk @@ -23,16 +23,4 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - -# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build these -# files with compatible flags -ifdef CONFIG_TEGRA2 -CFLAGS_arch/arm/lib/board.o += -march=armv4t -CFLAGS_arch/arm/lib/memset.o += -march=armv4t -CFLAGS_lib/string.o += -march=armv4t -CFLAGS_common/cmd_nvedit.o += -march=armv4t -endif - -USE_PRIVATE_LIBGCC = yes - CONFIG_ARCH_DEVICE_TREE := tegra20 diff --git a/arch/arm/cpu/armv7/tegra2/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c index 5f2b24375..cac0918ff 100644 --- a/arch/arm/cpu/armv7/tegra2/usb.c +++ b/arch/arm/cpu/armv7/tegra20/usb.c @@ -24,7 +24,7 @@ #include <common.h> #include <asm/io.h> #include <asm-generic/gpio.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> #include <asm/arch/gpio.h> @@ -137,24 +137,29 @@ static const u8 utmip_elastic_limit = 16; /* UTMIP High Speed Sync Start Delay */ static const u8 utmip_hs_sync_start_delay = 9; -/* Put the port into host mode (this only works for OTG ports) */ +/* Put the port into host mode */ static void set_host_mode(struct fdt_usb *config) { - if (config->dr_mode == DR_MODE_OTG) { - /* Check whether remote host from USB1 is driving VBus */ - if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS) - return; + /* + * If we are an OTG port, check if remote host is driving VBus and + * bail out in this case. + */ + if (config->dr_mode == DR_MODE_OTG && + (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) + return; - /* - * If not driving, we set the GPIO to enable VBUS. We assume - * that the pinmux is set up correctly for this. - */ - if (fdt_gpio_isvalid(&config->vbus_gpio)) { - fdtdec_setup_gpio(&config->vbus_gpio); - gpio_direction_output(config->vbus_gpio.gpio, 1); - debug("set_host_mode: GPIO %d high\n", - config->vbus_gpio.gpio); - } + /* + * If not driving, we set the GPIO to enable VBUS. We assume + * that the pinmux is set up correctly for this. + */ + if (fdt_gpio_isvalid(&config->vbus_gpio)) { + fdtdec_setup_gpio(&config->vbus_gpio); + gpio_direction_output(config->vbus_gpio.gpio, + (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? + 0 : 1); + debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio, + (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? + "low" : "high"); } } diff --git a/arch/arm/cpu/armv7/u8500/Makefile b/arch/arm/cpu/armv7/u8500/Makefile index 270aa40c8..ce8af9603 100644 --- a/arch/arm/cpu/armv7/u8500/Makefile +++ b/arch/arm/cpu/armv7/u8500/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS = timer.o clock.o +COBJS = timer.o clock.o prcmu.o cpu.o SOBJS = lowlevel.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/u8500/clock.c b/arch/arm/cpu/armv7/u8500/clock.c index 9e3b87394..fcfd61a1f 100644 --- a/arch/arm/cpu/armv7/u8500/clock.c +++ b/arch/arm/cpu/armv7/u8500/clock.c @@ -54,3 +54,37 @@ void u8500_clock_enable(int periph, int cluster, int kern) if (cluster != -1) writel(1 << cluster, &clkrst->pcken); } + +void db8500_clocks_init(void) +{ + /* + * Enable all clocks. This is u-boot, we can enable it all. There is no + * powersave in u-boot. + */ + + u8500_clock_enable(1, 9, -1); /* GPIO0 */ + u8500_clock_enable(2, 11, -1);/* GPIO1 */ + u8500_clock_enable(3, 8, -1); /* GPIO2 */ + u8500_clock_enable(5, 1, -1); /* GPIO3 */ + u8500_clock_enable(3, 6, 6); /* UART2 */ + u8500_clock_enable(3, 3, 3); /* I2C0 */ + u8500_clock_enable(1, 5, 5); /* SDI0 */ + u8500_clock_enable(2, 4, 2); /* SDI4 */ + u8500_clock_enable(6, 6, -1); /* MTU0 */ + u8500_clock_enable(3, 4, 4); /* SDI2 */ + + /* + * Enabling clocks for all devices which are AMBA devices in the + * kernel. Otherwise they will not get probe()'d because the + * peripheral ID register will not be powered. + */ + + /* XXX: some of these differ between ED/V1 */ + + u8500_clock_enable(1, 1, 1); /* UART1 */ + u8500_clock_enable(1, 0, 0); /* UART0 */ + u8500_clock_enable(3, 2, 2); /* SSP1 */ + u8500_clock_enable(3, 1, 1); /* SSP0 */ + u8500_clock_enable(2, 8, -1); /* SPI0 */ + u8500_clock_enable(2, 5, 3); /* MSP2 */ +} diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c new file mode 100644 index 000000000..6f95c3067 --- /dev/null +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -0,0 +1,192 @@ +/* + * Copyright (C) 2012 Linaro Limited + * Mathieu Poirier <mathieu.poirier@linaro.org> + * + * Based on original code from Joakim Axelsson at ST-Ericsson + * (C) Copyright 2010 ST-Ericsson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/prcmu.h> +#include <asm/arch/clock.h> +#include <asm/arch/hardware.h> + +#include <asm/arch/hardware.h> + +#define CPUID_DB8500V1 0x411fc091 +#define CPUID_DB8500V2 0x412fc091 +#define ASICID_DB8500V11 0x008500A1 + +#define CACHE_CONTR_BASE 0xA0412000 +/* Cache controller register offsets + * as found in ARM's technical reference manual + */ +#define CACHE_INVAL_BY_WAY (CACHE_CONTR_BASE + 0x77C) +#define CACHE_LOCKDOWN_BY_D (CACHE_CONTR_BASE + 0X900) +#define CACHE_LOCKDOWN_BY_I (CACHE_CONTR_BASE + 0X904) + +static unsigned int read_asicid(void); + +static inline unsigned int read_cpuid(void) +{ + unsigned int val; + + /* Main ID register (MIDR) */ + asm("mrc p15, 0, %0, c0, c0, 0" + : "=r" (val) + : + : "cc"); + + return val; +} + +static int cpu_is_u8500v11(void) +{ + return read_asicid() == ASICID_DB8500V11; +} + +static int cpu_is_u8500v2(void) +{ + return read_cpuid() == CPUID_DB8500V2; +} + +static unsigned int read_asicid(void) +{ + unsigned int *address; + + if (cpu_is_u8500v2()) + address = (void *) U8500_ASIC_ID_LOC_V2; + else + address = (void *) U8500_ASIC_ID_LOC_ED_V1; + + return readl(address); +} + +void cpu_cache_initialization(void) +{ + unsigned int value; + /* invalidate all cache entries */ + writel(0xFFFF, CACHE_INVAL_BY_WAY); + + /* ways are set to '0' when they are totally + * cleaned and invalidated + */ + do { + value = readl(CACHE_INVAL_BY_WAY); + } while (value & 0xFF); + + /* Invalidate register 9 D and I lockdown */ + writel(0xFF, CACHE_LOCKDOWN_BY_D); + writel(0xFF, CACHE_LOCKDOWN_BY_I); +} + +#ifdef CONFIG_ARCH_CPU_INIT +/* + * SOC specific cpu init + */ +int arch_cpu_init(void) +{ + db8500_prcmu_init(); + db8500_clocks_init(); + + return 0; +} +#endif /* CONFIG_ARCH_CPU_INIT */ + +#ifdef CONFIG_MMC + +int u8500_mmc_power_init(void) +{ + int ret; + int enable, voltage; + int ab8500_revision; + + if (!cpu_is_u8500v11() && !cpu_is_u8500v2()) + return 0; + + /* Get AB8500 revision */ + ret = ab8500_read(AB8500_MISC, AB8500_REV_REG); + if (ret < 0) + goto out; + + ab8500_revision = ret; + + /* + * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD + * card to work. This is done by enabling the regulators in the AB8500 + * via PRCMU I2C transactions. + * + * This code is derived from the handling of AB8500_LDO_VAUX3 in + * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux. + * + * Turn off and delay is required to have it work across soft reboots. + */ + + /* Turn off (read-modify-write) */ + ret = ab8500_read(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_REGU_REG); + if (ret < 0) + goto out; + + enable = ret; + + /* Turn off */ + ret = ab8500_write(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_REGU_REG, + enable & ~LDO_VAUX3_ENABLE_MASK); + if (ret < 0) + goto out; + + udelay(10 * 1000); + + /* Set the voltage to 2.91 V or 2.9 V without overriding VRF1 value */ + ret = ab8500_read(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_SEL_REG); + if (ret < 0) + goto out; + + voltage = ret; + + if (ab8500_revision < 0x20) { + voltage &= ~LDO_VAUX3_SEL_MASK; + voltage |= LDO_VAUX3_SEL_2V9; + } else { + voltage &= ~LDO_VAUX3_V2_SEL_MASK; + voltage |= LDO_VAUX3_V2_SEL_2V91; + } + + ret = ab8500_write(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_SEL_REG, voltage); + if (ret < 0) + goto out; + + /* Turn on the supply */ + enable &= ~LDO_VAUX3_ENABLE_MASK; + enable |= LDO_VAUX3_ENABLE_VAL; + + ret = ab8500_write(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_REGU_REG, enable); + +out: + return ret; +} +#endif /* CONFIG_MMC */ diff --git a/arch/arm/cpu/armv7/u8500/prcmu.c b/arch/arm/cpu/armv7/u8500/prcmu.c new file mode 100644 index 000000000..934428fb8 --- /dev/null +++ b/arch/arm/cpu/armv7/u8500/prcmu.c @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2009 ST-Ericsson SA + * + * Adapted from the Linux version: + * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +/* + * NOTE: This currently does not support the I2C workaround access method. + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/types.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/prcmu.h> + +/* CPU mailbox registers */ +#define PRCMU_I2C_WRITE(slave) \ + (((slave) << 1) | I2CWRITE | (1 << 6)) +#define PRCMU_I2C_READ(slave) \ + (((slave) << 1) | I2CREAD | (1 << 6)) + +#define I2C_MBOX_BIT (1 << 5) + +static int prcmu_is_ready(void) +{ + int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE; + if (!ready) + printf("PRCMU firmware not ready\n"); + return ready; +} + +static int wait_for_i2c_mbx_rdy(void) +{ + int timeout = 10000; + + if (readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) { + printf("prcmu: warning i2c mailbox was not acked\n"); + /* clear mailbox 5 ack irq */ + writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); + } + + /* check any already on-going transaction */ + while ((readl(PRCM_MBOX_CPU_VAL) & I2C_MBOX_BIT) && timeout) + timeout--; + + if (timeout == 0) + return -1; + + return 0; +} + +static int wait_for_i2c_req_done(void) +{ + int timeout = 10000; + + /* Set an interrupt to XP70 */ + writel(I2C_MBOX_BIT, PRCM_MBOX_CPU_SET); + + /* wait for mailbox 5 (i2c) ack */ + while (!(readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) && timeout) + timeout--; + + if (timeout == 0) + return -1; + + return 0; +} + +/** + * prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C + * @reg: - db8500 register bank to be accessed + * @slave: - db8500 register to be accessed + * Returns: ACK_MB5 value containing the status + */ +int prcmu_i2c_read(u8 reg, u16 slave) +{ + uint8_t i2c_status; + uint8_t i2c_val; + int ret; + + if (!prcmu_is_ready()) + return -1; + + debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n", + reg, slave); + + ret = wait_for_i2c_mbx_rdy(); + if (ret) { + printf("prcmu_i2c_read: mailbox became not ready\n"); + return ret; + } + + /* prepare the data for mailbox 5 */ + writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG); + writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); + writeb(slave, PRCM_REQ_MB5_I2CSLAVE); + writeb(0, PRCM_REQ_MB5_I2CVAL); + + ret = wait_for_i2c_req_done(); + if (ret) { + printf("prcmu_i2c_read: mailbox request timed out\n"); + return ret; + } + + /* retrieve values */ + debug("ack-mb5:transfer status = %x\n", + readb(PRCM_ACK_MB5_STATUS)); + debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); + debug("ack-mb5:slave_add = %x\n", + readb(PRCM_ACK_MB5_SLAVE)); + debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); + + i2c_status = readb(PRCM_ACK_MB5_STATUS); + i2c_val = readb(PRCM_ACK_MB5_VAL); + /* clear mailbox 5 ack irq */ + writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); + + if (i2c_status == I2C_RD_OK) + return i2c_val; + + printf("prcmu_i2c_read:read return status= %d\n", i2c_status); + return -1; +} + +/** + * prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C + * @reg: - db8500 register bank to be accessed + * @slave: - db800 register to be written to + * @reg_data: - the data to write + * Returns: ACK_MB5 value containing the status + */ +int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) +{ + uint8_t i2c_status; + int ret; + + if (!prcmu_is_ready()) + return -1; + + debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n", + reg, slave); + + ret = wait_for_i2c_mbx_rdy(); + if (ret) { + printf("prcmu_i2c_write: mailbox became not ready\n"); + return ret; + } + + /* prepare the data for mailbox 5 */ + writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG); + writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); + writeb(slave, PRCM_REQ_MB5_I2CSLAVE); + writeb(reg_data, PRCM_REQ_MB5_I2CVAL); + + ret = wait_for_i2c_req_done(); + if (ret) { + printf("prcmu_i2c_write: mailbox request timed out\n"); + return ret; + } + + /* retrieve values */ + debug("ack-mb5:transfer status = %x\n", + readb(PRCM_ACK_MB5_STATUS)); + debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); + debug("ack-mb5:slave_add = %x\n", + readb(PRCM_ACK_MB5_SLAVE)); + debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); + + i2c_status = readb(PRCM_ACK_MB5_STATUS); + debug("\ni2c_status = %x\n", i2c_status); + /* clear mailbox 5 ack irq */ + writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); + + if (i2c_status == I2C_WR_OK) + return 0; + + printf("%s: i2c_status : 0x%x\n", __func__, i2c_status); + return -1; +} + +void u8500_prcmu_enable(u32 *reg) +{ + writel(readl(reg) | (1 << 8), reg); +} + +void db8500_prcmu_init(void) +{ + /* Enable timers */ + writel(1 << 17, PRCM_TCR); + + u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG); + /* PER4CLK does not exist */ + u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG); + /* Only exists in ED but is always ok to write to */ + u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG); + + u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG); + + u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG); + + /* Clean up the mailbox interrupts after pre-u-boot code. */ + writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); +} diff --git a/arch/arm/cpu/ixp/cpu.c b/arch/arm/cpu/ixp/cpu.c index 942845d54..f1864d631 100644 --- a/arch/arm/cpu/ixp/cpu.c +++ b/arch/arm/cpu/ixp/cpu.c @@ -107,28 +107,6 @@ void pci_init(void) } */ -#ifdef CONFIG_BOOTCOUNT_LIMIT - -void bootcount_store (ulong a) -{ - volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR); - - save_addr[0] = a; - save_addr[1] = BOOTCOUNT_MAGIC; -} - -ulong bootcount_load (void) -{ - volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR); - - if (save_addr[1] != BOOTCOUNT_MAGIC) - return 0; - else - return save_addr[0]; -} - -#endif /* CONFIG_BOOTCOUNT_LIMIT */ - int cpu_eth_init(bd_t *bis) { #ifdef CONFIG_IXP4XX_NPE diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/tegra20-common/Makefile index 80da4536d..9e91e5cb8 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/tegra20-common/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2010,2011 Nvidia Corporation. # -# (C) Copyright 2000-2003 +# (C) Copyright 2000-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -14,7 +14,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -23,29 +23,24 @@ # MA 02111-1307 USA # +include $(TOPDIR)/config.mk + # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. -CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t -CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t -CFLAGS_arch/arm/cpu/armv7/tegra2/warmboot_avp.o += -march=armv4t - -include $(TOPDIR)/config.mk +CFLAGS_arch/arm/cpu/tegra20-common/warmboot_avp.o += -march=armv4t -LIB = $(obj)lib$(SOC).o +LIB = $(obj)lib$(SOC)-common.o -SOBJS := lowlevel_init.o -COBJS-y := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +SOBJS += lowlevel_init.o +COBJS-y += ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o COBJS-$(CONFIG_TEGRA_PMU) += pmu.o -COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o -COBJS-$(CONFIG_TEGRA2_LP0) += crypto.o warmboot.o warmboot_avp.o -COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) -all: $(obj).depend $(LIB) +all: $(obj).depend $(LIB) $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) diff --git a/arch/arm/cpu/tegra20-common/ap20.c b/arch/arm/cpu/tegra20-common/ap20.c new file mode 100644 index 000000000..c0ca6eb37 --- /dev/null +++ b/arch/arm/cpu/tegra20-common/ap20.c @@ -0,0 +1,131 @@ +/* +* (C) Copyright 2010-2011 +* NVIDIA Corporation <www.nvidia.com> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ +#include <asm/io.h> +#include <asm/arch/ap20.h> +#include <asm/arch/fuse.h> +#include <asm/arch/gp_padctrl.h> +#include <asm/arch/pmc.h> +#include <asm/arch/scu.h> +#include <asm/arch/warmboot.h> +#include <common.h> + +int tegra_get_chip_type(void) +{ + struct apb_misc_gp_ctlr *gp; + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; + uint tegra_sku_id, rev; + + /* + * This is undocumented, Chip ID is bits 15:8 of the register + * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for + * Tegra30 + */ + gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; + rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; + + tegra_sku_id = readl(&fuse->sku_info) & 0xff; + + switch (rev) { + case CHIPID_TEGRA20: + switch (tegra_sku_id) { + case SKU_ID_T20: + return TEGRA_SOC_T20; + case SKU_ID_T25SE: + case SKU_ID_AP25: + case SKU_ID_T25: + case SKU_ID_AP25E: + case SKU_ID_T25E: + return TEGRA_SOC_T25; + } + break; + } + /* unknown sku id */ + return TEGRA_SOC_UNKNOWN; +} + +static void enable_scu(void) +{ + struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; + u32 reg; + + /* If SCU already setup/enabled, return */ + if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE) + return; + + /* Invalidate all ways for all processors */ + writel(0xFFFF, &scu->scu_inv_all); + + /* Enable SCU - bit 0 */ + reg = readl(&scu->scu_ctrl); + reg |= SCU_CTRL_ENABLE; + writel(reg, &scu->scu_ctrl); +} + +static u32 get_odmdata(void) +{ + /* + * ODMDATA is stored in the BCT in IRAM by the BootROM. + * The BCT start and size are stored in the BIT in IRAM. + * Read the data @ bct_start + (bct_size - 12). This works + * on T20 and T30 BCTs, which are locked down. If this changes + * in new chips (T114, etc.), we can revisit this algorithm. + */ + + u32 bct_start, odmdata; + + bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR); + odmdata = readl(bct_start + BCT_ODMDATA_OFFSET); + + return odmdata; +} + +static void init_pmc_scratch(void) +{ + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + u32 odmdata; + int i; + + /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ + for (i = 0; i < 23; i++) + writel(0, &pmc->pmc_scratch1+i); + + /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ + odmdata = get_odmdata(); + writel(odmdata, &pmc->pmc_scratch20); +} + +void s_init(void) +{ + /* Init PMC scratch memory */ + init_pmc_scratch(); + + enable_scu(); + + /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #0x41\n" + "mcr p15, 0, r0, c1, c0, 1\n"); + + /* FIXME: should have ap20's L2 disabled too? */ +} diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/tegra20-common/board.c index 923678d06..8a8d3384a 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/tegra20-common/board.c @@ -23,12 +23,12 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/ap20.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pmc.h> #include <asm/arch/sys_proto.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> +#include <asm/arch/warmboot.h> DECLARE_GLOBAL_DATA_PTR; @@ -47,7 +47,7 @@ enum { unsigned int query_sdram_size(void) { - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; reg = readl(&pmc->pmc_scratch20); @@ -80,33 +80,12 @@ int checkboard(void) } #endif /* CONFIG_DISPLAY_BOARDINFO */ -#ifdef CONFIG_ARCH_CPU_INIT -/* - * Note this function is executed by the ARM7TDMI AVP. It does not return - * in this case. It is also called once the A9 starts up, but does nothing in - * that case. - */ -int arch_cpu_init(void) -{ - /* Fire up the Cortex A9 */ - tegra2_start(); - - /* We didn't do this init in start.S, so do it now */ - cpu_init_cp15(); - - /* Initialize essential common plls */ - clock_early_init(); - - return 0; -} -#endif - static int uart_configs[] = { -#if defined(CONFIG_TEGRA2_UARTA_UAA_UAB) +#if defined(CONFIG_TEGRA_UARTA_UAA_UAB) FUNCMUX_UART1_UAA_UAB, -#elif defined(CONFIG_TEGRA2_UARTA_GPU) +#elif defined(CONFIG_TEGRA_UARTA_GPU) FUNCMUX_UART1_GPU, -#elif defined(CONFIG_TEGRA2_UARTA_SDIO1) +#elif defined(CONFIG_TEGRA_UARTA_SDIO1) FUNCMUX_UART1_SDIO1, #else FUNCMUX_UART1_IRRX_IRTX, @@ -146,13 +125,13 @@ void board_init_uart_f(void) { int uart_ids = 0; /* bit mask of which UART ids to enable */ -#ifdef CONFIG_TEGRA2_ENABLE_UARTA +#ifdef CONFIG_TEGRA_ENABLE_UARTA uart_ids |= UARTA; #endif -#ifdef CONFIG_TEGRA2_ENABLE_UARTB +#ifdef CONFIG_TEGRA_ENABLE_UARTB uart_ids |= UARTB; #endif -#ifdef CONFIG_TEGRA2_ENABLE_UARTD +#ifdef CONFIG_TEGRA_ENABLE_UARTD uart_ids |= UARTD; #endif setup_uarts(uart_ids); diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/tegra20-common/clock.c index 602589cde..24038745b 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/tegra20-common/clock.c @@ -19,13 +19,13 @@ * MA 02111-1307 USA */ -/* Tegra2 Clock control functions */ +/* Tegra20 Clock control functions */ #include <asm/io.h> #include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> #include <asm/arch/timer.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <common.h> #include <div64.h> #include <fdtdec.h> @@ -49,7 +49,7 @@ static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = { }; /* - * Clock types that we can use as a source. The Tegra2 has muxes for the + * Clock types that we can use as a source. The Tegra20 has muxes for the * peripheral clocks, and in most cases there are four options for the clock * source. This gives us a clock 'type' and exploits what commonality exists * in the device. @@ -848,7 +848,7 @@ void reset_cmplx_set_enable(int cpu, int which, int reset) (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; u32 mask; - /* Form the mask, which depends on the cpu chosen. Tegra2 has 2 */ + /* Form the mask, which depends on the cpu chosen. Tegra20 has 2 */ assert(cpu >= 0 && cpu < 2); mask = which << cpu; @@ -976,7 +976,7 @@ void clock_ll_start_uart(enum periph_id periph_id) * the same but we are very cautious so we check that a valid clock ID is * provided. * - * @param clk_id Clock ID according to tegra2 device tree binding + * @param clk_id Clock ID according to tegra20 device tree binding * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid */ static enum periph_id clk_id_to_periph_id(int clk_id) diff --git a/arch/arm/cpu/armv7/tegra2/crypto.c b/arch/arm/cpu/tegra20-common/crypto.c index 5f0b240e2..5f0b240e2 100644 --- a/arch/arm/cpu/armv7/tegra2/crypto.c +++ b/arch/arm/cpu/tegra20-common/crypto.c diff --git a/arch/arm/cpu/armv7/tegra2/crypto.h b/arch/arm/cpu/tegra20-common/crypto.h index aff67e77b..aff67e77b 100644 --- a/arch/arm/cpu/armv7/tegra2/crypto.h +++ b/arch/arm/cpu/tegra20-common/crypto.h diff --git a/arch/arm/cpu/armv7/tegra2/emc.c b/arch/arm/cpu/tegra20-common/emc.c index c0e5c565f..ffc05e453 100644 --- a/arch/arm/cpu/armv7/tegra2/emc.c +++ b/arch/arm/cpu/tegra20-common/emc.c @@ -27,7 +27,7 @@ #include <asm/arch/apb_misc.h> #include <asm/arch/clock.h> #include <asm/arch/emc.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> /* * The EMC registers have shadow registers. When the EMC clock is updated diff --git a/arch/arm/cpu/armv7/tegra2/funcmux.c b/arch/arm/cpu/tegra20-common/funcmux.c index 4a31a4cf0..b2129adf2 100644 --- a/arch/arm/cpu/armv7/tegra2/funcmux.c +++ b/arch/arm/cpu/tegra20-common/funcmux.c @@ -19,7 +19,7 @@ * MA 02111-1307 USA */ -/* Tegra2 high-level function multiplexing */ +/* Tegra20 high-level function multiplexing */ #include <common.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> @@ -234,6 +234,13 @@ int funcmux_select(enum periph_id id, int config) } break; + case PERIPH_ID_NDFLASH: + if (config == FUNCMUX_NDFLASH_ATC) { + pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND); + pinmux_tristate_disable(PINGRP_ATC); + } + break; + default: debug("%s: invalid periph_id %d", __func__, id); return -1; diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/tegra20-common/lowlevel_init.S index d117f23a6..d117f23a6 100644 --- a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S +++ b/arch/arm/cpu/tegra20-common/lowlevel_init.S diff --git a/arch/arm/cpu/armv7/tegra2/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c index b053f9060..70e84dfa1 100644 --- a/arch/arm/cpu/armv7/tegra2/pinmux.c +++ b/arch/arm/cpu/tegra20-common/pinmux.c @@ -19,10 +19,10 @@ * MA 02111-1307 USA */ -/* Tegra2 pin multiplexing functions */ +/* Tegra20 pin multiplexing functions */ #include <asm/io.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/pinmux.h> #include <common.h> diff --git a/arch/arm/cpu/armv7/tegra2/pmu.c b/arch/arm/cpu/tegra20-common/pmu.c index 46738023f..53505e9c5 100644 --- a/arch/arm/cpu/armv7/tegra2/pmu.c +++ b/arch/arm/cpu/tegra20-common/pmu.c @@ -25,7 +25,7 @@ #include <tps6586x.h> #include <asm/io.h> #include <asm/arch/ap20.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/tegra_i2c.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/cpu/armv7/tegra2/sys_info.c b/arch/arm/cpu/tegra20-common/sys_info.c index 6d11dc16b..1a0bb561a 100644 --- a/arch/arm/cpu/armv7/tegra2/sys_info.c +++ b/arch/arm/cpu/tegra20-common/sys_info.c @@ -27,7 +27,7 @@ /* Print CPU information */ int print_cpuinfo(void) { - puts("TEGRA2\n"); + puts("TEGRA20\n"); /* TBD: Add printf of major/minor rev info, stepping, etc. */ return 0; diff --git a/arch/arm/cpu/armv7/tegra2/timer.c b/arch/arm/cpu/tegra20-common/timer.c index b12b12cc3..562e41401 100644 --- a/arch/arm/cpu/armv7/tegra2/timer.c +++ b/arch/arm/cpu/tegra20-common/timer.c @@ -37,7 +37,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/timer.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/cpu/armv7/tegra2/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c index 25d896888..6ce995ef0 100644 --- a/arch/arm/cpu/armv7/tegra2/warmboot.c +++ b/arch/arm/cpu/tegra20-common/warmboot.c @@ -29,7 +29,7 @@ #include <asm/arch/clock.h> #include <asm/arch/pmc.h> #include <asm/arch/pinmux.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/fuse.h> #include <asm/arch/emc.h> #include <asm/arch/gp_padctrl.h> @@ -39,7 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_TEGRA_CLOCK_SCALING -#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA2_LP0" +#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0" #endif /* @@ -139,9 +139,9 @@ int warmboot_save_sdram_params(void) u32 ram_code; struct sdram_params sdram; struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE; + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob); union scratch2_reg scratch2; union scratch4_reg scratch4; @@ -205,7 +205,7 @@ static u32 get_major_version(void) { u32 major_id; struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE; + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >> HIDREV_MAJORPREV_SHIFT; @@ -229,7 +229,7 @@ static int is_failure_analysis_mode(struct fuse_regs *fuse) static int ap20_is_odm_production_mode(void) { - struct fuse_regs *fuse = (struct fuse_regs *)TEGRA2_FUSE_BASE; + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; if (!is_failure_analysis_mode(fuse) && is_odm_production_mode_fuse_set(fuse)) @@ -240,7 +240,7 @@ static int ap20_is_odm_production_mode(void) static int ap20_is_production_mode(void) { - struct fuse_regs *fuse = (struct fuse_regs *)TEGRA2_FUSE_BASE; + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; if (get_major_version() == 0) return 1; @@ -257,11 +257,11 @@ static enum fuse_operating_mode fuse_get_operation_mode(void) { u32 chip_id; struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE; + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; - if (chip_id == CHIPID_TEGRA2) { + if (chip_id == CHIPID_TEGRA20) { if (ap20_is_odm_production_mode()) { printf("!! odm_production_mode is not supported !!\n"); return MODE_UNDEFINED; diff --git a/arch/arm/cpu/armv7/tegra2/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c index 70bcd8e5f..80a5a15de 100644 --- a/arch/arm/cpu/armv7/tegra2/warmboot_avp.c +++ b/arch/arm/cpu/tegra20-common/warmboot_avp.c @@ -29,7 +29,7 @@ #include <asm/arch/flow.h> #include <asm/arch/pinmux.h> #include <asm/arch/pmc.h> -#include <asm/arch/tegra2.h> +#include <asm/arch/tegra20.h> #include <asm/arch/warmboot.h> #include "warmboot_avp.h" @@ -38,7 +38,7 @@ void wb_start(void) { struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; diff --git a/arch/arm/cpu/armv7/tegra2/warmboot_avp.h b/arch/arm/cpu/tegra20-common/warmboot_avp.h index 4b71c0784..4b71c0784 100644 --- a/arch/arm/cpu/armv7/tegra2/warmboot_avp.h +++ b/arch/arm/cpu/tegra20-common/warmboot_avp.h |