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Diffstat (limited to 'arch/arm/cpu/armv7/mx6')
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c13
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c8
2 files changed, 20 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index fa3a12480..ef98563ff 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -36,6 +36,19 @@ enum pll_clocks {
struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
+void enable_usboh3_clk(unsigned char enable)
+{
+ u32 reg;
+
+ reg = __raw_readl(&imx_ccm->CCGR6);
+ if (enable)
+ reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
+ else
+ reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
+ __raw_writel(reg, &imx_ccm->CCGR6);
+
+}
+
static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{
u32 div;
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 2ac74b594..a81e2bc01 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -32,7 +32,13 @@
u32 get_cpu_rev(void)
{
- int system_rev = 0x61000 | CHIP_REV_1_0;
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ int reg = readl(&anatop->digprog);
+
+ /* Read mx6 variant: quad, dual or solo */
+ int system_rev = (reg >> 4) & 0xFF000;
+ /* Read mx6 silicon revision */
+ system_rev |= (reg & 0xFF) + 0x10;
return system_rev;
}