diff options
| -rw-r--r-- | CHANGELOG | 2 | ||||
| -rw-r--r-- | board/inka4x0/inka4x0.c | 52 | ||||
| -rw-r--r-- | common/cmd_ide.c | 2 | ||||
| -rw-r--r-- | include/configs/inka4x0.h | 5 | ||||
| -rw-r--r-- | include/mpc5xxx.h | 15 |
5 files changed, 59 insertions, 17 deletions
@@ -2,6 +2,8 @@ Changes for U-Boot 1.1.3: ====================================================================== +* Add port initialization for digital I/O on INKA4x0 + * Patch by Stefan Roese, 01 March 2005: Update for esd boards dp405 and hub405 diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c index 4900201dd..f5e32cc58 100644 --- a/board/inka4x0/inka4x0.c +++ b/board/inka4x0/inka4x0.c @@ -43,13 +43,11 @@ static void sdram_start (int hi_addr) long hi_addr_bit = hi_addr ? 0x01000000 : 0; /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | - hi_addr_bit; + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; __asm__ volatile ("sync"); /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; __asm__ volatile ("sync"); #if SDRAM_DDR @@ -63,13 +61,11 @@ static void sdram_start (int hi_addr) #endif /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; __asm__ volatile ("sync"); /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; __asm__ volatile ("sync"); /* set mode register */ @@ -177,27 +173,51 @@ void flash_preinit(void) *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } -#define GPIO_PSC3_9 0x04000000UL +#define GPIO_PSC3_9 0x04000000UL int misc_init_f (void) { + /* Initialize GPIO output pins. + */ + /* Configure GPT as GPIO output */ + *(vu_long *)MPC5XXX_GPT0_ENABLE = + *(vu_long *)MPC5XXX_GPT1_ENABLE = + *(vu_long *)MPC5XXX_GPT2_ENABLE = + *(vu_long *)MPC5XXX_GPT3_ENABLE = + *(vu_long *)MPC5XXX_GPT4_ENABLE = + *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x24; + + + /* Configure PSC3_6,7 as GPIO output */ + *(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000; + *(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000; + + /* Configure PSC3_8 as GPIO output, no interrupt */ + *(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000; + *(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000; + *(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000; + + /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */ + *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000; + *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000; + /* * Reset Coral-P graphics controller */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9; - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC3_9; - return 0; + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9; + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC3_9; + return 0; } -#ifdef CONFIG_PCI +#ifdef CONFIG_PCI static struct pci_controller hose; extern void pci_mpc5xxx_init(struct pci_controller *); void pci_init_board(void) { - pci_mpc5xxx_init(&hose); + pci_mpc5xxx_init(&hose); } #endif @@ -209,7 +229,7 @@ void init_ide_reset (void) { debug ("init_ide_reset\n"); - /* Configure PSC1_4 as GPIO output for ATA reset */ + /* Configure PSC1_4 as GPIO output for ATA reset */ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; /* Deassert reset */ diff --git a/common/cmd_ide.c b/common/cmd_ide.c index e185c95b2..1adfe2bfa 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -871,7 +871,7 @@ input_swap_data(int dev, ulong *sect_buf, int words) dbuf+=1; } } -#else +#else volatile ushort *pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG); ushort *dbuf = (ushort *)sect_buf; diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 038ab75e7..c817d2c3a 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -274,6 +274,11 @@ #define CFG_CS2_SIZE 0x0001000 #define CFG_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */ +/* GPIO in @0x30400000 */ +#define CFG_CS3_START 0x30400000 +#define CFG_CS3_SIZE 0x00100000 +#define CFG_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */ + #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333333 diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index e5c8c02ad..565e1cf02 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -233,6 +233,21 @@ /* General Purpose Timers registers */ #define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0) #define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4) +#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10) +#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14) +#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20) +#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24) +#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30) +#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34) +#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40) +#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44) +#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50) +#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54) +#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60) +#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64) +#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70) +#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74) + /* ATA registers */ #define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000) |