diff options
| -rw-r--r-- | drivers/fpga/spartan3.c | 52 | ||||
| -rw-r--r-- | include/spartan3.h | 1 | ||||
| -rw-r--r-- | include/xilinx.h | 1 | 
3 files changed, 30 insertions, 24 deletions
| diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 0fe30410a..7a89b5692 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -385,34 +385,38 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)  		} while ((*fn->init) (cookie));  		/* Load the data */ -		while (bytecount < bsize) { +		if(*fn->bwr) +			(*fn->bwr) (data, bsize, TRUE, cookie); +		else { +			while (bytecount < bsize) { -			/* Xilinx detects an error if INIT goes low (active) -			   while DONE is low (inactive) */ -			if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) { -				puts ("** CRC error during FPGA load.\n"); -				return (FPGA_FAIL); -			} -			val = data [bytecount ++]; -			i = 8; -			do { -				/* Deassert the clock */ -				(*fn->clk) (FALSE, TRUE, cookie); -				CONFIG_FPGA_DELAY (); -				/* Write data */ -				(*fn->wr) ((val & 0x80), TRUE, cookie); -				CONFIG_FPGA_DELAY (); -				/* Assert the clock */ -				(*fn->clk) (TRUE, TRUE, cookie); -				CONFIG_FPGA_DELAY (); -				val <<= 1; -				i --; -			} while (i > 0); +				/* Xilinx detects an error if INIT goes low (active) +				   while DONE is low (inactive) */ +				if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) { +					puts ("** CRC error during FPGA load.\n"); +					return (FPGA_FAIL); +				} +				val = data [bytecount ++]; +				i = 8; +				do { +					/* Deassert the clock */ +					(*fn->clk) (FALSE, TRUE, cookie); +					CONFIG_FPGA_DELAY (); +					/* Write data */ +					(*fn->wr) ((val & 0x80), TRUE, cookie); +					CONFIG_FPGA_DELAY (); +					/* Assert the clock */ +					(*fn->clk) (TRUE, TRUE, cookie); +					CONFIG_FPGA_DELAY (); +					val <<= 1; +					i --; +				} while (i > 0);  #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK -			if (bytecount % (bsize / 40) == 0) -				putc ('.');		/* let them know we are alive */ +				if (bytecount % (bsize / 40) == 0) +					putc ('.');		/* let them know we are alive */  #endif +			}  		}  		CONFIG_FPGA_DELAY (); diff --git a/include/spartan3.h b/include/spartan3.h index 30b1c2d62..d5a589d09 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -57,6 +57,7 @@ typedef struct {  	Xilinx_done_fn	done;  	Xilinx_wr_fn	wr;  	Xilinx_post_fn	post; +	Xilinx_bwr_fn	bwr; /* block write function */  } Xilinx_Spartan3_Slave_Serial_fns;  /* Device Image Sizes diff --git a/include/xilinx.h b/include/xilinx.h index d0799bc57..2cb2e5b6a 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -100,5 +100,6 @@ typedef int (*Xilinx_busy_fn)( int cookie );  typedef int (*Xilinx_abort_fn)( int cookie );  typedef int (*Xilinx_pre_fn)( int cookie );  typedef int (*Xilinx_post_fn)( int cookie ); +typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie );  #endif  /* _XILINX_H_ */ |