diff options
| -rw-r--r-- | CHANGELOG | 7 | ||||
| -rw-r--r-- | README | 4 | ||||
| -rw-r--r-- | board/total5200/total5200.c | 174 | ||||
| -rw-r--r-- | board/tqm5200/tqm5200.c | 8 | ||||
| -rw-r--r-- | common/cmd_mem.c | 4 | ||||
| -rw-r--r-- | common/cmd_reginfo.c | 22 | ||||
| -rw-r--r-- | common/docecc.c | 4 | ||||
| -rw-r--r-- | drivers/cfb_console.c | 7 | ||||
| -rw-r--r-- | include/configs/TQM5200.h | 46 | ||||
| -rw-r--r-- | include/configs/Total5200.h | 33 |
10 files changed, 257 insertions, 52 deletions
@@ -2,6 +2,13 @@ Changes since U-Boot 1.1.1: ====================================================================== +* Patch by Mark Jonas, 05 Jul 2004: + add support for the Total5100's and Total5200's LCD screen + +* Patches by Dan Eisenhut, 01 Jul 2004: + - README fixes. + - Move doc2000.h include to prevent compiler warning on some boards + * Patch by Mark Jonas, 01 Jul 2004: Added support for Total5100 and Total5200 (Rev.1 and Rev.2) MGT5100 and MPC5200 based Freescale platforms. @@ -596,13 +596,13 @@ The following options need to be configured: ----------------------------------------------- CFG_CMD_ALL all - CFG_CMD_DFL Default configuration; at the moment + CONFIG_CMD_DFL Default configuration; at the moment this is includes all commands, except the ones marked with "*" in the list above. If you don't define CONFIG_COMMANDS it defaults to - CFG_CMD_DFL in include/cmd_confdefs.h. A board can + CONFIG_CMD_DFL in include/cmd_confdefs.h. A board can override the default settings in the respective include file. diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c index 24aaafc74..4ec7b96c4 100644 --- a/board/total5200/total5200.c +++ b/board/total5200/total5200.c @@ -134,3 +134,177 @@ void ide_set_reset (int idereset) } } #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + +#ifdef CONFIG_VIDEO_SED13806 +#include <sed13806.h> + +#define DISPLAY_WIDTH 640 +#define DISPLAY_HEIGHT 480 + +#ifdef CONFIG_VIDEO_SED13806_8BPP +#error CONFIG_VIDEO_SED13806_8BPP not supported. +#endif /* CONFIG_VIDEO_SED13806_8BPP */ + +#ifdef CONFIG_VIDEO_SED13806_16BPP +static const S1D_REGS init_regs [] = +{ + {0x0001,0x00}, /* Miscellaneous Register */ + {0x01FC,0x00}, /* Display Mode Register */ + {0x0004,0x00}, /* General IO Pins Configuration Register 0 */ + {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ + {0x0008,0x00}, /* General IO Pins Control Register 0 */ + {0x0009,0x00}, /* General IO Pins Control Register 1 */ + {0x0010,0x02}, /* Memory Clock Configuration Register */ + {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ + {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ + {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ + {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ + {0x0021,0x03}, /* DRAM Refresh Rate Register */ + {0x002A,0x00}, /* DRAM Timings Control Register 0 */ + {0x002B,0x01}, /* DRAM Timings Control Register 1 */ + {0x0020,0x80}, /* Memory Configuration Register */ + {0x0030,0x25}, /* Panel Type Register */ + {0x0031,0x00}, /* MOD Rate Register */ + {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ + {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ + {0x0035,0x01}, /* TFT FPLINE Start Position Register */ + {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ + {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ + {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ + {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ + {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ + {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ + {0x0040,0x05}, /* LCD Display Mode Register */ + {0x0041,0x00}, /* LCD Miscellaneous Register */ + {0x0042,0x00}, /* LCD Display Start Address Register 0 */ + {0x0043,0x00}, /* LCD Display Start Address Register 1 */ + {0x0044,0x00}, /* LCD Display Start Address Register 2 */ + {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ + {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ + {0x0048,0x00}, /* LCD Pixel Panning Register */ + {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ + {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ + {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ + {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ + {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ + {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ + {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ + {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ + {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ + {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ + {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ + {0x005B,0x10}, /* TV Output Control Register */ + {0x0060,0x05}, /* CRT/TV Display Mode Register */ + {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ + {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ + {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ + {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ + {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ + {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ + {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ + {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ + {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ + {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ + {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ + {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ + {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ + {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ + {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ + {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ + {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ + {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ + {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ + {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ + {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ + {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ + {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ + {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ + {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ + {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ + {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ + {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ + {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ + {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ + {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ + {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ + {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ + {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ + {0x0100,0x00}, /* BitBlt Control Register 0 */ + {0x0101,0x00}, /* BitBlt Control Register 1 */ + {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ + {0x0103,0x00}, /* BitBlt Operation Register */ + {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ + {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ + {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ + {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ + {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ + {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ + {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ + {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ + {0x0110,0x00}, /* BitBlt Width Register 0 */ + {0x0111,0x00}, /* BitBlt Width Register 1 */ + {0x0112,0x00}, /* BitBlt Height Register 0 */ + {0x0113,0x00}, /* BitBlt Height Register 1 */ + {0x0114,0x00}, /* BitBlt Background Color Register 0 */ + {0x0115,0x00}, /* BitBlt Background Color Register 1 */ + {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ + {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ + {0x01E0,0x00}, /* Look-Up Table Mode Register */ + {0x01E2,0x00}, /* Look-Up Table Address Register */ + {0x01E4,0x00}, /* Look-Up Table Data Register */ + {0x01F0,0x00}, /* Power Save Configuration Register */ + {0x01F1,0x00}, /* Power Save Status Register */ + {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ + {0x01FC,0x01}, /* Display Mode Register */ + {0, 0} +}; +#endif /* CONFIG_VIDEO_SED13806_16BPP */ + +#ifdef CONFIG_CONSOLE_EXTRA_INFO +/* Return text to be printed besides the logo. */ +void video_get_info_str (int line_number, char *info) +{ + if (line_number == 1) { +#if CONFIG_MGT5100 + strcpy (info, " Total5100"); +#elif CONFIG_TOTAL5200_REV==1 + strcpy (info, " Total5200"); +#elif CONFIG_TOTAL5200_REV==2 + strcpy (info, " Total5200 Rev.2"); +#else +#error CONFIG_TOTAL5200_REV must be 1 or 2. +#endif + } else { + info [0] = '\0'; + } +} +#endif + +/* Returns SED13806 base address. First thing called in the driver. */ +unsigned int board_video_init (void) +{ + return CFG_LCD_BASE; +} + +/* Called after initializing the SED13806 and before clearing the screen. */ +void board_validate_screen (unsigned int base) +{ +} + +/* Return a pointer to the initialization sequence. */ +const S1D_REGS *board_get_regs (void) +{ + return init_regs; +} + +int board_get_width (void) +{ + return DISPLAY_WIDTH; +} + +int board_get_height (void) +{ + return DISPLAY_HEIGHT; +} + +#endif /* CONFIG_VIDEO_SED13806 */ diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 898f1f468..6383d9da1 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -18,7 +18,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -84,8 +84,8 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE - * is something else than 0x00000000. + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. */ #if defined(CONFIG_MPC5200) @@ -352,7 +352,7 @@ int post_hotkeys_pressed(void) /* * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in * CODEC or UART mode. Consumer IrDA should still be possible. - */ + */ gpio->port_config &= ~(0x07000000); gpio->port_config |= 0x03000000; diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 2bdbc9df1..e5c60bfad 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -558,7 +558,7 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) volatile uint *longp; volatile ushort *shortp; volatile u_char *cp; - + if (argc < 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; @@ -580,7 +580,7 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* data to write */ data = simple_strtoul(argv[3], NULL, 16); - + /* We want to optimize the loops to run as fast as possible. * If we have only one object, just run infinite loops. */ diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index a3af20fea..15ac16aef 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -281,54 +281,54 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("\nMPC5200 registers\n"); printf ("MBAR=%08x\n", CFG_MBAR); puts ("Memory map registers\n"); - printf ("\tCS0: start %08X\tstop %08X\tconfig %08X\ten %d\n", + printf ("\tCS0: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS0_START, *(volatile ulong*)MPC5XXX_CS0_STOP, *(volatile ulong*)MPC5XXX_CS0_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0); - printf ("\tCS1: start %08X\tstop %08X\tconfig %08X\ten %d\n", + printf ("\tCS1: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS1_START, *(volatile ulong*)MPC5XXX_CS1_STOP, *(volatile ulong*)MPC5XXX_CS1_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0); - printf ("\tCS2: start %08X\tstop %08X\tconfig %08X\ten %d\n", + printf ("\tCS2: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS2_START, *(volatile ulong*)MPC5XXX_CS2_STOP, *(volatile ulong*)MPC5XXX_CS2_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0); - printf ("\tCS3: start %08X\tstop %08X\tconfig %08X\ten %d\n", + printf ("\tCS3: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS3_START, *(volatile ulong*)MPC5XXX_CS3_STOP, *(volatile ulong*)MPC5XXX_CS3_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0); - printf ("\tCS4: start %08X\tstop %08X\tconfig %08X\ten %d\n", + printf ("\tCS4: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS4_START, *(volatile ulong*)MPC5XXX_CS4_STOP, *(volatile ulong*)MPC5XXX_CS4_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0); - printf ("\tCS5: start %08X\tstop %08X\tconfig %08X\ten %d\n", + printf ("\tCS5: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS5_START, *(volatile ulong*)MPC5XXX_CS5_STOP, *(volatile ulong*)MPC5XXX_CS5_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0); - printf ("\tCS6: start %08X\tstop %08X\tconfig %08X\ten %d\n", + printf ("\tCS6: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS6_START, *(volatile ulong*)MPC5XXX_CS6_STOP, *(volatile ulong*)MPC5XXX_CS6_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0); - printf ("\tCS7: start %08X\tstop %08X\tconfig %08X\ten %d\n", + printf ("\tCS7: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS7_START, *(volatile ulong*)MPC5XXX_CS7_STOP, *(volatile ulong*)MPC5XXX_CS7_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0); - printf ("\tBOOTCS: start %08X\tstop %08X\tconfig %08X\ten %d\n", + printf ("\tBOOTCS: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_BOOTCS_START, *(volatile ulong*)MPC5XXX_BOOTCS_STOP, *(volatile ulong*)MPC5XXX_BOOTCS_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0); - printf ("\tSDRAMCS0: %08X\n", + printf ("\tSDRAMCS0: %08X\n", *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG); - printf ("\tSDRAMCS0: %08X\n", + printf ("\tSDRAMCS0: %08X\n", *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG); #endif /* CONFIG_MPC5200 */ return 0; diff --git a/common/docecc.c b/common/docecc.c index cf45e0f6d..79adb4895 100644 --- a/common/docecc.c +++ b/common/docecc.c @@ -28,13 +28,13 @@ #include <common.h> #include <malloc.h> -#include <linux/mtd/doc2000.h> - #undef ECC_DEBUG #undef PSYCHO_DEBUG #if (CONFIG_COMMANDS & CFG_CMD_DOC) +#include <linux/mtd/doc2000.h> + /* need to undef it (from asm/termbits.h) */ #undef B0 diff --git a/drivers/cfb_console.c b/drivers/cfb_console.c index fee0386ae..138b9689b 100644 --- a/drivers/cfb_console.c +++ b/drivers/cfb_console.c @@ -1173,14 +1173,15 @@ int drv_video_init (void) skip_dev_init = 0; + /* Init video chip - returns with framebuffer cleared */ + if (video_init () == -1) + skip_dev_init = 1; + /* Force console i/o to serial ? */ if ((penv = getenv ("console")) != NULL) if (strcmp (penv, "serial") == 0) return 0; - /* Init video chip - returns with framebuffer cleared */ - if (video_init () == -1) - skip_dev_init = 1; #ifdef CONFIG_VGA_AS_SINGLE_DEVICE /* Devices VGA and Keyboard will be assigned seperately */ /* Init vga device */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 65eff423c..4b2763364 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -79,7 +79,7 @@ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#define ADD_PCI_CMD 0 /* CFG_CMD_PCI */ +#define ADD_PCI_CMD 0 /* CFG_CMD_PCI */ #else /* MPC5100 */ @@ -96,10 +96,10 @@ /* USB */ #if 0 #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE #else -#define ADD_USB_CMD 0 +#define ADD_USB_CMD 0 #endif /* POST support */ @@ -132,7 +132,7 @@ ADD_USB_CMD | \ CFG_CMD_POST_DIAG | \ CFG_CMD_DATE | \ - CFG_CMD_REGINFO | \ + CFG_CMD_REGINFO | \ CFG_CMD_MII | \ CFG_CMD_PING | \ ADD_IDE_CMD) @@ -141,7 +141,7 @@ #include <cmd_confdefs.h> #if (TEXT_BASE == 0xFC000000) /* Boot low */ -# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT 1 #endif /* @@ -149,14 +149,14 @@ */ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_PREBOOT "echo;" \ +#define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS #if defined (CONFIG_TQM5200_AA) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=$(serverip):$(rootpath)\0" \ @@ -174,13 +174,13 @@ "load=tftp 200000 $(loadfile)\0" \ "load133=tftp 200000 $(loadfile133)\0" \ "loadfile=u-boot_tqm5200_aa_mkr.bin\0" \ - "loadfile133=u-boot_tqm5200_aa_133_mkr.bin\0" \ + "loadfile133=u-boot_tqm5200_aa_133_mkr.bin\0" \ "update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0" \ "serverip=172.20.5.13\0" \ "" #else #if defined (CONFIG_TQM5200_AB) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=$(serverip):$(rootpath)\0" \ @@ -198,13 +198,13 @@ "load=tftp 200000 $(loadfile)\0" \ "load133=tftp 200000 $(loadfile133)\0" \ "loadfile=u-boot_tqm5200_ab_mkr.bin\0" \ - "loadfile133=u-boot_tqm5200_ab_133_mkr.bin\0" \ + "loadfile133=u-boot_tqm5200_ab_133_mkr.bin\0" \ "update=protect off 1:0-1; erase 1:0-1; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-1\0" \ "serverip=172.20.5.13\0" \ "" #else #if defined (CONFIG_TQM5200_AC) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=$(serverip):$(rootpath)\0" \ @@ -222,7 +222,7 @@ "load=tftp 200000 $(loadfile)\0" \ "load133=tftp 200000 $(loadfile133)\0" \ "loadfile=u-boot_tqm5200_ac_mkr.bin\0" \ - "loadfile133=u-boot_tqm5200_ac_133_mkr.bin\0" \ + "loadfile133=u-boot_tqm5200_ac_133_mkr.bin\0" \ "update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0" \ "serverip=172.20.5.13\0" \ "" @@ -235,7 +235,7 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ #if defined(CFG_IPBSPEED_133) /* @@ -328,8 +328,8 @@ #endif /* CFG_LOWBOOT */ #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks (= chip selects) */ -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ /* @@ -387,8 +387,8 @@ * Bit 0 (mask: 0x80000000): 1 * use ALT CAN position: Bits 2-3 (mask: 0x30000000): * 00 -> No Alternatives, I2C1 is used for onboard EEPROM - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard - * EEPROM + * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard + * EEPROM * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000): * 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible. @@ -495,12 +495,12 @@ *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ -#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_RESET /* reset for ide supported */ #define CONFIG_IDE_PREINIT #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ @@ -519,7 +519,7 @@ /* Offset for alternate registers */ #define CFG_ATA_ALT_OFFSET (0x005C) -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 #endif /* __CONFIG_H */ diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 29c627c62..830bf81a4 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -60,6 +60,25 @@ #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +/* + * Video console + */ +#if 1 +#define CONFIG_VIDEO_SED13806 +#define CONFIG_VIDEO_SED13806_16BPP + +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +/* #define CONFIG_VIDEO_BMP_LOGO */ +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN + +#define ADD_VIDEO_CMD CFG_CMD_BMP +#else +#define ADD_VIDEO_CMD 0 +#endif #ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */ /* @@ -114,6 +133,7 @@ CFG_CMD_EEPROM | \ CFG_CMD_FAT | \ CFG_CMD_IDE | \ + ADD_VIDEO_CMD | \ ADD_PCI_CMD | \ ADD_USB_CMD) @@ -129,7 +149,9 @@ */ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_PREBOOT "echo;" \ +#define CONFIG_PREBOOT \ + "setenv stdout serial;setenv stderr serial;" \ + "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" @@ -150,6 +172,7 @@ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_82xx\0" \ "bootfile=/tftpboot/MPC5200/uImage\0" \ + "console=serial\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -201,7 +224,7 @@ # define CFG_FLASH_SIZE 0x06000000 #endif /* CONFIG_TOTAL5200_REV */ -#if !defined(CFG_LOWBOOT) +#if defined(CFG_LOWBOOT) # define CFG_ENV_ADDR 0xFE040000 #else /* CFG_LOWBOOT */ # define CFG_ENV_ADDR 0xFFF40000 @@ -223,7 +246,7 @@ #define CFG_MBAR 0xF0000000 /* 64 kB */ #define CFG_FPGA_BASE 0xF0010000 /* 64 kB */ #define CFG_CPLD_BASE 0xF0020000 /* 64 kB */ -#define CFG_LCD_BASE 0xF0100000 /* 2048 kB */ +#define CFG_LCD_BASE 0xF1000000 /* 4096 kB */ /* Use SRAM until RAM will be available */ #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM @@ -332,8 +355,8 @@ #define CFG_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */ #define CFG_CS2_START CFG_LCD_BASE -#define CFG_CS2_SIZE 0x00200000 /* 2048 kB */ -#define CFG_CS2_CFG 0x0019FD00 /* 25WS, MX, AL, AA, CE, AS_25, DS_16 */ +#define CFG_CS2_SIZE 0x00400000 /* 4096 kB */ +#define CFG_CS2_CFG 0x0032FD00 /* 50WS, MX, AL, AA, CE, AS_25, DS_16 */ #if CONFIG_TOTAL5200_REV==1 # define CFG_CS3_START CFG_CPLD_BASE |