diff options
| -rw-r--r-- | arch/powerpc/cpu/mpc83xx/Makefile | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 8 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 4 | ||||
| -rw-r--r-- | board/freescale/c29xpcie/ddr.c | 13 | ||||
| -rw-r--r-- | drivers/mtd/spi/fsl_espi_spl.c | 5 | ||||
| -rw-r--r-- | include/configs/MPC8349EMDS.h | 1 | ||||
| -rw-r--r-- | include/configs/P1010RDB.h | 2 | ||||
| -rw-r--r-- | include/configs/T2080QDS.h | 2 |
8 files changed, 34 insertions, 5 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index c345dd6ae..cf9116274 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -38,9 +38,7 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o # Stub implementations of cache management functions for USB obj-y += cache.o -ifdef CONFIG_SYS_FSL_DDR2 -obj-$(CONFIG_MPC8349) += $(SRCTREE)/drivers/ddr/fsl/mpc85xx_ddr_gen2.o -else +ifndef CONFIG_SYS_FSL_DDRC_GEN2 obj-y += spd_sdram.o endif obj-$(CONFIG_SYS_FSL_DDR2) += law.o diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 1a58a194f..46ae80c4d 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -86,6 +86,14 @@ void get_sys_info(sys_info_t *sys_info) mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of + * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 + * it uses 6. + */ +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) + if (SVR_MAJ(get_svr()) >= 2) + mem_pll_rat *= 2; +#endif if (mem_pll_rat > 2) sys_info->freq_ddrbus *= mem_pll_rat; else diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 6a81fa73e..db84d10c5 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -886,7 +886,11 @@ delete_ccsr_l2_tlb: erratum_set_dcsr 0xb0008 0x00900000 erratum_set_dcsr 0xb0e40 0xe00a0000 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY +#ifdef CONFIG_RAMBOOT_PBL + erratum_set_ccsr 0x10f00 0x495e5000 +#else erratum_set_ccsr 0x10f00 0x415e5000 +#endif erratum_set_ccsr 0x11f00 0x415e5000 /* Make temp mapping uncacheable again, if it was initially */ diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c index 968655c1b..7c915b036 100644 --- a/board/freescale/c29xpcie/ddr.c +++ b/board/freescale/c29xpcie/ddr.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <i2c.h> #include <asm/fsl_law.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> @@ -92,3 +93,15 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; } } + +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd, + sizeof(generic_spd_eeprom_t)); + + if (ret) { + printf("DDR: failed to read SPD from address %u\n", + i2c_address); + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c index 6263d8c22..e5ac79b95 100644 --- a/drivers/mtd/spi/fsl_espi_spl.c +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -31,6 +31,10 @@ void spi_boot(void) hang(); } +#ifdef CONFIG_FSL_CORENET + offset = CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS; + code_len = CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE; +#else /* * Load U-Boot image from SPI flash into RAM */ @@ -50,6 +54,7 @@ void spi_boot(void) code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE); /* Skip spl code */ code_len = code_len - CONFIG_SPL_MAX_SIZE; +#endif /* copy code to DDR */ spi_flash_read(flash, offset, code_len, (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST); diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index a80a6966b..037484104 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -67,6 +67,7 @@ */ #define CONFIG_SYS_FSL_DDR2 #ifdef CONFIG_SYS_FSL_DDR2 +#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x52 #define SPD_EEPROM_ADDRESS2 0x51 diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index eab386add..1ed5e1df2 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -173,7 +173,7 @@ #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x1fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ diff --git a/include/configs/T2080QDS.h b/include/configs/T2080QDS.h index ad0981697..bff001f43 100644 --- a/include/configs/T2080QDS.h +++ b/include/configs/T2080QDS.h @@ -155,7 +155,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR3 -#define CONFIG_FSL_DDR_INTERACTIVE +#undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 |