diff options
117 files changed, 820 insertions, 1103 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 260c3e65b..a7f9b8737 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -319,8 +319,8 @@ Ricardo Ribalda <ricardo.ribalda@uam.es> ml507 PPC440x5 v5fx30teval PPC440x5 - xilinx-pp440-generic PPC440x5 - xilinx-pp405-generic PPC405 + xilinx-ppc405-generic PPC405 + xilinx-ppc440-generic PPC440x5 Stefan Roese <sr@denx.de> @@ -3121,7 +3121,7 @@ mimc200_config : unconfig rsk7203_config: unconfig @ >include/config.h @echo "#define CONFIG_RSK7203 1" >> include/config.h - @./mkconfig -a $(@:_config=) sh sh2 rsk7203 + @./mkconfig -a $(@:_config=) sh sh2 rsk7203 renesas ######################################################################### ## sh3 (Renesas SuperH) @@ -3144,7 +3144,7 @@ ms7720se_config: unconfig MigoR_config : unconfig @mkdir -p $(obj)include @echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h - @./mkconfig -a $(@:_config=) sh sh4 MigoR + @./mkconfig -a $(@:_config=) sh sh4 MigoR renesas ms7750se_config: unconfig @mkdir -p $(obj)include @@ -3159,27 +3159,27 @@ ms7722se_config : unconfig r2dplus_config : unconfig @mkdir -p $(obj)include @echo "#define CONFIG_R2DPLUS 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) sh sh4 r2dplus + @$(MKCONFIG) -a $(@:_config=) sh sh4 r2dplus renesas r7780mp_config: unconfig @mkdir -p $(obj)include @echo "#define CONFIG_R7780MP 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) sh sh4 r7780mp + @$(MKCONFIG) -a $(@:_config=) sh sh4 r7780mp renesas sh7763rdp_config : unconfig @mkdir -p $(obj)include @echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) sh sh4 sh7763rdp + @$(MKCONFIG) -a $(@:_config=) sh sh4 sh7763rdp renesas sh7785lcr_config : unconfig @ >include/config.h @echo "#define CONFIG_SH7785LCR 1" >> include/config.h - @$(MKCONFIG) -a $(@:_config=) sh sh4 sh7785lcr + @$(MKCONFIG) -a $(@:_config=) sh sh4 sh7785lcr renesas ap325rxa_config : unconfig @mkdir -p $(obj)include @echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) sh sh4 ap325rxa + @$(MKCONFIG) -a $(@:_config=) sh sh4 ap325rxa renesas #======================================================================== # SPARC @@ -151,6 +151,7 @@ Directory Hierarchy: - arm926ejs Files specific to ARM 926 CPUs - arm1136 Files specific to ARM 1136 CPUs - at32ap Files specific to Atmel AVR32 AP CPUs + - blackfin Files specific to Analog Devices Blackfin CPUs - i386 Files specific to i386 CPUs - ixp Files specific to Intel XScale IXP CPUs - leon2 Files specific to Gaisler LEON2 SPARC CPU @@ -182,6 +183,7 @@ Directory Hierarchy: - include Header Files - lib_arm Files generic to ARM architecture - lib_avr32 Files generic to AVR32 architecture +- lib_blackfin Files generic to Blackfin architecture - lib_generic Files generic to all architectures - lib_i386 Files generic to i386 architecture - lib_m68k Files generic to m68k architecture diff --git a/blackfin_config.mk b/blackfin_config.mk index a9a3d1a17..c8be75e08 100644 --- a/blackfin_config.mk +++ b/blackfin_config.mk @@ -24,7 +24,7 @@ CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU))) CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE))) -PLATFORM_RELFLAGS += -ffixed-P5 +PLATFORM_RELFLAGS += -ffixed-P5 -fomit-frame-pointer PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN ifneq (,$(CONFIG_BFIN_CPU)) diff --git a/board/avnet/fx12mm/xparameters.h b/board/avnet/fx12mm/xparameters.h index f7031b347..4410f19b7 100644 --- a/board/avnet/fx12mm/xparameters.h +++ b/board/avnet/fx12mm/xparameters.h @@ -46,6 +46,6 @@ #define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 /* FLASH */ -#define XPAR_FLASH_2MX16_MEM0_BASEADDR 0xFFC00000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000 #endif diff --git a/board/bf533-ezkit/u-boot.lds.S b/board/bf533-ezkit/u-boot.lds.S index 538a19f81..70764acf1 100644 --- a/board/bf533-ezkit/u-boot.lds.S +++ b/board/bf533-ezkit/u-boot.lds.S @@ -54,6 +54,8 @@ SECTIONS { .text : { + cpu/blackfin/start.o (.text) + #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within * the sector before the environment sector. If it throws @@ -61,7 +63,6 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/start.o (.text) cpu/blackfin/traps.o (.text) cpu/blackfin/interrupt.o (.text) cpu/blackfin/serial.o (.text) @@ -74,6 +75,10 @@ SECTIONS common/env_embedded.o (.text) #endif + __initcode_start = .; + cpu/blackfin/initcode.o (.text) + __initcode_end = .; + *(.text .text.*) } >ram diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index a113c40fd..0c6324b4b 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -26,7 +26,6 @@ */ #include <common.h> -#include <asm/mem_init.h> #include <asm/io.h> #include "bf533-stamp.h" diff --git a/board/bf533-stamp/u-boot.lds.S b/board/bf533-stamp/u-boot.lds.S index 97ebd7926..187309f3f 100644 --- a/board/bf533-stamp/u-boot.lds.S +++ b/board/bf533-stamp/u-boot.lds.S @@ -54,6 +54,8 @@ SECTIONS { .text : { + cpu/blackfin/start.o (.text) + #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within * the sector before the environment sector. If it throws @@ -61,7 +63,6 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/start.o (.text) cpu/blackfin/traps.o (.text) cpu/blackfin/interrupt.o (.text) cpu/blackfin/serial.o (.text) @@ -72,6 +73,10 @@ SECTIONS common/env_embedded.o (.text) #endif + __initcode_start = .; + cpu/blackfin/initcode.o (.text) + __initcode_end = .; + *(.text .text.*) } >ram diff --git a/board/bf537-stamp/u-boot.lds.S b/board/bf537-stamp/u-boot.lds.S index 97ebd7926..187309f3f 100644 --- a/board/bf537-stamp/u-boot.lds.S +++ b/board/bf537-stamp/u-boot.lds.S @@ -54,6 +54,8 @@ SECTIONS { .text : { + cpu/blackfin/start.o (.text) + #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within * the sector before the environment sector. If it throws @@ -61,7 +63,6 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/start.o (.text) cpu/blackfin/traps.o (.text) cpu/blackfin/interrupt.o (.text) cpu/blackfin/serial.o (.text) @@ -72,6 +73,10 @@ SECTIONS common/env_embedded.o (.text) #endif + __initcode_start = .; + cpu/blackfin/initcode.o (.text) + __initcode_end = .; + *(.text .text.*) } >ram diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index a74ff0db6..7f8598c71 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -1,8 +1,7 @@ /* - * U-boot - ezkit561.c + * U-boot - main board file * - * Copyright (c) 2005 Bas Vermeulen <bas@buyways.nl> - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005-2008 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -33,7 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { - printf("CPU: ADSP BF561\n"); printf("Board: ADI BF561 EZ-Kit Lite board\n"); printf(" Support: http://blackfin.uclinux.org/\n"); return 0; @@ -57,18 +55,3 @@ phys_size_t initdram(int board_type) gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; return CONFIG_SYS_MAX_RAM_SIZE; } - -#if defined(CONFIG_MISC_INIT_R) -/* miscellaneous platform dependent initialisations */ -int misc_init_r(void) -{ - /* Keep PF12 low to be able to drive the USB-LAN Extender */ - *pFIO0_DIR = 0x0000; - *pFIO0_FLAG_C = 0x1000; /* Clear PF12 */ - SSYNC(); - *pFIO0_POLAR = 0x0000; - SSYNC(); - - return 0; -} -#endif diff --git a/board/bf561-ezkit/u-boot.lds.S b/board/bf561-ezkit/u-boot.lds.S index 3defef45a..99d6be634 100644 --- a/board/bf561-ezkit/u-boot.lds.S +++ b/board/bf561-ezkit/u-boot.lds.S @@ -54,6 +54,8 @@ SECTIONS { .text : { + cpu/blackfin/start.o (.text) + #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within * the sector before the environment sector. If it throws @@ -61,7 +63,6 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/start.o (.text) cpu/blackfin/traps.o (.text) cpu/blackfin/interrupt.o (.text) cpu/blackfin/serial.o (.text) @@ -74,6 +75,10 @@ SECTIONS common/env_embedded.o (.text) #endif + __initcode_start = .; + cpu/blackfin/initcode.o (.text) + __initcode_end = .; + *(.text .text.*) } >ram diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c index d88b3876d..ad490c349 100644 --- a/board/esd/common/cmd_loadpci.c +++ b/board/esd/common/cmd_loadpci.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005-2008 * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -23,6 +23,9 @@ #include <common.h> #include <command.h> +#if !defined(CONFIG_440) +#include <asm/4xx_pci.h> +#endif #if defined(CONFIG_CMD_BSP) @@ -36,18 +39,24 @@ extern int do_autoscript (cmd_tbl_t *, int, int, char *[]); */ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - unsigned int *ptr = 0; + u32 *ptr = 0; int count = 0; int count2 = 0; char addr[16]; char str[] = "\\|/-"; char *local_args[2]; + u32 la, ptm1la; +#if defined(CONFIG_440) + ptm1la = in32r(PCIX0_PTM1LA); +#else + ptm1la = in32r(PTM1LA); +#endif while(1) { /* * Mark sync address */ - ptr = 0; + ptr = (u32 *)ptm1la; memset(ptr, 0, 0x20); *ptr = 0xffffffff; @@ -74,7 +83,8 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } printf("\nGot bootcode %08x: ", *ptr); - sprintf(addr, "%08x", *ptr & ADDRMASK); + la = ptm1la + (*ptr & ADDRMASK); + sprintf(addr, "%08x", la); switch (*ptr & ~ADDRMASK) { case 0: @@ -83,8 +93,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ printf("booting image at addr 0x%s ...\n", addr); setenv("loadaddr", addr); - - do_bootm (cmdtp, 0, 0, NULL); + do_bootm(cmdtp, 0, 0, NULL); break; case 1: @@ -92,7 +101,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Boot image via autoscr */ printf("executing script at addr 0x%s ...\n", addr); - local_args[0] = addr; local_args[1] = NULL; do_autoscript(cmdtp, 0, 1, local_args); @@ -103,7 +111,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Call run_cmd */ printf("running command at addr 0x%s ...\n", addr); - run_command ((char*)(*ptr & ADDRMASK), 0); + run_command((char*)la, 0); break; default: diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index 38ee74eb4..3f0dca087 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -26,6 +26,9 @@ #include <asm/io.h> #include <asm/cache.h> #include <asm/processor.h> +#if defined(CONFIG_LOGBUFFER) +#include <logbuff.h> +#endif #include "pmc440.h" @@ -343,14 +346,11 @@ extern env_t *env_ptr; int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - u32 memsize; - u32 pram, env_base; + u32 pram, nextbase, base; char *v; u32 param; ulong *lptr; - memsize = gd->bd->bi_memsize; - v = getenv("pram"); if (v) pram = simple_strtoul(v, NULL, 10); @@ -359,21 +359,42 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } - param = memsize - (pram << 10); + base = gd->bd->bi_memsize; +#if defined(CONFIG_LOGBUFFER) + base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD; +#endif + /* + * gd->bd->bi_memsize == physical ram size - CFG_MEM_TOP_HIDE + */ + param = base - (pram << 10); printf("PARAM: @%08x\n", param); + debug("memsize=0x%08x, base=0x%08x\n", gd->bd->bi_memsize, base); + /* clear entire PA ram */ memset((void*)param, 0, (pram << 10)); - env_base = memsize - 4096 - ((CONFIG_ENV_SIZE + 4096) & ~(4096-1)); - memcpy((void*)env_base, env_ptr, CONFIG_ENV_SIZE); - lptr = (ulong*)memsize; - *(--lptr) = CONFIG_ENV_SIZE; - *(--lptr) = memsize - env_base; - *(--lptr) = crc32(0, (void*)(memsize - 0x08), 0x08); - *(--lptr) = 0; + /* reserve 4k for pointer field */ + nextbase = base - 4096; + lptr = (ulong*)(base); + + /* + * *(--lptr) = item_size; + * *(--lptr) = base - item_base = distance from field top; + */ + + /* env is first (4k aligned) */ + nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1)); + memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE); + *(--lptr) = CONFIG_ENV_SIZE; /* size */ + *(--lptr) = base - nextbase; /* offset | type=0 */ + + /* free section */ + *(--lptr) = nextbase - param; /* size */ + *(--lptr) = (base - param) | 126; /* offset | type=126 */ - /* make sure data can be accessed through PCI */ - flush_dcache_range(param, param + (pram << 10) - 1); + /* terminate pointer field */ + *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10); + *(--lptr) = 0; /* offset=0 -> terminator */ return 0; } U_BOOT_CMD( @@ -385,28 +406,11 @@ U_BOOT_CMD( int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - if (argc > 1) { - if (argv[1][0] == '0') { - /* assert */ - printf("self-reset# asserted\n"); - out_be32((void*)GPIO0_TCR, - in_be32((void*)GPIO0_TCR) | GPIO0_SELF_RST); - } else { - /* deassert */ - printf("self-reset# deasserted\n"); - out_be32((void*)GPIO0_TCR, - in_be32((void*)GPIO0_TCR) & ~GPIO0_SELF_RST); - } - } else { - printf("self-reset# is %s\n", - in_be32((void*)GPIO0_TCR) & GPIO0_SELF_RST ? - "active" : "inactive"); - } - + in_be32((void*)CONFIG_SYS_RESET_BASE); return 0; } U_BOOT_CMD( - selfreset, 2, 1, do_selfreset, + selfreset, 1, 1, do_selfreset, "selfreset- assert self-reset# signal\n", NULL ); diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c index a35f42bd5..a2eda32ac 100644 --- a/board/esd/pmc440/fpga.c +++ b/board/esd/pmc440/fpga.c @@ -220,8 +220,9 @@ int fpga_post_config_fn(int cookie) FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK); - /* NGCC only: enable ledlink */ - if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) + /* NGCC/CANDES only: enable ledlink */ + if ((s = getenv("bd_type")) && + ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) FPGA_SETBITS(&fpga->ctrla, 0x29f8c000); return rc; diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 013815e26..8563d7d5f 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2008 + * (Cg) Copyright 2007-2008 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. * Based on board/amcc/sequoia/sequoia.c * @@ -45,9 +45,11 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern void __ft_board_setup(void *blob, bd_t *bd); ulong flash_get_size(ulong base, int banknum); int pci_is_66mhz(void); +int is_monarch(void); int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); @@ -107,9 +109,9 @@ int board_early_init_f(void) */ out32(GPIO0_OR, 0x40000002); out32(GPIO0_TCR, 0x4c90011f); - out32(GPIO0_OSRL, 0x28011400); + out32(GPIO0_OSRL, 0x28051400); out32(GPIO0_OSRH, 0x55005000); - out32(GPIO0_TSRL, 0x08011400); + out32(GPIO0_TSRL, 0x08051400); out32(GPIO0_TSRH, 0x55005000); out32(GPIO0_ISR1L, 0x54000000); out32(GPIO0_ISR1H, 0x00000000); @@ -196,6 +198,23 @@ int board_early_init_f(void) return 0; } +#if defined(CONFIG_MISC_INIT_F) +int misc_init_f(void) +{ + struct pci_controller hose; + hose.first_busno = 0; + hose.last_busno = 0; + hose.region_count = 0; + + if (getenv("pciearly") && (!is_monarch())) { + printf("PCI: early target init\n"); + pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA); + pci_target_init(&hose); + } + return 0; +} +#endif + /* * misc_init_r. */ @@ -207,6 +226,7 @@ int misc_init_r(void) unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; + unsigned long sdr0_srst0, sdr0_srst1; char *act = getenv("usbact"); /* @@ -256,7 +276,7 @@ int misc_init_r(void) /* * USB suff... */ - if ((act == NULL || strcmp(act, "hostdev") == 0) && + if ((act == NULL || strcmp(act, "host") == 0) && !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){ /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); @@ -290,12 +310,46 @@ int misc_init_r(void) mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr); - /* clear resets */ + /* + * Take USB out of reset: + * -Initial status = all cores are in reset + * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores + * -wait 1 ms + * -deassert reset to PHY + * -wait 1 ms + * -deassert reset to HOST + * -wait 4 ms + * -deassert all other resets + */ + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \ + SDR0_SRST1_P4OPB0 | \ + SDR0_SRST1_OPBA2 | \ + SDR0_SRST1_PLB42OPB1 | \ + SDR0_SRST1_OPB2PLB40); + mtsdr(SDR0_SRST1, sdr0_srst1); udelay(1000); - mtsdr(SDR0_SRST1, 0x00000000); + + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~SDR0_SRST1_USB20PHY; + mtsdr(SDR0_SRST1, sdr0_srst1); udelay(1000); + + mfsdr(SDR0_SRST0, sdr0_srst0); + sdr0_srst0 &= ~SDR0_SRST0_USB2H; + mtsdr(SDR0_SRST0, sdr0_srst0); + udelay(4000); + + /* finally all the other resets */ + mtsdr(SDR0_SRST1, 0x00000000); mtsdr(SDR0_SRST0, 0x00000000); + if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) { + /* enable power on USB socket */ + out_be32((void*)GPIO1_OR, + in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N); + } + printf("USB: Host\n"); } else if ((strcmp(act, "dev") == 0) || @@ -547,14 +601,14 @@ void pci_target_init(struct pci_controller *hose) out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16)); out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16)); } else { - /* BAR2: default: 16 MB FPGA + registers */ - out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */ + /* BAR2: default: 4MB FPGA */ + out32r(PCIX0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */ out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */ } if (is_monarch()) { /* BAR2: map FPGA registers behind system memory at 1GB */ - pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008); + pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008); } /* @@ -562,8 +616,8 @@ void pci_target_init(struct pci_controller *hose) */ /* Program the board's vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_SYS_PCI_SUBSYS_VENDORID); /* disabled for PMC405 backward compatibility */ /* Configure command register as bus master */ @@ -571,19 +625,19 @@ void pci_target_init(struct pci_controller *hose) /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1); /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); + pci_hose_write_config_word(hose, 0, PCI_ERREN, 0); pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); if (!is_monarch()) { /* Program the board's subsystem id/classcode */ - pci_write_config_word(0, PCI_SUBSYSTEM_ID, - CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH); - pci_write_config_word(0, PCI_CLASS_SUB_CODE, - CONFIG_SYS_PCI_CLASSCODE_NONMONARCH); + pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, + CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH); + pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE, + CONFIG_SYS_PCI_CLASSCODE_NONMONARCH); /* PCI configuration done: release ERREADY */ out_be32((void*)GPIO1_OR, @@ -592,11 +646,14 @@ void pci_target_init(struct pci_controller *hose) in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY); } else { /* Program the board's subsystem id/classcode */ - pci_write_config_word(0, PCI_SUBSYSTEM_ID, - CONFIG_SYS_PCI_SUBSYS_ID_MONARCH); - pci_write_config_word(0, PCI_CLASS_SUB_CODE, - CONFIG_SYS_PCI_CLASSCODE_MONARCH); + pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, + CONFIG_SYS_PCI_SUBSYS_ID_MONARCH); + pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE, + CONFIG_SYS_PCI_CLASSCODE_MONARCH); } + + /* enable host configuration */ + pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ @@ -626,6 +683,12 @@ static void wait_for_pci_ready(void) { int i; char *s = getenv("pcidelay"); + /* + * We have our own handling of the pcidelay variable. + * Using CONFIG_PCI_BOOTDELAY enables pausing for host + * and adapter devices. For adapter devices we do not + * want this. + */ if (s) { int ms = simple_strtoul(s, NULL, 10); printf("PCI: Waiting for %d ms\n", ms); @@ -851,7 +914,7 @@ int usb_board_init(void) char *act = getenv("usbact"); int i; - if ((act == NULL || strcmp(act, "hostdev") == 0) && + if ((act == NULL || strcmp(act, "host") == 0) && !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) /* enable power on USB socket */ out_be32((void*)GPIO1_OR, @@ -876,3 +939,24 @@ int usb_board_init_fail(void) return 0; } #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + int rc; + + __ft_board_setup(blob, bd); + + /* + * Disable PCI in non-monarch mode. + */ + if (!is_monarch()) { + rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status", + "disabled", sizeof("disabled"), 1); + if (rc) { + printf("Unable to update property status in PCI node, err=%s\n", + fdt_strerror(rc)); + } + } +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h index d834f2585..295cec1e3 100644 --- a/board/esd/pmc440/pmc440.h +++ b/board/esd/pmc440/pmc440.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. * * See file CREDITS for list of people who contributed to this @@ -24,8 +24,7 @@ #ifndef __PMC440_H__ #define __PMC440_H__ - -/*----------------------------------------------------------------------- +/* * GPIOs */ #define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */ @@ -41,9 +40,10 @@ #define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */ #define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */ #define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */ -#define GPIO0_SELF_RST (0x80000000 >> 6) /* GPIO6 OD */ -/* FPGA programming pin configuration */ +/* + * FPGA programming pin configuration + */ #define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */ #define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */ #define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */ @@ -51,7 +51,7 @@ #define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */ #define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */ -/*----------------------------------------------------------------------- +/* * FPGA interface */ #define FPGA_BA CONFIG_SYS_FPGA_BASE0 @@ -103,7 +103,6 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; #define RESET_OUT (1 << 19) #define IRIGB_R_OUT (1 << 14) - /* status register */ #define STATUS_VERSION_SHIFT 24 #define STATUS_VERSION_MASK 0xff000000 @@ -115,13 +114,11 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; #define STATUS_FIFO_ISF (1 << 9) #define STATUS_HOST_ISF (1 << 8) - /* inputs */ #define RESET_IN (1 << 0) #define CLOCK_IN (1 << 1) #define IRIGB_R_IN (1 << 5) - /* hostctrl register */ #define HOSTCTRL_PMCRSTOUT_GATE (1 << 17) #define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16) @@ -137,7 +134,7 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; #define NGCC_CTRL_BASE (CONFIG_SYS_FPGA_BASE0 + 0x80000) #define NGCC_CTRL_FPGARST_N (1 << 2) -/*----------------------------------------------------------------------- +/* * FPGA to PPC interrupt */ #define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */ diff --git a/board/MigoR/Makefile b/board/renesas/MigoR/Makefile index 661b59d00..661b59d00 100644 --- a/board/MigoR/Makefile +++ b/board/renesas/MigoR/Makefile diff --git a/board/MigoR/config.mk b/board/renesas/MigoR/config.mk index 2c5085a91..2c5085a91 100644 --- a/board/MigoR/config.mk +++ b/board/renesas/MigoR/config.mk diff --git a/board/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S index e48f7b3b1..e48f7b3b1 100644 --- a/board/MigoR/lowlevel_init.S +++ b/board/renesas/MigoR/lowlevel_init.S diff --git a/board/MigoR/migo_r.c b/board/renesas/MigoR/migo_r.c index 204ca78fa..204ca78fa 100644 --- a/board/MigoR/migo_r.c +++ b/board/renesas/MigoR/migo_r.c diff --git a/board/MigoR/u-boot.lds b/board/renesas/MigoR/u-boot.lds index f9c1effa4..f9c1effa4 100644 --- a/board/MigoR/u-boot.lds +++ b/board/renesas/MigoR/u-boot.lds diff --git a/board/ap325rxa/Makefile b/board/renesas/ap325rxa/Makefile index 21f3e6e29..21f3e6e29 100644 --- a/board/ap325rxa/Makefile +++ b/board/renesas/ap325rxa/Makefile diff --git a/board/ap325rxa/ap325rxa.c b/board/renesas/ap325rxa/ap325rxa.c index 9f1112a43..9f1112a43 100644 --- a/board/ap325rxa/ap325rxa.c +++ b/board/renesas/ap325rxa/ap325rxa.c diff --git a/board/ap325rxa/config.mk b/board/renesas/ap325rxa/config.mk index b52a5e5cb..b52a5e5cb 100644 --- a/board/ap325rxa/config.mk +++ b/board/renesas/ap325rxa/config.mk diff --git a/board/ap325rxa/cpld-ap325rxa.c b/board/renesas/ap325rxa/cpld-ap325rxa.c index 16fadcbca..16fadcbca 100644 --- a/board/ap325rxa/cpld-ap325rxa.c +++ b/board/renesas/ap325rxa/cpld-ap325rxa.c diff --git a/board/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S index 4f6658879..4f6658879 100644 --- a/board/ap325rxa/lowlevel_init.S +++ b/board/renesas/ap325rxa/lowlevel_init.S diff --git a/board/ap325rxa/u-boot.lds b/board/renesas/ap325rxa/u-boot.lds index e9f8dc0de..e9f8dc0de 100644 --- a/board/ap325rxa/u-boot.lds +++ b/board/renesas/ap325rxa/u-boot.lds diff --git a/board/r2dplus/Makefile b/board/renesas/r2dplus/Makefile index e96a8aa98..e96a8aa98 100644 --- a/board/r2dplus/Makefile +++ b/board/renesas/r2dplus/Makefile diff --git a/board/r2dplus/config.mk b/board/renesas/r2dplus/config.mk index 1ec7dcc60..1ec7dcc60 100644 --- a/board/r2dplus/config.mk +++ b/board/renesas/r2dplus/config.mk diff --git a/board/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index 5755de87b..5755de87b 100644 --- a/board/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S diff --git a/board/r2dplus/r2dplus.c b/board/renesas/r2dplus/r2dplus.c index 0c08d6859..0c08d6859 100644 --- a/board/r2dplus/r2dplus.c +++ b/board/renesas/r2dplus/r2dplus.c diff --git a/board/r2dplus/u-boot.lds b/board/renesas/r2dplus/u-boot.lds index 040e53017..040e53017 100644 --- a/board/r2dplus/u-boot.lds +++ b/board/renesas/r2dplus/u-boot.lds diff --git a/board/r7780mp/Makefile b/board/renesas/r7780mp/Makefile index c100e7e2a..c100e7e2a 100644 --- a/board/r7780mp/Makefile +++ b/board/renesas/r7780mp/Makefile diff --git a/board/r7780mp/config.mk b/board/renesas/r7780mp/config.mk index 6a045a15c..6a045a15c 100644 --- a/board/r7780mp/config.mk +++ b/board/renesas/r7780mp/config.mk diff --git a/board/r7780mp/lowlevel_init.S b/board/renesas/r7780mp/lowlevel_init.S index ab0499a3a..ab0499a3a 100644 --- a/board/r7780mp/lowlevel_init.S +++ b/board/renesas/r7780mp/lowlevel_init.S diff --git a/board/r7780mp/r7780mp.c b/board/renesas/r7780mp/r7780mp.c index 396e4b6db..396e4b6db 100644 --- a/board/r7780mp/r7780mp.c +++ b/board/renesas/r7780mp/r7780mp.c diff --git a/board/r7780mp/r7780mp.h b/board/renesas/r7780mp/r7780mp.h index 476a41354..476a41354 100644 --- a/board/r7780mp/r7780mp.h +++ b/board/renesas/r7780mp/r7780mp.h diff --git a/board/r7780mp/u-boot.lds b/board/renesas/r7780mp/u-boot.lds index eaa05d0d5..eaa05d0d5 100644 --- a/board/r7780mp/u-boot.lds +++ b/board/renesas/r7780mp/u-boot.lds diff --git a/board/rsk7203/Makefile b/board/renesas/rsk7203/Makefile index 7365d1930..7365d1930 100644 --- a/board/rsk7203/Makefile +++ b/board/renesas/rsk7203/Makefile diff --git a/board/rsk7203/config.mk b/board/renesas/rsk7203/config.mk index 61aa51f2b..61aa51f2b 100644 --- a/board/rsk7203/config.mk +++ b/board/renesas/rsk7203/config.mk diff --git a/board/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index e4d6f9e7d..e4d6f9e7d 100644 --- a/board/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S diff --git a/board/rsk7203/rsk7203.c b/board/renesas/rsk7203/rsk7203.c index 2cbd45e04..2cbd45e04 100644 --- a/board/rsk7203/rsk7203.c +++ b/board/renesas/rsk7203/rsk7203.c diff --git a/board/rsk7203/u-boot.lds b/board/renesas/rsk7203/u-boot.lds index 63e5b9744..63e5b9744 100644 --- a/board/rsk7203/u-boot.lds +++ b/board/renesas/rsk7203/u-boot.lds diff --git a/board/sh7763rdp/Makefile b/board/renesas/sh7763rdp/Makefile index 62a683d57..62a683d57 100644 --- a/board/sh7763rdp/Makefile +++ b/board/renesas/sh7763rdp/Makefile diff --git a/board/sh7763rdp/config.mk b/board/renesas/sh7763rdp/config.mk index c52dbfd7b..c52dbfd7b 100644 --- a/board/sh7763rdp/config.mk +++ b/board/renesas/sh7763rdp/config.mk diff --git a/board/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S index 2a44eee1a..2a44eee1a 100644 --- a/board/sh7763rdp/lowlevel_init.S +++ b/board/renesas/sh7763rdp/lowlevel_init.S diff --git a/board/sh7763rdp/sh7763rdp.c b/board/renesas/sh7763rdp/sh7763rdp.c index 88bab70e3..88bab70e3 100644 --- a/board/sh7763rdp/sh7763rdp.c +++ b/board/renesas/sh7763rdp/sh7763rdp.c diff --git a/board/sh7763rdp/u-boot.lds b/board/renesas/sh7763rdp/u-boot.lds index 7177416c2..7177416c2 100644 --- a/board/sh7763rdp/u-boot.lds +++ b/board/renesas/sh7763rdp/u-boot.lds diff --git a/board/sh7785lcr/Makefile b/board/renesas/sh7785lcr/Makefile index b1b538c9d..b1b538c9d 100644 --- a/board/sh7785lcr/Makefile +++ b/board/renesas/sh7785lcr/Makefile diff --git a/board/sh7785lcr/config.mk b/board/renesas/sh7785lcr/config.mk index 20807dfc5..20807dfc5 100644 --- a/board/sh7785lcr/config.mk +++ b/board/renesas/sh7785lcr/config.mk diff --git a/board/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S index 50e1789cc..50e1789cc 100644 --- a/board/sh7785lcr/lowlevel_init.S +++ b/board/renesas/sh7785lcr/lowlevel_init.S diff --git a/board/sh7785lcr/rtl8169.h b/board/renesas/sh7785lcr/rtl8169.h index ca9c0bd94..ca9c0bd94 100644 --- a/board/sh7785lcr/rtl8169.h +++ b/board/renesas/sh7785lcr/rtl8169.h diff --git a/board/sh7785lcr/rtl8169_mac.c b/board/renesas/sh7785lcr/rtl8169_mac.c index bf0ba145d..bf0ba145d 100644 --- a/board/sh7785lcr/rtl8169_mac.c +++ b/board/renesas/sh7785lcr/rtl8169_mac.c diff --git a/board/sh7785lcr/selfcheck.c b/board/renesas/sh7785lcr/selfcheck.c index ce0620f68..ce0620f68 100644 --- a/board/sh7785lcr/selfcheck.c +++ b/board/renesas/sh7785lcr/selfcheck.c diff --git a/board/sh7785lcr/sh7785lcr.c b/board/renesas/sh7785lcr/sh7785lcr.c index 786c758a9..786c758a9 100644 --- a/board/sh7785lcr/sh7785lcr.c +++ b/board/renesas/sh7785lcr/sh7785lcr.c diff --git a/board/sh7785lcr/u-boot.lds b/board/renesas/sh7785lcr/u-boot.lds index 231769f3b..231769f3b 100644 --- a/board/sh7785lcr/u-boot.lds +++ b/board/renesas/sh7785lcr/u-boot.lds diff --git a/common/fdt_support.c b/common/fdt_support.c index d483d66f1..5a83bca48 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -602,9 +602,12 @@ int fdt_resize(void *blob) } } - /* Calculate the actual size of the fdt */ + /* + * Calculate the actual size of the fdt + * plus the size needed for fdt_add_mem_rsv + */ actualsize = fdt_off_dt_strings(blob) + - fdt_size_dt_strings(blob); + fdt_size_dt_strings(blob) + sizeof(struct fdt_reserve_entry); /* Make it so the fdt ends on a page boundary */ actualsize = ALIGN(actualsize, 0x1000); diff --git a/cpu/blackfin/Makefile b/cpu/blackfin/Makefile index f194a3835..8fed4b422 100644 --- a/cpu/blackfin/Makefile +++ b/cpu/blackfin/Makefile @@ -16,7 +16,7 @@ LIB = $(obj)lib$(CPU).a EXTRA := CEXTRA := initcode.o SEXTRA := start.o -SOBJS := interrupt.o cache.o flush.o +SOBJS := interrupt.o cache.o COBJS := cpu.o traps.o interrupts.o reset.o serial.o i2c.o watchdog.o ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) diff --git a/cpu/blackfin/cpu.c b/cpu/blackfin/cpu.c index 53de5aba6..9efd88e7e 100644 --- a/cpu/blackfin/cpu.c +++ b/cpu/blackfin/cpu.c @@ -14,46 +14,11 @@ #include <asm/blackfin.h> #include <asm/cplb.h> #include <asm/mach-common/bits/core.h> -#include <asm/mach-common/bits/mpu.h> #include <asm/mach-common/bits/trace.h> #include "cpu.h" #include "serial.h" -void icache_enable(void) -{ - bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() | (IMC | ENICPLB)); - SSYNC(); -} - -void icache_disable(void) -{ - bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() & ~(IMC | ENICPLB)); - SSYNC(); -} - -int icache_status(void) -{ - return bfin_read_IMEM_CONTROL() & ENICPLB; -} - -void dcache_enable(void) -{ - bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() | (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)); - SSYNC(); -} - -void dcache_disable(void) -{ - bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0)); - SSYNC(); -} - -int dcache_status(void) -{ - return bfin_read_DMEM_CONTROL() & ENDCPLB; -} - __attribute__ ((__noreturn__)) void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) { @@ -133,9 +98,8 @@ int irq_init(void) bfin_write_EVT15(evt_default); bfin_write_ILAT(0); CSYNC(); - /* enable all interrupts except for core timer */ - irq_flags = 0xffffffbf; + /* enable hardware error irq */ + irq_flags = 0x3f; local_irq_enable(); - CSYNC(); return 0; } diff --git a/cpu/blackfin/flush.S b/cpu/blackfin/flush.S deleted file mode 100644 index 417f798f8..000000000 --- a/cpu/blackfin/flush.S +++ /dev/null @@ -1,230 +0,0 @@ -/* flush.S - low level cache flushing routines - * Copyright (C) 2003-2007 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#include <config.h> -#include <asm/blackfin.h> -#include <asm/cplb.h> -#include <asm/mach-common/bits/mpu.h> - -.text - -/* This is an external function being called by the user - * application through __flush_cache_all. Currently this function - * serves the purpose of flushing all the pending writes in - * in the data cache. - */ - -ENTRY(_flush_data_cache) - [--SP] = ( R7:6, P5:4 ); - LINK 12; - SP += -12; - P5.H = HI(DCPLB_ADDR0); - P5.L = LO(DCPLB_ADDR0); - P4.H = HI(DCPLB_DATA0); - P4.L = LO(DCPLB_DATA0); - R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z); - R6 = 16; -.Lnext: R0 = [P5++]; - R1 = [P4++]; - CC = BITTST(R1, 14); /* Is it write-through?*/ - IF CC JUMP .Lskip; /* If so, ignore it.*/ - R2 = R1 & R7; /* Is it a dirty, cached page?*/ - CC = R2; - IF !CC JUMP .Lskip; /* If not, ignore it.*/ - [--SP] = RETS; - CALL _dcplb_flush; /* R0 = page, R1 = data*/ - RETS = [SP++]; -.Lskip: R6 += -1; - CC = R6; - IF CC JUMP .Lnext; - SSYNC; - SP += 12; - UNLINK; - ( R7:6, P5:4 ) = [SP++]; - RTS; -ENDPROC(_flush_data_cache) - -/* This is an internal function to flush all pending - * writes in the cache associated with a particular DCPLB. - * - * R0 - page's start address - * R1 - CPLB's data field. - */ - -.align 2 -ENTRY(_dcplb_flush) - [--SP] = ( R7:0, P5:0 ); - [--SP] = LC0; - [--SP] = LT0; - [--SP] = LB0; - [--SP] = LC1; - [--SP] = LT1; - [--SP] = LB1; - - /* If it's a 1K or 4K page, then it's quickest to - * just systematically flush all the addresses in - * the page, regardless of whether they're in the - * cache, or dirty. If it's a 1M or 4M page, there - * are too many addresses, and we have to search the - * cache for lines corresponding to the page. - */ - - CC = BITTST(R1, 17); /* 1MB or 4MB */ - IF !CC JUMP .Ldflush_whole_page; - - /* We're only interested in the page's size, so extract - * this from the CPLB (bits 17:16), and scale to give an - * offset into the page_size and page_prefix tables. - */ - - R1 <<= 14; - R1 >>= 30; - R1 <<= 2; - - /* The page could be mapped into Bank A or Bank B, depending - * on (a) whether both banks are configured as cache, and - * (b) on whether address bit A[x] is set. x is determined - * by DCBS in DMEM_CONTROL - */ - - R2 = 0; /* Default to Bank A (Bank B would be 1)*/ - - P0.L = LO(DMEM_CONTROL); - P0.H = HI(DMEM_CONTROL); - - R3 = [P0]; /* If Bank B is not enabled as cache*/ - CC = BITTST(R3, 2); /* then Bank A is our only option.*/ - IF CC JUMP .Lbank_chosen; - - R4 = 1<<14; /* If DCBS==0, use A[14].*/ - R5 = R4 << 7; /* If DCBS==1, use A[23];*/ - CC = BITTST(R3, 4); - IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/ - R5 = R0 & R4; /* Use it to test the Page address*/ - CC = R5; /* and if that bit is set, we use Bank B,*/ - R2 = CC; /* else we use Bank A.*/ - R2 <<= 23; /* The Bank selection's at posn 23.*/ - -.Lbank_chosen: - - /* We can also determine the sub-bank used, because this is - * taken from bits 13:12 of the address. - */ - - R3 = ((12<<8)|2); /* Extraction pattern */ - nop; /*Anamoly 05000209*/ - R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/ - /* Save in extraction pattern for later deposit.*/ - R3.H = R4.L << 0; - - /* So: - * R0 = Page start - * R1 = Page length (actually, offset into size/prefix tables) - * R2 = Bank select mask - * R3 = sub-bank deposit values - * - * The cache has 2 Ways, and 64 sets, so we iterate through - * the sets, accessing the tag for each Way, for our Bank and - * sub-bank, looking for dirty, valid tags that match our - * address prefix. - */ - - P5.L = LO(DTEST_COMMAND); - P5.H = HI(DTEST_COMMAND); - P4.L = LO(DTEST_DATA0); - P4.H = HI(DTEST_DATA0); - - P0.L = page_prefix_table; - P0.H = page_prefix_table; - P1 = R1; - R5 = 0; /* Set counter*/ - P0 = P1 + P0; - R4 = [P0]; /* This is the address prefix*/ - - - /* We're reading (bit 1==0) the tag (bit 2==0), and we - * don't care about which double-word, since we're only - * fetching tags, so we only have to set Set, Bank, - * Sub-bank and Way. - */ - - P2 = 2; - LSETUP (.Lfs1, .Lfe1) LC1 = P2; -.Lfs1: P0 = 64; /* iterate over all sets*/ - LSETUP (.Lfs0, .Lfe0) LC0 = P0; -.Lfs0: R6 = R5 << 5; /* Combine set*/ - R6.H = R3.H << 0 ; /* and sub-bank*/ - R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/ - BITSET(R6,14); - [P5] = R6; /* Issue Command*/ - SSYNC; - R7 = [P4]; /* and read Tag.*/ - CC = BITTST(R7, 0); /* Check if valid*/ - IF !CC JUMP .Lfskip; /* and skip if not.*/ - CC = BITTST(R7, 1); /* Check if dirty*/ - IF !CC JUMP .Lfskip; /* and skip if not.*/ - - /* Compare against the page address. First, plant bits 13:12 - * into the tag, since those aren't part of the returned data. - */ - - R7 = DEPOSIT(R7, R3); /* set 13:12*/ - R1 = R7 & R4; /* Mask off lower bits*/ - CC = R1 == R0; /* Compare against page start.*/ - IF !CC JUMP .Lfskip; /* Skip it if it doesn't match.*/ - - /* Tag address matches against page, so this is an entry - * we must flush. - */ - - R7 >>= 10; /* Mask off the non-address bits*/ - R7 <<= 10; - P3 = R7; - SSYNC; - FLUSHINV [P3]; /* And flush the entry*/ -.Lfskip: -.Lfe0: R5 += 1; /* Advance to next Set*/ -.Lfe1: BITSET(R2, 26); /* Go to next Way.*/ - -.Ldfinished: - SSYNC; /* Ensure the data gets out to mem.*/ - - /*Finished. Restore context.*/ - LB1 = [SP++]; - LT1 = [SP++]; - LC1 = [SP++]; - LB0 = [SP++]; - LT0 = [SP++]; - LC0 = [SP++]; - ( R7:0, P5:0 ) = [SP++]; - RTS; - -.Ldflush_whole_page: - - /* It's a 1K or 4K page, so quicker to just flush the - * entire page. - */ - - P1 = 32; /* For 1K pages*/ - P2 = P1 << 2; /* For 4K pages*/ - P0 = R0; /* Start of page*/ - CC = BITTST(R1, 16); /* Whether 1K or 4K*/ - IF CC P1 = P2; - P1 += -1; /* Unroll one iteration*/ - SSYNC; - FLUSHINV [P0++]; /* because CSYNC can't end loops.*/ - LSETUP (.Leall, .Leall) LC0 = P1; -.Leall: FLUSHINV [P0++]; - SSYNC; - JUMP .Ldfinished; -ENDPROC(_dcplb_flush) - -.align 4; -page_prefix_table: -.byte4 0xFFFFFC00; /* 1K */ -.byte4 0xFFFFF000; /* 4K */ -.byte4 0xFFF00000; /* 1M */ -.byte4 0xFFC00000; /* 4M */ -.page_prefix_table.end: diff --git a/cpu/blackfin/serial.c b/cpu/blackfin/serial.c index 406d9d023..0d6f377c0 100644 --- a/cpu/blackfin/serial.c +++ b/cpu/blackfin/serial.c @@ -35,6 +35,32 @@ #include "serial.h" +#ifdef CONFIG_DEBUG_SERIAL +uint16_t cached_lsr[256]; +uint16_t cached_rbr[256]; +size_t cache_count; + +/* The LSR is read-to-clear on some parts, so we have to make sure status + * bits aren't inadvertently lost when doing various tests. + */ +static uint16_t uart_lsr_save; +static uint16_t uart_lsr_read(void) +{ + uint16_t lsr = *pUART_LSR; + uart_lsr_save |= (lsr & (OE|PE|FE|BI)); + return lsr | uart_lsr_save; +} +/* Just do the clear for everyone since it can't hurt. */ +static void uart_lsr_clear(void) +{ + uart_lsr_save = 0; + *pUART_LSR |= -1; +} +#else +static inline uint16_t uart_lsr_read(void) { return *pUART_LSR; } +static inline void uart_lsr_clear(void) { *pUART_LSR = -1; } +#endif + /* Symbol for our assembly to call. */ void serial_set_baud(uint32_t baud) { @@ -61,6 +87,12 @@ int serial_init(void) { serial_initialize(); serial_setbrg(); + uart_lsr_clear(); +#ifdef CONFIG_DEBUG_SERIAL + cache_count = 0; + memset(cached_lsr, 0x00, sizeof(cached_lsr)); + memset(cached_rbr, 0x00, sizeof(cached_rbr)); +#endif return 0; } @@ -73,7 +105,7 @@ void serial_putc(const char c) WATCHDOG_RESET(); /* wait for the hardware fifo to clear up */ - while (!(*pUART_LSR & THRE)) + while (!(uart_lsr_read() & THRE)) continue; /* queue the character for transmission */ @@ -83,38 +115,54 @@ void serial_putc(const char c) WATCHDOG_RESET(); /* wait for the byte to be shifted over the line */ - while (!(*pUART_LSR & TEMT)) + while (!(uart_lsr_read() & TEMT)) continue; } int serial_tstc(void) { WATCHDOG_RESET(); - return (*pUART_LSR & DR) ? 1 : 0; + return (uart_lsr_read() & DR) ? 1 : 0; } int serial_getc(void) { - uint16_t uart_lsr_val, uart_rbr_val; + uint16_t uart_rbr_val; /* wait for data ! */ while (!serial_tstc()) continue; - /* clear the status and grab the new byte */ - uart_lsr_val = *pUART_LSR; + /* grab the new byte */ uart_rbr_val = *pUART_RBR; +#ifdef CONFIG_DEBUG_SERIAL + /* grab & clear the LSR */ + uint16_t uart_lsr_val = uart_lsr_read(); + + cached_lsr[cache_count] = uart_lsr_val; + cached_rbr[cache_count] = uart_rbr_val; + cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr); + if (uart_lsr_val & (OE|PE|FE|BI)) { - /* Some parts are read-to-clear while others are - * write-to-clear. Just do the write for everyone - * since it cant hurt (other than code size). - */ - *pUART_LSR = (OE|PE|FE|BI); + uint16_t dll, dlh; + printf("\n[SERIAL ERROR]\n"); + ACCESS_LATCH(); + dll = *pUART_DLL; + dlh = *pUART_DLH; + ACCESS_PORT_IER(); + printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh); + do { + --cache_count; + printf("\t%3i: RBR=0x%02x LSR=0x%02x\n", cache_count, + cached_rbr[cache_count], cached_lsr[cache_count]); + } while (cache_count > 0); return -1; } +#endif + uart_lsr_clear(); - return uart_rbr_val & 0xFF; + return uart_rbr_val; } void serial_puts(const char *s) diff --git a/cpu/blackfin/serial.h b/cpu/blackfin/serial.h index 1f0f4b46c..ec40c266a 100644 --- a/cpu/blackfin/serial.h +++ b/cpu/blackfin/serial.h @@ -175,11 +175,11 @@ static inline uint32_t serial_early_get_baud(void) __attribute__((always_inline)) static inline void serial_early_set_baud(uint32_t baud) { - /* Translate from baud into divisor in terms of SCLK. - * The +1 is to make sure we over sample just a little - * rather than under sample the incoming signals. + /* Translate from baud into divisor in terms of SCLK. The + * weird multiplication is to make sure we over sample just + * a little rather than under sample the incoming signals. */ - uint16_t divisor = (get_sclk() / (baud * 16)) + 1; + uint16_t divisor = (get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230; /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH(); diff --git a/cpu/blackfin/start.S b/cpu/blackfin/start.S index 8303292a5..9975a0c62 100644 --- a/cpu/blackfin/start.S +++ b/cpu/blackfin/start.S @@ -1,7 +1,7 @@ /* * U-boot - start.S Startup file for Blackfin u-boot * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005-2008 Analog Devices Inc. * * This file is based on head.S * Copyright (c) 2003 Metrowerks/Motorola @@ -49,8 +49,8 @@ ENTRY(_start) /* Set our initial stack to L1 scratch space */ - sp.l = LO(L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE); - sp.h = HI(L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE); + sp.l = LO(L1_SRAM_SCRATCH_END - 20); + sp.h = HI(L1_SRAM_SCRATCH_END - 20); #ifdef CONFIG_HW_WATCHDOG # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START @@ -75,7 +75,7 @@ ENTRY(_start) serial_early_puts("Init Registers"); - /* Disable nested interrupts and enable CYCLES for udelay() */ + /* Disable self-nested interrupts and enable CYCLES for udelay() */ R0 = CCEN | 0x30; SYSCFG = R0; @@ -180,7 +180,7 @@ ENTRY(_start) /* Now lower ourselves from the highest interrupt level to * the lowest. We do this by masking all interrupts but 15, - * setting the 15 handler to "board_init_f", raising the 15 + * setting the 15 handler to ".Lenable_nested", raising the 15 * interrupt, and then returning from the highest interrupt * level to the dummy "jump" until the interrupt controller * services the pending 15 interrupt. @@ -190,20 +190,23 @@ ENTRY(_start) r1 = r6; p0.l = LO(EVT15); p0.h = HI(EVT15); - p1.l = _cpu_init_f; - p1.h = _cpu_init_f; + p1.l = .Lenable_nested; + p1.h = .Lenable_nested; [p0] = p1; - p2.l = LO(IMASK); - p2.h = HI(IMASK); - p3.l = LO(EVT_IVG15); - p3.h = HI(EVT_IVG15); - [p2] = p3; + r7 = EVT_IVG15 (z); + sti r7; raise 15; p4.l = .LWAIT_HERE; p4.h = .LWAIT_HERE; reti = p4; rti; + /* Enable nested interrupts before continuing with cpu init */ +.Lenable_nested: + cli r7; + [--sp] = reti; + jump.l _cpu_init_f; + .LWAIT_HERE: jump .LWAIT_HERE; ENDPROC(_start) diff --git a/cpu/blackfin/traps.c b/cpu/blackfin/traps.c index 2eb45b59c..d17c0a195 100644 --- a/cpu/blackfin/traps.c +++ b/cpu/blackfin/traps.c @@ -236,19 +236,60 @@ static void decode_address(char *buf, unsigned long address) sprintf(buf, "<0x%p> /* unknown address */", address); } +static char *strhwerrcause(uint16_t hwerrcause) +{ + switch (hwerrcause) { + case 0x02: return "system mmr error"; + case 0x03: return "external memory addressing error"; + case 0x12: return "performance monitor overflow"; + case 0x18: return "raise 5 instruction"; + default: return "undef"; + } +} + +static char *strexcause(uint16_t excause) +{ + switch (excause) { + case 0x00 ... 0xf: return "custom exception"; + case 0x10: return "single step"; + case 0x11: return "trace buffer full"; + case 0x21: return "undef inst"; + case 0x22: return "illegal inst"; + case 0x23: return "dcplb prot violation"; + case 0x24: return "misaligned data"; + case 0x25: return "unrecoverable event"; + case 0x26: return "dcplb miss"; + case 0x27: return "multiple dcplb hit"; + case 0x28: return "emulation watchpoint"; + case 0x2a: return "misaligned inst"; + case 0x2b: return "icplb prot violation"; + case 0x2c: return "icplb miss"; + case 0x2d: return "multiple icplb hit"; + case 0x2e: return "illegal use of supervisor resource"; + default: return "undef"; + } +} + void dump(struct pt_regs *fp) { char buf[150]; size_t i; + uint16_t hwerrcause, excause; if (!ENABLE_DUMP) return; + /* fp->ipend is garbage, so load it ourself */ + fp->ipend = bfin_read_IPEND(); + + hwerrcause = (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P; + excause = (fp->seqstat & EXCAUSE) >> EXCAUSE_P; + printf("SEQUENCER STATUS:\n"); printf(" SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n", fp->seqstat, fp->ipend, fp->syscfg); - printf(" HWERRCAUSE: 0x%lx\n", (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P); - printf(" EXCAUSE : 0x%lx\n", (fp->seqstat & EXCAUSE) >> EXCAUSE_P); + printf(" HWERRCAUSE: 0x%lx: %s\n", hwerrcause, strhwerrcause(hwerrcause)); + printf(" EXCAUSE : 0x%lx: %s\n", excause, strexcause(excause)); for (i = 6; i <= 15; ++i) { if (fp->ipend & (1 << i)) { decode_address(buf, bfin_read32(EVT0 + 4*i)); @@ -263,8 +304,9 @@ void dump(struct pt_regs *fp) printf(" RETX: %s\n", buf); decode_address(buf, fp->rets); printf(" RETS: %s\n", buf); + /* we lie and store RETI in "pc" */ decode_address(buf, fp->pc); - printf(" PC : %s\n", buf); + printf(" RETI: %s\n", buf); if (fp->seqstat & EXCAUSE) { decode_address(buf, bfin_read_DCPLB_FAULT_ADDR()); @@ -344,10 +386,6 @@ void bfin_panic(struct pt_regs *regs) ); dump(regs); dump_bfin_trace_buffer(); - printf( - "\n" - "Please reset the board\n" - "\n" - ); + puts("\n"); bfin_reset_or_hang(); } diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index c40bf6610..24e9b9fa2 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -596,7 +596,8 @@ static int flash_toggle (flash_info_t * info, flash_sect_t sect, retval = flash_read32(addr) != flash_read32(addr); break; case FLASH_CFI_64BIT: - retval = flash_read64(addr) != flash_read64(addr); + retval = ( (flash_read32( addr ) != flash_read32( addr )) || + (flash_read32(addr+4) != flash_read32(addr+4)) ); break; default: retval = 0; diff --git a/drivers/rtc/bfin_rtc.c b/drivers/rtc/bfin_rtc.c index 3f8c7eda6..5de695384 100644 --- a/drivers/rtc/bfin_rtc.c +++ b/drivers/rtc/bfin_rtc.c @@ -26,10 +26,17 @@ #define NUM_SECS_IN_HR HRS_TO_SECS(1) #define NUM_SECS_IN_DAY DAYS_TO_SECS(1) +/* Enable the RTC prescaler enable register */ +static void rtc_init(void) +{ + if (!(bfin_read_RTC_PREN() & 0x1)) + bfin_write_RTC_PREN(0x1); +} + /* Our on-chip RTC has no notion of "reset" */ void rtc_reset(void) { - return; + rtc_init(); } /* Wait for pending writes to complete */ @@ -42,14 +49,6 @@ static void wait_for_complete(void) bfin_write_RTC_ISTAT(WRITE_COMPLETE); } -/* Enable the RTC prescaler enable register */ -int rtc_init(void) -{ - pr_stamp(); - bfin_write_RTC_PREN(0x1); - return 0; -} - /* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers * based on this value. */ @@ -64,6 +63,7 @@ int rtc_set(struct rtc_time *tmp) return -1; } + rtc_init(); wait_for_complete(); /* Calculate number of seconds this incoming time represents */ @@ -100,6 +100,7 @@ int rtc_get(struct rtc_time *tmp) return -1; } + rtc_init(); wait_for_complete(); /* Read the RTC_STAT register */ diff --git a/include/asm-blackfin/blackfin-config-pre.h b/include/asm-blackfin/blackfin-config-pre.h index 541cb76f4..714352b1c 100644 --- a/include/asm-blackfin/blackfin-config-pre.h +++ b/include/asm-blackfin/blackfin-config-pre.h @@ -20,7 +20,7 @@ #define CONFIG_SYS_BFIN_CMD_OTP 0x04 #define CONFIG_SYS_BFIN_CMD_CACHE_DUMP 0x08 -/* Bootmode defines -- your config needs to select this via BFIN_BOOT_MODE. +/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE. * Depending on your cpu, some of these may not be valid, check your HRM. * The actual values here are meaningless as long as they're unique. */ @@ -36,5 +36,6 @@ #define BFIN_BOOT_MEM 10 /* boot ldr out of memory (warmboot) */ #define BFIN_BOOT_16HOST_DMA 11 /* boot ldr from 16-bit host dma */ #define BFIN_BOOT_8HOST_DMA 12 /* boot ldr from 8-bit host dma */ +#define BFIN_BOOT_NAND 13 /* boot ldr from nand flash */ #endif diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index e36af2da3..cc21e93a1 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -73,9 +73,4 @@ #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #endif -#if defined(CONFIG_BF561) -#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4) /* SDRAM +L1 + ASYNC_Memory */ -#else -#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM + L1 + ASYNC_Memory */ -#endif #endif /* _CPLB_H */ diff --git a/include/asm-blackfin/mach-bf527/BF522_cdef.h b/include/asm-blackfin/mach-bf527/BF522_cdef.h index 480168c16..987cc862c 100644 --- a/include/asm-blackfin/mach-bf527/BF522_cdef.h +++ b/include/asm-blackfin/mach-bf527/BF522_cdef.h @@ -337,8 +337,5 @@ #define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ #define bfin_read_TCOUNT() bfin_read32(TCOUNT) #define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) #endif /* __BFIN_CDEF_ADSP_BF522_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF522_def.h b/include/asm-blackfin/mach-bf527/BF522_def.h index ce3f8e541..44143ba89 100644 --- a/include/asm-blackfin/mach-bf527/BF522_def.h +++ b/include/asm-blackfin/mach-bf527/BF522_def.h @@ -119,7 +119,6 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define DSPID 0xFFE05000 #define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ #define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) #define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) diff --git a/include/asm-blackfin/mach-bf527/BF523_cdef.h b/include/asm-blackfin/mach-bf527/BF523_cdef.h index 9d3cb9eab..390f3dc16 100644 --- a/include/asm-blackfin/mach-bf527/BF523_cdef.h +++ b/include/asm-blackfin/mach-bf527/BF523_cdef.h @@ -337,8 +337,5 @@ #define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ #define bfin_read_TCOUNT() bfin_read32(TCOUNT) #define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) #endif /* __BFIN_CDEF_ADSP_BF523_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF523_def.h b/include/asm-blackfin/mach-bf527/BF523_def.h index cb15ec04c..02675a952 100644 --- a/include/asm-blackfin/mach-bf527/BF523_def.h +++ b/include/asm-blackfin/mach-bf527/BF523_def.h @@ -119,7 +119,6 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define DSPID 0xFFE05000 #define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ #define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) #define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) diff --git a/include/asm-blackfin/mach-bf527/BF524_cdef.h b/include/asm-blackfin/mach-bf527/BF524_cdef.h index 4373bd738..9ec89c66a 100644 --- a/include/asm-blackfin/mach-bf527/BF524_cdef.h +++ b/include/asm-blackfin/mach-bf527/BF524_cdef.h @@ -337,9 +337,6 @@ #define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ #define bfin_read_TCOUNT() bfin_read32(TCOUNT) #define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) #define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ #define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) diff --git a/include/asm-blackfin/mach-bf527/BF524_def.h b/include/asm-blackfin/mach-bf527/BF524_def.h index ef2fc0b36..10793e8ed 100644 --- a/include/asm-blackfin/mach-bf527/BF524_def.h +++ b/include/asm-blackfin/mach-bf527/BF524_def.h @@ -119,7 +119,6 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define DSPID 0xFFE05000 #define USB_FADDR 0xFFC03800 /* Function address register */ #define USB_POWER 0xFFC03804 /* Power management register */ #define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ diff --git a/include/asm-blackfin/mach-bf527/BF525_cdef.h b/include/asm-blackfin/mach-bf527/BF525_cdef.h index b406b101c..8fe29db07 100644 --- a/include/asm-blackfin/mach-bf527/BF525_cdef.h +++ b/include/asm-blackfin/mach-bf527/BF525_cdef.h @@ -337,9 +337,6 @@ #define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ #define bfin_read_TCOUNT() bfin_read32(TCOUNT) #define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) #define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ #define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) diff --git a/include/asm-blackfin/mach-bf527/BF525_def.h b/include/asm-blackfin/mach-bf527/BF525_def.h index a149eda26..c4c2f2f09 100644 --- a/include/asm-blackfin/mach-bf527/BF525_def.h +++ b/include/asm-blackfin/mach-bf527/BF525_def.h @@ -119,7 +119,6 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define DSPID 0xFFE05000 #define USB_FADDR 0xFFC03800 /* Function address register */ #define USB_POWER 0xFFC03804 /* Power management register */ #define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ diff --git a/include/asm-blackfin/mach-bf527/BF526_cdef.h b/include/asm-blackfin/mach-bf527/BF526_cdef.h index 765336357..943886210 100644 --- a/include/asm-blackfin/mach-bf527/BF526_cdef.h +++ b/include/asm-blackfin/mach-bf527/BF526_cdef.h @@ -337,9 +337,6 @@ #define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ #define bfin_read_TCOUNT() bfin_read32(TCOUNT) #define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) #define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */ #define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) diff --git a/include/asm-blackfin/mach-bf527/BF526_def.h b/include/asm-blackfin/mach-bf527/BF526_def.h index b432c7a3d..04db6c787 100644 --- a/include/asm-blackfin/mach-bf527/BF526_def.h +++ b/include/asm-blackfin/mach-bf527/BF526_def.h @@ -119,7 +119,6 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define DSPID 0xFFE05000 #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ diff --git a/include/asm-blackfin/mach-bf527/BF527_cdef.h b/include/asm-blackfin/mach-bf527/BF527_cdef.h index 16c834264..fb9b30793 100644 --- a/include/asm-blackfin/mach-bf527/BF527_cdef.h +++ b/include/asm-blackfin/mach-bf527/BF527_cdef.h @@ -337,9 +337,6 @@ #define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ #define bfin_read_TCOUNT() bfin_read32(TCOUNT) #define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) #define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */ #define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) diff --git a/include/asm-blackfin/mach-bf527/BF527_def.h b/include/asm-blackfin/mach-bf527/BF527_def.h index 784d627cc..c1e1aab2c 100644 --- a/include/asm-blackfin/mach-bf527/BF527_def.h +++ b/include/asm-blackfin/mach-bf527/BF527_def.h @@ -119,7 +119,6 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define DSPID 0xFFE05000 #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h index 058d95c89..7c5127eca 100644 --- a/include/asm-blackfin/mach-bf527/anomaly.h +++ b/include/asm-blackfin/mach-bf527/anomaly.h @@ -2,12 +2,12 @@ * File: include/asm-blackfin/mach-bf527/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2007 Analog Devices Inc. + * Copyright (C) 2004-2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ /* This file shoule be up to date with: - * - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List + * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -23,20 +23,66 @@ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) -/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) /* Incorrect Access of OTP_STATUS During otp_write() Function */ #define ANOMALY_05000328 (1) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ #define ANOMALY_05000337 (1) -/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */ +/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ +#define ANOMALY_05000341 (1) +/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ #define ANOMALY_05000342 (1) -/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ +/* USB Calibration Value Is Not Initialized */ +#define ANOMALY_05000346 (1) +/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ #define ANOMALY_05000347 (1) +/* Security Features Are Not Functional */ +#define ANOMALY_05000348 (__SILICON_REVISION__ < 1) +/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ +#define ANOMALY_05000355 (1) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* Incorrect Revision Number in DSPID Register */ +#define ANOMALY_05000364 (__SILICON_REVISION__ > 0) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* New Feature: Higher Default CCLK Rate */ +#define ANOMALY_05000368 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) +/* Authentication Fails To Initiate */ +#define ANOMALY_05000376 (__SILICON_REVISION__ > 0) +/* Data Read From L3 Memory by USB DMA May be Corrupted */ +#define ANOMALY_05000380 (1) +/* USB Full-speed Mode not Fully Tested */ +#define ANOMALY_05000381 (1) +/* New Feature: Boot from OTP Memory */ +#define ANOMALY_05000385 (1) +/* New Feature: bfrom_SysControl() Routine */ +#define ANOMALY_05000386 (1) +/* New Feature: Programmable Preboot Settings */ +#define ANOMALY_05000387 (1) +/* Reset Vector Must Not Be in SDRAM Memory Space */ +#define ANOMALY_05000389 (1) +/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */ +#define ANOMALY_05000392 (1) +/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000393 (1) +/* New Feature: Log Buffer Functionality */ +#define ANOMALY_05000394 (1) +/* New Feature: Hook Routine Functionality */ +#define ANOMALY_05000395 (1) +/* New Feature: Header Indirect Bit */ +#define ANOMALY_05000396 (1) +/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */ +#define ANOMALY_05000397 (1) +/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */ +#define ANOMALY_05000398 (1) +/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */ +#define ANOMALY_05000399 (1) +/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ +#define ANOMALY_05000401 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -49,7 +95,10 @@ #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) +#define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000323 (0) +#define ANOMALY_05000353 (1) +#define ANOMALY_05000363 (0) #endif diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h index 98209d40a..7c34c3813 100644 --- a/include/asm-blackfin/mach-bf533/anomaly.h +++ b/include/asm-blackfin/mach-bf533/anomaly.h @@ -2,12 +2,12 @@ * File: include/asm-blackfin/mach-bf533/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2007 Analog Devices Inc. + * Copyright (C) 2004-2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ /* This file shoule be up to date with: - * - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List + * - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -164,6 +164,8 @@ #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) +/* SCKELOW Bit Does Not Maintain State Through Hibernate */ +#define ANOMALY_05000307 (1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ @@ -176,6 +178,21 @@ #define ANOMALY_05000315 (1) /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ #define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* UART Break Signal Issues */ +#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) +/* PPI Does Not Start Properly In Specific Mode */ +#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) +/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ +#define ANOMALY_05000403 (1) + /* These anomalies have been "phased" out of analog.com anomaly sheets and are * here to show running on older silicon just isn't feasible. @@ -249,15 +266,10 @@ #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) /* Internal Voltage Regulator may not start up */ #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (1) -/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ -#define ANOMALY_05000366 (1) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000266 (0) #define ANOMALY_05000323 (0) +#define ANOMALY_05000353 (1) #endif diff --git a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h index b000ea2eb..b9e4d6770 100644 --- a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h +++ b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h @@ -2721,9 +2721,6 @@ #define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ #define bfin_read_TCOUNT() bfin_read32(TCOUNT) #define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) #define pCHIPID ((uint32_t volatile *)CHIPID) #define bfin_read_CHIPID() bfin_read32(CHIPID) #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) diff --git a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_def.h b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_def.h index 077412a69..61ffa148e 100644 --- a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_def.h +++ b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_def.h @@ -911,7 +911,6 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define DSPID 0xFFE05000 #define CHIPID 0xFFC00014 #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index d604457f9..8d7f30579 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h @@ -2,12 +2,12 @@ * File: include/asm-blackfin/mach-bf537/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2007 Analog Devices Inc. + * Copyright (C) 2004-2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ /* This file shoule be up to date with: - * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List + * - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -132,12 +132,22 @@ #define ANOMALY_05000322 (1) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) +/* New Feature: UART Remains Enabled after UART Boot */ +#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) +/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ +#define ANOMALY_05000355 (1) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ #define ANOMALY_05000357 (1) /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ #define ANOMALY_05000359 (1) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) +/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ +#define ANOMALY_05000403 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -148,5 +158,7 @@ #define ANOMALY_05000266 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000323 (0) +#define ANOMALY_05000353 (1) +#define ANOMALY_05000363 (0) #endif diff --git a/include/asm-blackfin/mach-bf548/BF541_cdef.h b/include/asm-blackfin/mach-bf548/BF541_cdef.h index c0d2a4223..1b8c79b59 100644 --- a/include/asm-blackfin/mach-bf548/BF541_cdef.h +++ b/include/asm-blackfin/mach-bf548/BF541_cdef.h @@ -310,9 +310,6 @@ #define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ #define bfin_read_IPRIO() bfin_read32(IPRIO) #define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) #define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ #define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) #define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) diff --git a/include/asm-blackfin/mach-bf548/BF541_def.h b/include/asm-blackfin/mach-bf548/BF541_def.h index 2f9cec696..1469ac2db 100644 --- a/include/asm-blackfin/mach-bf548/BF541_def.h +++ b/include/asm-blackfin/mach-bf548/BF541_def.h @@ -110,7 +110,6 @@ #define IMASK 0xFFE02104 /* Interrupt Mask Register */ #define IPEND 0xFFE02108 /* Interrupt Pending Register */ #define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define DSPID 0xFFE05000 #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ diff --git a/include/asm-blackfin/mach-bf548/BF542_cdef.h b/include/asm-blackfin/mach-bf548/BF542_cdef.h index be48dfd52..306b5f117 100644 --- a/include/asm-blackfin/mach-bf548/BF542_cdef.h +++ b/include/asm-blackfin/mach-bf548/BF542_cdef.h @@ -310,9 +310,6 @@ #define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ #define bfin_read_IPRIO() bfin_read32(IPRIO) #define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) #define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ #define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) #define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) diff --git a/include/asm-blackfin/mach-bf548/BF542_def.h b/include/asm-blackfin/mach-bf548/BF542_def.h index c2be4de10..40fe555c8 100644 --- a/include/asm-blackfin/mach-bf548/BF542_def.h +++ b/include/asm-blackfin/mach-bf548/BF542_def.h @@ -110,7 +110,6 @@ #define IMASK 0xFFE02104 /* Interrupt Mask Register */ #define IPEND 0xFFE02108 /* Interrupt Pending Register */ #define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define DSPID 0xFFE05000 #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ diff --git a/include/asm-blackfin/mach-bf548/BF544_cdef.h b/include/asm-blackfin/mach-bf548/BF544_cdef.h index b3232fcf3..47ef6e17b 100644 --- a/include/asm-blackfin/mach-bf548/BF544_cdef.h +++ b/include/asm-blackfin/mach-bf548/BF544_cdef.h @@ -310,9 +310,6 @@ #define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ #define bfin_read_IPRIO() bfin_read32(IPRIO) #define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) #define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ #define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) #define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) diff --git a/include/asm-blackfin/mach-bf548/BF544_def.h b/include/asm-blackfin/mach-bf548/BF544_def.h index 834b7a653..042e2ac82 100644 --- a/include/asm-blackfin/mach-bf548/BF544_def.h +++ b/include/asm-blackfin/mach-bf548/BF544_def.h @@ -110,7 +110,6 @@ #define IMASK 0xFFE02104 /* Interrupt Mask Register */ #define IPEND 0xFFE02108 /* Interrupt Pending Register */ #define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define DSPID 0xFFE05000 #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ diff --git a/include/asm-blackfin/mach-bf548/BF547_cdef.h b/include/asm-blackfin/mach-bf548/BF547_cdef.h index e1a1daffb..42d041a74 100644 --- a/include/asm-blackfin/mach-bf548/BF547_cdef.h +++ b/include/asm-blackfin/mach-bf548/BF547_cdef.h @@ -310,9 +310,6 @@ #define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ #define bfin_read_IPRIO() bfin_read32(IPRIO) #define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) #define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ #define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) #define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) diff --git a/include/asm-blackfin/mach-bf548/BF547_def.h b/include/asm-blackfin/mach-bf548/BF547_def.h index bb7ae5ecc..1cb338154 100644 --- a/include/asm-blackfin/mach-bf548/BF547_def.h +++ b/include/asm-blackfin/mach-bf548/BF547_def.h @@ -110,7 +110,6 @@ #define IMASK 0xFFE02104 /* Interrupt Mask Register */ #define IPEND 0xFFE02108 /* Interrupt Pending Register */ #define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define DSPID 0xFFE05000 #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ diff --git a/include/asm-blackfin/mach-bf548/BF548_cdef.h b/include/asm-blackfin/mach-bf548/BF548_cdef.h index 6cdfbf3d5..cf02834e9 100644 --- a/include/asm-blackfin/mach-bf548/BF548_cdef.h +++ b/include/asm-blackfin/mach-bf548/BF548_cdef.h @@ -310,9 +310,6 @@ #define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ #define bfin_read_IPRIO() bfin_read32(IPRIO) #define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) #define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ #define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) #define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) diff --git a/include/asm-blackfin/mach-bf548/BF548_def.h b/include/asm-blackfin/mach-bf548/BF548_def.h index e72510209..950ce4325 100644 --- a/include/asm-blackfin/mach-bf548/BF548_def.h +++ b/include/asm-blackfin/mach-bf548/BF548_def.h @@ -110,7 +110,6 @@ #define IMASK 0xFFE02104 /* Interrupt Mask Register */ #define IPEND 0xFFE02108 /* Interrupt Pending Register */ #define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define DSPID 0xFFE05000 #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ diff --git a/include/asm-blackfin/mach-bf548/BF549_cdef.h b/include/asm-blackfin/mach-bf548/BF549_cdef.h index 9ac8c2dd4..3514ceff4 100644 --- a/include/asm-blackfin/mach-bf548/BF549_cdef.h +++ b/include/asm-blackfin/mach-bf548/BF549_cdef.h @@ -310,9 +310,6 @@ #define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ #define bfin_read_IPRIO() bfin_read32(IPRIO) #define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) #define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ #define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) #define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) diff --git a/include/asm-blackfin/mach-bf548/BF549_def.h b/include/asm-blackfin/mach-bf548/BF549_def.h index f36ecd6ce..55b0a296c 100644 --- a/include/asm-blackfin/mach-bf548/BF549_def.h +++ b/include/asm-blackfin/mach-bf548/BF549_def.h @@ -110,7 +110,6 @@ #define IMASK 0xFFE02104 /* Interrupt Mask Register */ #define IPEND 0xFFE02108 /* Interrupt Pending Register */ #define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define DSPID 0xFFE05000 #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index 0451ea7b8..1dc75ef1a 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -2,18 +2,18 @@ * File: include/asm-blackfin/mach-bf548/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2007 Analog Devices Inc. + * Copyright (C) 2004-2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ /* This file shoule be up to date with: - * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List + * - Revision F, 06/11/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) @@ -43,7 +43,7 @@ #define ANOMALY_05000328 (__SILICON_REVISION__ < 1) /* Synchronous Burst Flash Boot Mode Is Not Functional */ #define ANOMALY_05000329 (__SILICON_REVISION__ < 1) -/* Host DMA Boot Mode Is Not Functional */ +/* Host DMA Boot Modes Are Not Functional */ #define ANOMALY_05000330 (__SILICON_REVISION__ < 1) /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ #define ANOMALY_05000334 (__SILICON_REVISION__ < 1) @@ -61,26 +61,90 @@ #define ANOMALY_05000344 (__SILICON_REVISION__ < 1) /* USB Calibration Value Is Not Intialized */ #define ANOMALY_05000346 (__SILICON_REVISION__ < 1) -/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ +/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ #define ANOMALY_05000347 (__SILICON_REVISION__ < 1) /* Data Lost when Core Reads SDH Data FIFO */ #define ANOMALY_05000349 (__SILICON_REVISION__ < 1) /* PLL Status Register Is Inaccurate */ #define ANOMALY_05000351 (__SILICON_REVISION__ < 1) +/* bfrom_SysControl() Firmware Function Performs Improper System Reset */ +#define ANOMALY_05000353 (1) +/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ +#define ANOMALY_05000355 (__SILICON_REVISION__ < 1) +/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ +#define ANOMALY_05000356 (__SILICON_REVISION__ < 1) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ #define ANOMALY_05000357 (1) /* External Memory Read Access Hangs Core With PLL Bypass */ #define ANOMALY_05000360 (1) /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ #define ANOMALY_05000365 (1) +/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */ +#define ANOMALY_05000367 (__SILICON_REVISION__ < 1) /* Addressing Conflict between Boot ROM and Asynchronous Memory */ #define ANOMALY_05000369 (1) +/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ +#define ANOMALY_05000370 (__SILICON_REVISION__ < 1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (__SILICON_REVISION__ < 1) +#define ANOMALY_05000371 (1) +/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ +#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) /* Mobile DDR Operation Not Functional */ #define ANOMALY_05000377 (1) /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ #define ANOMALY_05000378 (1) +/* 16-Bit NAND FLASH Boot Mode Is Not Functional */ +#define ANOMALY_05000379 (1) +/* 8-Bit NAND Flash Boot Mode Not Functional */ +#define ANOMALY_05000382 (__SILICON_REVISION__ < 1) +/* Some ATAPI Modes Are Not Functional */ +#define ANOMALY_05000383 (1) +/* Boot from OTP Memory Not Functional */ +#define ANOMALY_05000385 (__SILICON_REVISION__ < 1) +/* bfrom_SysControl() Firmware Routine Not Functional */ +#define ANOMALY_05000386 (__SILICON_REVISION__ < 1) +/* Programmable Preboot Settings Not Functional */ +#define ANOMALY_05000387 (__SILICON_REVISION__ < 1) +/* CRC32 Checksum Support Not Functional */ +#define ANOMALY_05000388 (__SILICON_REVISION__ < 1) +/* Reset Vector Must Not Be in SDRAM Memory Space */ +#define ANOMALY_05000389 (__SILICON_REVISION__ < 1) +/* Changed Meaning of BCODE Field in SYSCR Register */ +#define ANOMALY_05000390 (__SILICON_REVISION__ < 1) +/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */ +#define ANOMALY_05000391 (__SILICON_REVISION__ < 1) +/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000392 (__SILICON_REVISION__ < 1) +/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000393 (__SILICON_REVISION__ < 1) +/* Log Buffer Not Functional */ +#define ANOMALY_05000394 (__SILICON_REVISION__ < 1) +/* Hook Routine Not Functional */ +#define ANOMALY_05000395 (__SILICON_REVISION__ < 1) +/* Header Indirect Bit Not Functional */ +#define ANOMALY_05000396 (__SILICON_REVISION__ < 1) +/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ +#define ANOMALY_05000397 (__SILICON_REVISION__ < 1) +/* Lockbox SESR Disallows Certain User Interrupts */ +#define ANOMALY_05000404 (1) +/* Lockbox SESR Firmware Does Not Save/Restore Full Context */ +#define ANOMALY_05000405 (1) +/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */ +#define ANOMALY_05000406 (1) +/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ +#define ANOMALY_05000407 (1) +/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ +#define ANOMALY_05000408 (1) +/* Lockbox firmware leaves MDMA0 channel enabled */ +#define ANOMALY_05000409 (1) +/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ +#define ANOMALY_05000411 (1) +/* FIFO Boot Mode Is Not Functional */ +#define ANOMALY_05000412 (1) +/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */ +#define ANOMALY_05000413 (1) +/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ +#define ANOMALY_05000414 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -93,7 +157,9 @@ #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) +#define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000323 (0) +#define ANOMALY_05000363 (0) #endif diff --git a/include/asm-blackfin/mach-bf548/ports.h b/include/asm-blackfin/mach-bf548/ports.h index c9bd28718..c8285163f 100644 --- a/include/asm-blackfin/mach-bf548/ports.h +++ b/include/asm-blackfin/mach-bf548/ports.h @@ -59,38 +59,38 @@ #define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) #define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) #define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) -#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 14) -#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) -#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) -#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) -#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 14) -#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) -#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) -#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) -#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 14) -#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) -#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) -#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) -#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 14) -#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) -#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) -#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) -#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 14) -#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) -#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) -#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) -#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 14) -#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) -#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) -#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) -#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 14) -#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) -#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) -#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) -#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 14) -#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) -#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) -#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) +#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 16) +#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 16) +#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 16) +#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 16) +#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 18) +#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 18) +#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 18) +#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 18) +#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 20) +#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 20) +#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 20) +#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 20) +#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 22) +#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 22) +#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 22) +#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 22) +#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 24) +#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 24) +#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 24) +#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 24) +#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 26) +#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 26) +#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 26) +#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 26) +#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 28) +#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 28) +#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 28) +#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 28) +#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 30) +#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 30) +#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30) +#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30) /* Port A Masks */ #define PA0 0x0001 diff --git a/include/asm-blackfin/mach-bf561/BF561_cdef.h b/include/asm-blackfin/mach-bf561/BF561_cdef.h index 395cd28e9..d8883f317 100644 --- a/include/asm-blackfin/mach-bf561/BF561_cdef.h +++ b/include/asm-blackfin/mach-bf561/BF561_cdef.h @@ -241,9 +241,9 @@ #define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) #define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) #define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pSICA_SWRST ((uint32_t volatile *)SICA_SWRST) -#define bfin_read_SICA_SWRST() bfin_read32(SICA_SWRST) -#define bfin_write_SICA_SWRST(val) bfin_write32(SICA_SWRST, val) +#define pSICA_SWRST ((uint16_t volatile *)SICA_SWRST) +#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) +#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST, val) #define pSICA_SYSCR ((uint32_t volatile *)SICA_SYSCR) #define bfin_read_SICA_SYSCR() bfin_read32(SICA_SYSCR) #define bfin_write_SICA_SYSCR(val) bfin_write32(SICA_SYSCR, val) @@ -292,9 +292,9 @@ #define pSICA_IAR7 ((uint32_t volatile *)SICA_IAR7) #define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) #define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7, val) -#define pSICB_SWRST ((uint32_t volatile *)SICB_SWRST) -#define bfin_read_SICB_SWRST() bfin_read32(SICB_SWRST) -#define bfin_write_SICB_SWRST(val) bfin_write32(SICB_SWRST, val) +#define pSICB_SWRST ((uint16_t volatile *)SICB_SWRST) +#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) +#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST, val) #define pSICB_SYSCR ((uint32_t volatile *)SICB_SYSCR) #define bfin_read_SICB_SYSCR() bfin_read32(SICB_SYSCR) #define bfin_write_SICB_SYSCR(val) bfin_write32(SICB_SYSCR, val) @@ -400,12 +400,6 @@ #define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE) #define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE) #define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) -#define pDBGSTAT ((uint32_t volatile *)DBGSTAT) -#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT) -#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val) #define pUART_THR ((uint16_t volatile *)UART_THR) #define bfin_read_UART_THR() bfin_read16(UART_THR) #define bfin_write_UART_THR(val) bfin_write16(UART_THR, val) diff --git a/include/asm-blackfin/mach-bf561/BF561_def.h b/include/asm-blackfin/mach-bf561/BF561_def.h index 22b5bac3e..853496232 100644 --- a/include/asm-blackfin/mach-bf561/BF561_def.h +++ b/include/asm-blackfin/mach-bf561/BF561_def.h @@ -140,8 +140,6 @@ #define SRAM_BASE_ADDR_CORE_A 0xFFE00000 #define SRAM_BASE_ADDR_CORE_B 0xFFE00000 #define EVT_OVERRIDE 0xFFE02100 -#define DSPID 0xFFE05000 -#define DBGSTAT 0xFFE05008 #define UART_THR 0xFFC00400 #define UART_RBR 0xFFC00400 #define UART_DLL 0xFFC00400 diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h index 0c1d46193..e9c4ca878 100644 --- a/include/asm-blackfin/mach-bf561/anomaly.h +++ b/include/asm-blackfin/mach-bf561/anomaly.h @@ -2,12 +2,12 @@ * File: include/asm-blackfin/mach-bf561/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2007 Analog Devices Inc. + * Copyright (C) 2004-2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ /* This file shoule be up to date with: - * - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List + * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -256,15 +256,20 @@ #define ANOMALY_05000357 (1) /* Conflicting Column Address Widths Causes SDRAM Errors */ #define ANOMALY_05000362 (1) +/* UART Break Signal Issues */ +#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ #define ANOMALY_05000366 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) +/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ +#define ANOMALY_05000403 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000158 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) +#define ANOMALY_05000353 (1) #endif diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-core_cdef.h b/include/asm-blackfin/mach-common/ADSP-EDN-core_cdef.h index 4ac71f632..af17813db 100644 --- a/include/asm-blackfin/mach-common/ADSP-EDN-core_cdef.h +++ b/include/asm-blackfin/mach-common/ADSP-EDN-core_cdef.h @@ -63,5 +63,11 @@ #define pWPSTAT ((uint32_t volatile *)WPSTAT) #define bfin_read_WPSTAT() bfin_read32(WPSTAT) #define bfin_write_WPSTAT(val) bfin_write32(WPSTAT, val) +#define pDSPID ((uint32_t volatile *)DSPID) +#define bfin_read_DSPID() bfin_read32(DSPID) +#define bfin_write_DSPID(val) bfin_write32(DSPID, val) +#define pDBGSTAT ((uint32_t volatile *)DBGSTAT) +#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT) +#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val) #endif /* __BFIN_CDEF_ADSP_EDN_core__ */ diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-core_def.h b/include/asm-blackfin/mach-common/ADSP-EDN-core_def.h index 721af1256..74f5d309c 100644 --- a/include/asm-blackfin/mach-common/ADSP-EDN-core_def.h +++ b/include/asm-blackfin/mach-common/ADSP-EDN-core_def.h @@ -25,5 +25,7 @@ #define WPDACNT0 0xFFE07180 #define WPDACNT1 0xFFE07184 #define WPSTAT 0xFFE07200 +#define DSPID 0xFFE05000 +#define DBGSTAT 0xFFE05008 #endif /* __BFIN_DEF_ADSP_EDN_core__ */ diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h index 2f5a2658f..4c439e528 100644 --- a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h +++ b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h @@ -897,18 +897,15 @@ #define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count register (16-bit) */ #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pSWRST ((uint32_t volatile *)SWRST) /* Software Reset Register (16-bit) */ -#define bfin_read_SWRST() bfin_read32(SWRST) -#define bfin_write_SWRST(val) bfin_write32(SWRST, val) +#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */ +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST, val) #define pSYSCR ((uint32_t volatile *)SYSCR) /* System Configuration register */ #define bfin_read_SYSCR() bfin_read32(SYSCR) #define bfin_write_SYSCR(val) bfin_write32(SYSCR, val) #define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE) #define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE) #define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) #define pCHIPID ((uint32_t volatile *)CHIPID) #define bfin_read_CHIPID() bfin_read32(CHIPID) #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-extended_def.h b/include/asm-blackfin/mach-common/ADSP-EDN-extended_def.h index 91902709f..24b56b387 100644 --- a/include/asm-blackfin/mach-common/ADSP-EDN-extended_def.h +++ b/include/asm-blackfin/mach-common/ADSP-EDN-extended_def.h @@ -306,7 +306,6 @@ #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ #define SYSCR 0xFFC00104 /* System Configuration register */ #define EVT_OVERRIDE 0xFFE02100 -#define DSPID 0xFFE05000 #define CHIPID 0xFFC00014 #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h deleted file mode 100644 index cb448ad61..000000000 --- a/include/asm-blackfin/mem_init.h +++ /dev/null @@ -1,321 +0,0 @@ -/* - * U-boot - mem_init.h Header file for memory initialization - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \ - CONFIG_MEM_MT48LC64M4A2FB_7E || \ - CONFIG_MEM_MT48LC16M8A2TG_75 || \ - CONFIG_MEM_MT48LC8M16A2TG_7E || \ - CONFIG_MEM_MT48LC8M32B2B5_7 || \ - CONFIG_MEM_MT48LC32M8A2_75) - - #if ( CONFIG_SCLK_HZ > 119402985 ) - #define SDRAM_tRP TRP_2 - #define SDRAM_tRP_num 2 - #define SDRAM_tRAS TRAS_7 - #define SDRAM_tRAS_num 7 - #define SDRAM_tRCD TRCD_2 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 ) - #define SDRAM_tRP TRP_2 - #define SDRAM_tRP_num 2 - #define SDRAM_tRAS TRAS_6 - #define SDRAM_tRAS_num 6 - #define SDRAM_tRCD TRCD_2 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ > 89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 ) - #define SDRAM_tRP TRP_2 - #define SDRAM_tRP_num 2 - #define SDRAM_tRAS TRAS_5 - #define SDRAM_tRAS_num 5 - #define SDRAM_tRCD TRCD_2 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ > 74626866 ) && ( CONFIG_SCLK_HZ <= 89552239 ) - #define SDRAM_tRP TRP_2 - #define SDRAM_tRP_num 2 - #define SDRAM_tRAS TRAS_4 - #define SDRAM_tRAS_num 4 - #define SDRAM_tRCD TRCD_2 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ > 66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 ) - #define SDRAM_tRP TRP_2 - #define SDRAM_tRP_num 2 - #define SDRAM_tRAS TRAS_3 - #define SDRAM_tRAS_num 3 - #define SDRAM_tRCD TRCD_2 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 ) - #define SDRAM_tRP TRP_1 - #define SDRAM_tRP_num 1 - #define SDRAM_tRAS TRAS_3 - #define SDRAM_tRAS_num 3 - #define SDRAM_tRCD TRCD_1 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ > 44776119 ) && ( CONFIG_SCLK_HZ <= 59701493 ) - #define SDRAM_tRP TRP_1 - #define SDRAM_tRP_num 1 - #define SDRAM_tRAS TRAS_3 - #define SDRAM_tRAS_num 3 - #define SDRAM_tRCD TRCD_1 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ > 29850746 ) && ( CONFIG_SCLK_HZ <= 44776119 ) - #define SDRAM_tRP TRP_1 - #define SDRAM_tRP_num 1 - #define SDRAM_tRAS TRAS_2 - #define SDRAM_tRAS_num 2 - #define SDRAM_tRCD TRCD_1 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ <= 29850746 ) - #define SDRAM_tRP TRP_1 - #define SDRAM_tRP_num 1 - #define SDRAM_tRAS TRAS_1 - #define SDRAM_tRAS_num 1 - #define SDRAM_tRCD TRCD_1 - #define SDRAM_tWR TWR_2 - #endif -#endif - -#if (CONFIG_MEM_MT48LC16M16A2TG_75) - /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ - #define SDRAM_CL CL_3 -#endif - -#if (CONFIG_MEM_MT48LC64M4A2FB_7E) - /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ - #define SDRAM_CL CL_2 -#endif - -#if (CONFIG_MEM_MT48LC16M8A2TG_75) - /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ - #define SDRAM_CL CL_3 -#endif - -#if (CONFIG_MEM_MT48LC32M8A2_75) -/*SDRAM INFORMATION: */ -#define SDRAM_Tref 64 /* Refresh period in milliseconds */ -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ -#define SDRAM_CL CL_3 -#endif - -#if (CONFIG_MEM_MT48LC8M16A2TG_7E) - /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ - #define SDRAM_CL CL_2 -#endif - -#if (CONFIG_MEM_MT48LC8M32B2B5_7) - /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ - #define SDRAM_CL CL_3 -#endif - -#if ( CONFIG_MEM_SIZE == 128 ) - #define SDRAM_SIZE EBSZ_128 -#endif -#if ( CONFIG_MEM_SIZE == 64 ) - #define SDRAM_SIZE EBSZ_64 -#endif -#if ( CONFIG_MEM_SIZE == 32 ) - #define SDRAM_SIZE EBSZ_32 -#endif -#if ( CONFIG_MEM_SIZE == 16 ) - #define SDRAM_SIZE EBSZ_16 -#endif -#if ( CONFIG_MEM_ADD_WDTH == 11 ) - #define SDRAM_WIDTH EBCAW_11 -#endif -#if ( CONFIG_MEM_ADD_WDTH == 10 ) - #define SDRAM_WIDTH EBCAW_10 -#endif -#if ( CONFIG_MEM_ADD_WDTH == 9 ) - #define SDRAM_WIDTH EBCAW_9 -#endif -#if ( CONFIG_MEM_ADD_WDTH == 8 ) - #define SDRAM_WIDTH EBCAW_8 -#endif - -#define mem_SDBCTL SDRAM_WIDTH | SDRAM_SIZE | EBE - -/* Equation from section 17 (p17-46) of BF533 HRM */ -#define mem_SDRRC ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) - -/* Enable SCLK Out */ -#define mem_SDGCTL ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS ) - -#define flash_EBIU_AMBCTL_WAT ( ( CONFIG_FLASH_SPEED_BWAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 -#define flash_EBIU_AMBCTL_RAT ( ( CONFIG_FLASH_SPEED_BRAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 -#define flash_EBIU_AMBCTL_HT ( ( CONFIG_FLASH_SPEED_BHT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) -#define flash_EBIU_AMBCTL_ST ( ( CONFIG_FLASH_SPEED_BST * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 -#define flash_EBIU_AMBCTL_TT ( ( CONFIG_FLASH_SPEED_BTT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 - -#if (flash_EBIU_AMBCTL_TT > 3 ) - #define flash_EBIU_AMBCTL0_TT B0TT_4 -#endif -#if (flash_EBIU_AMBCTL_TT == 3 ) - #define flash_EBIU_AMBCTL0_TT B0TT_3 -#endif -#if (flash_EBIU_AMBCTL_TT == 2 ) - #define flash_EBIU_AMBCTL0_TT B0TT_2 -#endif -#if (flash_EBIU_AMBCTL_TT < 2 ) - #define flash_EBIU_AMBCTL0_TT B0TT_1 -#endif - -#if (flash_EBIU_AMBCTL_ST > 3 ) - #define flash_EBIU_AMBCTL0_ST B0ST_4 -#endif -#if (flash_EBIU_AMBCTL_ST == 3 ) - #define flash_EBIU_AMBCTL0_ST B0ST_3 -#endif -#if (flash_EBIU_AMBCTL_ST == 2 ) - #define flash_EBIU_AMBCTL0_ST B0ST_2 -#endif -#if (flash_EBIU_AMBCTL_ST < 2 ) - #define flash_EBIU_AMBCTL0_ST B0ST_1 -#endif - -#if (flash_EBIU_AMBCTL_HT > 2 ) - #define flash_EBIU_AMBCTL0_HT B0HT_3 -#endif -#if (flash_EBIU_AMBCTL_HT == 2 ) - #define flash_EBIU_AMBCTL0_HT B0HT_2 -#endif -#if (flash_EBIU_AMBCTL_HT == 1 ) - #define flash_EBIU_AMBCTL0_HT B0HT_1 -#endif -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) - #define flash_EBIU_AMBCTL0_HT B0HT_0 -#endif -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) - #define flash_EBIU_AMBCTL0_HT B0HT_1 -#endif - -#if (flash_EBIU_AMBCTL_WAT > 14) - #define flash_EBIU_AMBCTL0_WAT B0WAT_15 -#endif -#if (flash_EBIU_AMBCTL_WAT == 14) - #define flash_EBIU_AMBCTL0_WAT B0WAT_14 -#endif -#if (flash_EBIU_AMBCTL_WAT == 13) - #define flash_EBIU_AMBCTL0_WAT B0WAT_13 -#endif -#if (flash_EBIU_AMBCTL_WAT == 12) - #define flash_EBIU_AMBCTL0_WAT B0WAT_12 -#endif -#if (flash_EBIU_AMBCTL_WAT == 11) - #define flash_EBIU_AMBCTL0_WAT B0WAT_11 -#endif -#if (flash_EBIU_AMBCTL_WAT == 10) - #define flash_EBIU_AMBCTL0_WAT B0WAT_10 -#endif -#if (flash_EBIU_AMBCTL_WAT == 9) - #define flash_EBIU_AMBCTL0_WAT B0WAT_9 -#endif -#if (flash_EBIU_AMBCTL_WAT == 8) - #define flash_EBIU_AMBCTL0_WAT B0WAT_8 -#endif -#if (flash_EBIU_AMBCTL_WAT == 7) - #define flash_EBIU_AMBCTL0_WAT B0WAT_7 -#endif -#if (flash_EBIU_AMBCTL_WAT == 6) - #define flash_EBIU_AMBCTL0_WAT B0WAT_6 -#endif -#if (flash_EBIU_AMBCTL_WAT == 5) - #define flash_EBIU_AMBCTL0_WAT B0WAT_5 -#endif -#if (flash_EBIU_AMBCTL_WAT == 4) - #define flash_EBIU_AMBCTL0_WAT B0WAT_4 -#endif -#if (flash_EBIU_AMBCTL_WAT == 3) - #define flash_EBIU_AMBCTL0_WAT B0WAT_3 -#endif -#if (flash_EBIU_AMBCTL_WAT == 2) - #define flash_EBIU_AMBCTL0_WAT B0WAT_2 -#endif -#if (flash_EBIU_AMBCTL_WAT == 1) - #define flash_EBIU_AMBCTL0_WAT B0WAT_1 -#endif - -#if (flash_EBIU_AMBCTL_RAT > 14) - #define flash_EBIU_AMBCTL0_RAT B0RAT_15 -#endif -#if (flash_EBIU_AMBCTL_RAT == 14) - #define flash_EBIU_AMBCTL0_RAT B0RAT_14 -#endif -#if (flash_EBIU_AMBCTL_RAT == 13) - #define flash_EBIU_AMBCTL0_RAT B0RAT_13 -#endif -#if (flash_EBIU_AMBCTL_RAT == 12) - #define flash_EBIU_AMBCTL0_RAT B0RAT_12 -#endif -#if (flash_EBIU_AMBCTL_RAT == 11) - #define flash_EBIU_AMBCTL0_RAT B0RAT_11 -#endif -#if (flash_EBIU_AMBCTL_RAT == 10) - #define flash_EBIU_AMBCTL0_RAT B0RAT_10 -#endif -#if (flash_EBIU_AMBCTL_RAT == 9) - #define flash_EBIU_AMBCTL0_RAT B0RAT_9 -#endif -#if (flash_EBIU_AMBCTL_RAT == 8) - #define flash_EBIU_AMBCTL0_RAT B0RAT_8 -#endif -#if (flash_EBIU_AMBCTL_RAT == 7) - #define flash_EBIU_AMBCTL0_RAT B0RAT_7 -#endif -#if (flash_EBIU_AMBCTL_RAT == 6) - #define flash_EBIU_AMBCTL0_RAT B0RAT_6 -#endif -#if (flash_EBIU_AMBCTL_RAT == 5) - #define flash_EBIU_AMBCTL0_RAT B0RAT_5 -#endif -#if (flash_EBIU_AMBCTL_RAT == 4) - #define flash_EBIU_AMBCTL0_RAT B0RAT_4 -#endif -#if (flash_EBIU_AMBCTL_RAT == 3) - #define flash_EBIU_AMBCTL0_RAT B0RAT_3 -#endif -#if (flash_EBIU_AMBCTL_RAT == 2) - #define flash_EBIU_AMBCTL0_RAT B0RAT_2 -#endif -#if (flash_EBIU_AMBCTL_RAT == 1) - #define flash_EBIU_AMBCTL0_RAT B0RAT_1 -#endif - -#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 85342a60c..7071ccbfe 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. * Based on the sequoia configuration file. * @@ -46,6 +46,7 @@ #endif #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_F 1 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ #define CONFIG_BOARD_TYPES 1 /* support board types */ /*----------------------------------------------------------------------- @@ -79,6 +80,7 @@ #define CONFIG_SYS_USB_HOST 0xe0000400 #define CONFIG_SYS_FPGA_BASE0 0xef000000 /* 32 bit */ #define CONFIG_SYS_FPGA_BASE1 0xef100000 /* 16 bit */ +#define CONFIG_SYS_RESET_BASE 0xef200000 /*----------------------------------------------------------------------- * Initial RAM & stack pointer @@ -139,7 +141,7 @@ #ifdef CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) @@ -217,13 +219,15 @@ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #endif +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_I2C_CMD_TREE 1 @@ -260,38 +264,50 @@ #define CONFIG_DTT_ADM1021 #define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} } -#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_PREBOOT "echo Add \\\"run fpga\\\" and " \ + "\\\"painit\\\" to preboot command" #undef CONFIG_BOOTARGS /* Setup some board specific values for the default environment variables */ #define CONFIG_HOSTNAME pmc440 -#define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0" -#define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk_410/ppc_4xx\0" +#define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0" +#define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_SYS_BOOTFILE \ - CONFIG_SYS_ROOTPATH \ + CONFIG_SYS_BOOTFILE \ + CONFIG_SYS_ROOTPATH \ + "fdt_file=/tftpboot/pmc440/pmc440.dtb\0" \ "netdev=eth0\0" \ "ethrotate=no\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "kernel_addr=FC000000\0" \ - "ramdisk_addr=FC180000\0" \ + "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \ + "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \ + "nand_boot=run nandargs addip addtty addmisc;bootm ${kernel_addr}\0" \ + "nand_boot_fdt=run nandargs addip addtty addmisc;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "run nfsargs addip addtty addmisc;" \ + "bootm\0" \ + "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdt_file};" \ + "run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "kernel_addr=ffc00000\0" \ + "kernel_addr_r=200000\0" \ + "fpga_addr=fff00000\0" \ + "fdt_addr=fff80000\0" \ + "fdt_addr_r=800000\0" \ + "fpga=fpga loadb 0 ${fpga_addr}\0" \ "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \ - "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ - "cp.b 200000 FFFA0000 60000\0" \ + "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ + "cp.b 200000 fffa0000 60000\0" \ "" #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ @@ -366,14 +382,8 @@ CONFIG_SYS_POST_SPR) #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -/* esd expects pram at end of physical memory. - * So no logbuffer at the moment. - */ -#if 0 #define CONFIG_LOGBUFFER -#endif -#define CONFIG_SYS_POST_CACHE_ADDR 0x10000000 /* free virtual address */ +#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ @@ -478,6 +488,10 @@ #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000) #endif +/* Memory Bank 1 (RESET) initialization */ +#define CFG_EBC_PB1AP 0x7f817200 //0x03017200 +#define CFG_EBC_PB1CR (CFG_RESET_BASE | 0x1c000) + /* Memory Bank 4 (FPGA / 32Bit) initialization */ #define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */ #define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */ @@ -512,4 +526,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_API 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index ec08ba7a2..f8e880181 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -571,6 +571,16 @@ #define CONFIG_SYS_EBC_CFG 0xB8400000 /* EBC0_CFG */ /* + * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO + * pin multiplexing correctly + */ +#if defined(CONFIG_ARCHES) +#define GPIO43_USE GPIO_SEL /* On Arches this pin is used as GPIO */ +#else +#define GPIO43_USE GPIO_ALT1 /* On Glacier this pin is used as ALT1 -> PerCS3 */ +#endif + +/* * PPC4xx GPIO Configuration */ #ifdef CONFIG_460EX @@ -698,7 +708,7 @@ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \ {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \ {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \ {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \ {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \ {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \ diff --git a/include/configs/fx12mm.h b/include/configs/fx12mm.h index d45e7a0ef..8481c33b9 100644 --- a/include/configs/fx12mm.h +++ b/include/configs/fx12mm.h @@ -57,11 +57,8 @@ #define CONFIG_PREBOOT "echo U-Boot is up and runnining;" /*Flash*/ -#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_2MX16_MEM0_BASEADDR #define CONFIG_SYS_FLASH_SIZE (4*1024*1024) #define CONFIG_SYS_MAX_FLASH_SECT 71 -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 #define MTDIDS_DEFAULT "nor0=fx12mm-flash" #define MTDPARTS_DEFAULT "mtdparts=fx12mm-flash:-(user)" diff --git a/include/configs/ml507.h b/include/configs/ml507.h index c637904fe..a7319e427 100644 --- a/include/configs/ml507.h +++ b/include/configs/ml507.h @@ -30,15 +30,15 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x340000 +#define CONFIG_ENV_OFFSET 0x340000 #define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET) /*Misc*/ -#define CONFIG_SYS_PROMPT "ml507:/# " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "ml507:/# " /* Monitor Command Prompt */ #define CONFIG_PREBOOT "echo U-Boot is up and runnining;" /*Flash*/ -#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) +#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) #define CONFIG_SYS_MAX_FLASH_SECT 259 #define MTDIDS_DEFAULT "nor0=ml507-flash" #define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)" diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h new file mode 100644 index 000000000..e7daa0771 --- /dev/null +++ b/include/configs/xilinx-ppc.h @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * (C) Copyright 2008 + * Georg Schardt <schardt@team-ctech.de> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __CONFIG_XLX_H +#define __CONFIG_XLX_H +/* +#define DEBUG +#define ET_DEBUG +*/ + +/*Mem Map*/ +#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (192 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/*Cmd*/ +#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_REGINFO +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_JFFS2_CMDLINE +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_PING +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_IMLS + +/*Misc*/ +#define CONFIG_BOOTDELAY 5/* autoboot after 5 seconds */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256/* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 + /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot Argument Buffer Size */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 + /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00C00000 + /* 4 ... 12 MB in DRAM */ +#define CONFIG_SYS_LOAD_ADDR 0x00400000 + /* default load address */ +#define CONFIG_SYS_EXTBDINFO 1 + /* Extended board_into (bd_t) */ +#define CONFIG_SYS_HZ 1000 + /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_LOOPW /* enable loopw command */ +#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE /* include version env variable */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + /* Initial Memory map for Linux */ + +/*Stack*/ +#define CONFIG_SYS_INIT_RAM_ADDR 0x800000/* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +/*Speed*/ +#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ + +/*Flash*/ +#ifdef XPAR_FLASH_MEM0_BASEADDR +#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_CMDLINE +#else +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_NO_FLASH +#endif + +/* serial communication */ +#ifdef XPAR_UARTLITE_0_BASEADDR +#define CONFIG_XILINX_UARTLITE +#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR +#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE +#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } +#else +#ifdef XPAR_UARTNS550_0_BASEADDR +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 4 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 XPAR_UARTNS550_0_BASEADDR +#define CONFIG_SYS_NS16550_CLK XPAR_UARTNS550_0_CLOCK_FREQ_HZ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 115200 } +#endif +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/xilinx-ppc405.h b/include/configs/xilinx-ppc405.h index 74584705c..d335f1e29 100644 --- a/include/configs/xilinx-ppc405.h +++ b/include/configs/xilinx-ppc405.h @@ -30,97 +30,10 @@ #define __CONFIG_H /* cpu parameter */ -#define CONFIG_4xx 1 #define CONFIG_405 1 +#define CONFIG_4xx 1 #define CONFIG_XILINX_405 1 -/* memory map */ -#define CONFIG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) - -/* u-boot commands configuration */ -#include <config_cmd_default.h> - -/*Misc*/ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* Extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_CMDLINE_EDITING /* add command line history */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_LOOPW /* enable loopw command */ -#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE /* include version env variable */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ -#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - /* Initial Memory map for Linux */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_CACHELINE_SHIFT 2 - -/* stack */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_FLASH_CF 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_PROTECTION - -/* serial communication */ -#ifdef XPAR_UARTLITE_0_BASEADDR -#define CONFIG_XILINX_UARTLITE -#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR -#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE -#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } -#else -#ifdef XPAR_UARTNS550_0_BASEADDR -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 4 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 XPAR_UARTNS550_0_BASEADDR -#define CONFIG_SYS_NS16550_CLK XPAR_UARTNS550_0_CLOCK_FREQ_HZ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 115200 } -#endif -#endif - -/* cmd config */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_JFFS2 -#define CONFIG_JFFS2_CMDLINE -#undef CONFIG_CMD_SPI -#undef CONFIG_CMD_I2C -#undef CONFIG_CMD_DTT -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_PING -#undef CONFIG_CMD_DHCP -#undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_IMLS +#include <configs/xilinx-ppc.h> #endif diff --git a/include/configs/xilinx-ppc440.h b/include/configs/xilinx-ppc440.h index ac78420bb..6e938dcf4 100644 --- a/include/configs/xilinx-ppc440.h +++ b/include/configs/xilinx-ppc440.h @@ -17,90 +17,12 @@ #ifndef __CONFIG_GEN_H #define __CONFIG_GEN_H -/* -#define DEBUG -#define ET_DEBUG -*/ - /*CPU*/ -#define CONFIG_XILINX_440 1 -#define CONFIG_440 1 -#define CONFIG_4xx 1 - -/*Mem Map*/ -#define CONFIG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) -/*Uart*/ -#define CONFIG_XILINX_UARTLITE -#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE -#define CONFIG_SYS_BAUDRATE_TABLE { XPAR_UARTLITE_0_BAUDRATE } -#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR - -/*Cmd*/ -#include <config_cmd_default.h> -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_JFFS2 -#define CONFIG_JFFS2_CMDLINE -#undef CONFIG_CMD_SPI -#undef CONFIG_CMD_I2C -#undef CONFIG_CMD_DTT -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_PING -#undef CONFIG_CMD_DHCP -#undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_IMLS - -/*Misc*/ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* Extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_CMDLINE_EDITING /* add command line history */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_LOOPW /* enable loopw command */ -#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE /* include version env variable */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ -#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */ - -/*Stack*/ -#define CONFIG_SYS_INIT_RAM_ADDR 0x800000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -/*Speed*/ -#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ +/*CPU*/ +#define CONFIG_4xx 1 +#define CONFIG_440 1 +#define CONFIG_XILINX_440 1 -/*Flash*/ -#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_PROTECTION +#include <configs/xilinx-ppc.h> #endif /* __CONFIG_H */ diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index ba573928b..e184fd2f2 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -250,7 +250,6 @@ void init_cplbtables(void) extern int exception_init(void); extern int irq_init(void); -extern int rtc_init(void); extern int timer_init(void); void board_init_f(ulong bootflag) @@ -313,9 +312,6 @@ void board_init_f(ulong bootflag) display_banner(); checkboard(); -#if defined(CONFIG_RTC_BFIN) && defined(CONFIG_CMD_DATE) - rtc_init(); -#endif timer_init(); printf("Clock: VCO: %lu MHz, Core: %lu MHz, System: %lu MHz\n", @@ -384,6 +380,11 @@ void board_init_r(gd_t * id, ulong dest_addr) spi_init_r(); #endif +#ifdef CONFIG_CMD_NAND + puts("NAND: "); + nand_init(); /* go init the NAND */ +#endif + /* relocate environment function pointers etc. */ env_relocate(); @@ -431,11 +432,6 @@ void board_init_r(gd_t * id, ulong dest_addr) copy_filename(BootFile, s, sizeof(BootFile)); #endif -#ifdef CONFIG_CMD_NAND - puts("NAND: "); - nand_init(); /* go init the NAND */ -#endif - #if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ misc_init_r(); diff --git a/lib_blackfin/cache.c b/lib_blackfin/cache.c index c2f6e2848..870c5bfba 100644 --- a/lib_blackfin/cache.c +++ b/lib_blackfin/cache.c @@ -11,6 +11,7 @@ #include <common.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/mpu.h> void flush_cache(unsigned long addr, unsigned long size) { @@ -24,3 +25,37 @@ void flush_cache(unsigned long addr, unsigned long size) if (dcache_status()) blackfin_dcache_flush_range((void *)addr, (void *)(addr + size)); } + +void icache_enable(void) +{ + bfin_write_IMEM_CONTROL(IMC | ENICPLB); + SSYNC(); +} + +void icache_disable(void) +{ + bfin_write_IMEM_CONTROL(0); + SSYNC(); +} + +int icache_status(void) +{ + return bfin_read_IMEM_CONTROL() & IMC; +} + +void dcache_enable(void) +{ + bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); + SSYNC(); +} + +void dcache_disable(void) +{ + bfin_write_DMEM_CONTROL(0); + SSYNC(); +} + +int dcache_status(void) +{ + return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE; +} diff --git a/libfdt/fdt_ro.c b/libfdt/fdt_ro.c index b705f91ec..fdc9c29d2 100644 --- a/libfdt/fdt_ro.c +++ b/libfdt/fdt_ro.c @@ -112,12 +112,12 @@ int fdt_num_mem_rsv(const void *fdt) int fdt_subnode_offset_namelen(const void *fdt, int offset, const char *name, int namelen) { - int depth; + int depth = 0; FDT_CHECK_HEADER(fdt); - for (depth = 0; - offset >= 0; + for (depth = 0, offset = fdt_next_node(fdt, offset, &depth); + (offset >= 0) && (depth > 0); offset = fdt_next_node(fdt, offset, &depth)) { if (depth < 0) return -FDT_ERR_NOTFOUND; @@ -126,7 +126,10 @@ int fdt_subnode_offset_namelen(const void *fdt, int offset, return offset; } - return offset; /* error */ + if (offset < 0) + return offset; /* error */ + else + return -FDT_ERR_NOTFOUND; } int fdt_subnode_offset(const void *fdt, int parentoffset, |