diff options
44 files changed, 98 insertions, 98 deletions
diff --git a/board/Marvell/db64360/pci.c b/board/Marvell/db64360/pci.c index a7e3c95b8..499809514 100644 --- a/board/Marvell/db64360/pci.c +++ b/board/Marvell/db64360/pci.c @@ -52,13 +52,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host) printf ("PCI %d bus mode: Conventional PCI\n", host); break; case 1: - printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 66 MHz PCIX\n", host); break; case 2: - printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 100 MHz PCIX\n", host); break; case 3: - printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 133 MHz PCIX\n", host); break; default: printf ("Unknown BUS %d\n", mode); diff --git a/board/Marvell/db64460/pci.c b/board/Marvell/db64460/pci.c index a7e3c95b8..499809514 100644 --- a/board/Marvell/db64460/pci.c +++ b/board/Marvell/db64460/pci.c @@ -52,13 +52,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host) printf ("PCI %d bus mode: Conventional PCI\n", host); break; case 1: - printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 66 MHz PCIX\n", host); break; case 2: - printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 100 MHz PCIX\n", host); break; case 3: - printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 133 MHz PCIX\n", host); break; default: printf ("Unknown BUS %d\n", mode); diff --git a/board/amcc/katmai/cmd_katmai.c b/board/amcc/katmai/cmd_katmai.c index 703d22560..ba71bd55c 100644 --- a/board/amcc/katmai/cmd_katmai.c +++ b/board/amcc/katmai/cmd_katmai.c @@ -57,9 +57,9 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) do { #ifdef CONFIG_STRESS - printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n"); + printf("enter cpu clock frequency 400, 500, 533, 667 MHz or quit to abort\n"); #else - printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n"); + printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n"); #endif nbytes = readline (" ? "); @@ -87,11 +87,11 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else { do { if (strcmp(cpuClock, "400") == 0) - printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n"); + printf("enter plb clock frequency 100, 133 MHz or quit to abort\n"); #ifdef CONFIG_STRESS if (strcmp(cpuClock, "667") == 0) - printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n"); + printf("enter plb clock frequency 133, 166 MHz or quit to abort\n"); #endif nbytes = readline (" ? "); @@ -117,7 +117,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } do { - printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n"); + printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n"); nbytes = readline (" ? "); if (strcmp(console_buffer, "quit") == 0) @@ -133,10 +133,10 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } while (nbytes == 0); - printf("\nsys clk = %sMhz\n", sysClock); - printf("cpu clk = %sMhz\n", cpuClock); - printf("plb clk = %sMhz\n", plbClock); - printf("Pci-X clk = %sMhz\n", pcixClock); + printf("\nsys clk = %s MHz\n", sysClock); + printf("cpu clk = %s MHz\n", cpuClock); + printf("plb clk = %s MHz\n", plbClock); + printf("Pci-X clk = %s MHz\n", pcixClock); do { printf("\npress [y] to write I2C bootstrap \n"); diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c index bd42c5d46..d9698602b 100644 --- a/board/amcc/yucca/cmd_yucca.c +++ b/board/amcc/yucca/cmd_yucca.c @@ -69,7 +69,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, chip = IIC0_ALT_BOOTPROM_ADDR; do { - printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n"); + printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n"); nbytes = readline (" ? "); if (strcmp(console_buffer, "quit") == 0) @@ -85,12 +85,12 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, do { if (strcmp(sysClock, "66") == 0) { - printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n"); + printf("enter cpu clock frequency 400, 533 MHz or quit to abort\n"); } else { #ifdef CONFIG_STRESS - printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n"); + printf("enter cpu clock frequency 400, 500, 533, 667 MHz or quit to abort\n"); #else - printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n"); + printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n"); #endif } nbytes = readline (" ? "); @@ -130,11 +130,11 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, } else { do { if (strcmp(cpuClock, "400") == 0) - printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n"); + printf("enter plb clock frequency 100, 133 MHz or quit to abort\n"); #ifdef CONFIG_STRESS if (strcmp(cpuClock, "667") == 0) - printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n"); + printf("enter plb clock frequency 133, 166 MHz or quit to abort\n"); #endif nbytes = readline (" ? "); @@ -160,7 +160,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, } do { - printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n"); + printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n"); nbytes = readline (" ? "); if (strcmp(console_buffer, "quit") == 0) @@ -176,10 +176,10 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, } while (nbytes == 0); - printf("\nsys clk = %sMhz\n", sysClock); - printf("cpu clk = %sMhz\n", cpuClock); - printf("plb clk = %sMhz\n", plbClock); - printf("Pci-X clk = %sMhz\n", pcixClock); + printf("\nsys clk = %s MHz\n", sysClock); + printf("cpu clk = %s MHz\n", cpuClock); + printf("plb clk = %s MHz\n", plbClock); + printf("Pci-X clk = %s MHz\n", pcixClock); do { printf("\npress [y] to write I2C bootstrap \n"); diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c index 7c36c8155..889aa5c4f 100644 --- a/board/bf537-stamp/post-memory.c +++ b/board/bf537-stamp/post-memory.c @@ -27,18 +27,18 @@ const int pll[CCLK_NUM][SCLK_NUM][2] = { {{4, 1}, {4, 2}, {4, 4}} /* CCLK = 100M */ }; const char *const log[CCLK_NUM][SCLK_NUM] = { - {"CCLK-500Mhz SCLK-125Mhz: Writing...\0", - "CCLK-500Mhz SCLK-100Mhz: Writing...\0", - "CCLK-500Mhz SCLK- 50Mhz: Writing...\0",}, - {"CCLK-400Mhz SCLK-100Mhz: Writing...\0", - "CCLK-400Mhz SCLK- 80Mhz: Writing...\0", - "CCLK-400Mhz SCLK- 50Mhz: Writing...\0",}, - {"CCLK-200Mhz SCLK-100Mhz: Writing...\0", - "CCLK-200Mhz SCLK- 50Mhz: Writing...\0", - "CCLK-200Mhz SCLK- 40Mhz: Writing...\0",}, - {"CCLK-100Mhz SCLK-100Mhz: Writing...\0", - "CCLK-100Mhz SCLK- 50Mhz: Writing...\0", - "CCLK-100Mhz SCLK- 25Mhz: Writing...\0",}, + {"CCLK-500MHz SCLK-125MHz: Writing...\0", + "CCLK-500MHz SCLK-100MHz: Writing...\0", + "CCLK-500MHz SCLK- 50MHz: Writing...\0",}, + {"CCLK-400MHz SCLK-100MHz: Writing...\0", + "CCLK-400MHz SCLK- 80MHz: Writing...\0", + "CCLK-400MHz SCLK- 50MHz: Writing...\0",}, + {"CCLK-200MHz SCLK-100MHz: Writing...\0", + "CCLK-200MHz SCLK- 50MHz: Writing...\0", + "CCLK-200MHz SCLK- 40MHz: Writing...\0",}, + {"CCLK-100MHz SCLK-100MHz: Writing...\0", + "CCLK-100MHz SCLK- 50MHz: Writing...\0", + "CCLK-100MHz SCLK- 25MHz: Writing...\0",}, }; int memory_post_test(int flags) diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c index 2babd2d35..1c82bdf12 100644 --- a/board/cray/L1/L1.c +++ b/board/cray/L1/L1.c @@ -205,13 +205,13 @@ static void init_sdram (void) /* To set the appropriate timings, we need to know the SDRAM speed. */ /* We can use the PLB speed since the SDRAM speed is the same as */ /* the PLB speed. The PLB speed is the FBK divider times the */ -/* 405GP reference clock, which on the L1 is 25Mhz. */ -/* Thus, if FBK div is 2, SDRAM is 50Mhz; if FBK div is 3, SDRAM is */ -/* 150Mhz; if FBK is 3, SDRAM is 150Mhz. */ +/* 405GP reference clock, which on the L1 is 25MHz. */ +/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is */ +/* 150MHz; if FBK is 3, SDRAM is 150MHz. */ /* divisor = ((mfdcr(strap)>> 28) & 0x3); */ -/* write SDRAM timing for 100Mhz. */ +/* write SDRAM timing for 100MHz. */ mtdcr (memcfga, mem_sdtr1); mtdcr (memcfgd, 0x0086400D); diff --git a/board/eltec/bab7xx/misc.c b/board/eltec/bab7xx/misc.c index 1c94a76d4..bc6eb4055 100644 --- a/board/eltec/bab7xx/misc.c +++ b/board/eltec/bab7xx/misc.c @@ -377,7 +377,7 @@ int misc_init_r (void) { if (pci_find_device(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, 0) > 0) { - /* BAB740 with SCSI=IRQ 11; SCC=IRQ 9; no IDE; NCR860 at 80 Mhz */ + /* BAB740 with SCSI=IRQ 11; SCC=IRQ 9; no IDE; NCR860 at 80 MHz */ scsi_dev_id = PCI_DEVICE_ID_NCR_53C860; scsi_max_scsi_id = 7; scsi_sym53c8xx_ccf = 0x15; diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c index cbe766ffd..bfc7e555b 100644 --- a/board/esd/cpci750/pci.c +++ b/board/esd/cpci750/pci.c @@ -66,13 +66,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host) printf ("PCI %d bus mode: Conventional PCI\n", host); break; case 1: - printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 66 MHz PCIX\n", host); break; case 2: - printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 100 MHz PCIX\n", host); break; case 3: - printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 133 MHz PCIX\n", host); break; default: printf ("Unknown BUS %d\n", mode); diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index 4db70521b..911278898 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -347,7 +347,7 @@ int checkboard (void) if (value) { puts(", 33 MHz PCI"); } else { - puts(", 66 Mhz PCI"); + puts(", 66 MHz PCI"); } } diff --git a/board/fads/fads.c b/board/fads/fads.c index 278fa2ab2..9f7faaf47 100644 --- a/board/fads/fads.c +++ b/board/fads/fads.c @@ -449,19 +449,19 @@ static int _initsdram(uint base, uint noMbytes) /* Now run the precharge/nop/mrs commands. */ - memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50Mhz) */ - /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100Mhz) */ + memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50MHz) */ + /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */ udelay(200); /* Run 8 refresh cycles */ - memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 Mhz)*/ + memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 MHz)*/ /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */ udelay(200); - memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 Mhz) or TLF 8 (50MHz) */ - memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 Mhz) */ + memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 MHz) or TLF 8 (50MHz) */ + memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 MHz) */ /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */ udelay(200); diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index 7dccd3735..a0b6fbd12 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -127,8 +127,8 @@ local_bus_init(void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 7c35c35fc..7e40c5c80 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -302,8 +302,8 @@ local_bus_init(void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 4cd25b671..33685c19f 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -302,8 +302,8 @@ local_bus_init(void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 4fe1d8538..37308189d 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -331,8 +331,8 @@ local_bus_init(void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ diff --git a/board/gen860t/beeper.c b/board/gen860t/beeper.c index b472b914e..c6be83f65 100644 --- a/board/gen860t/beeper.c +++ b/board/gen860t/beeper.c @@ -36,7 +36,7 @@ /* * Initialize beeper-related hardware. Initialize timer 1 for use with - * the beeper. Use 66 Mhz internal clock with prescale of 33 to get + * the beeper. Use 66 MHz internal clock with prescale of 33 to get * 1 uS period per count. * FIXME: we should really compute the prescale based on the reported * core clock frequency. diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c index 3771c191e..682991379 100644 --- a/board/idmr/idmr.c +++ b/board/idmr/idmr.c @@ -78,7 +78,7 @@ phys_size_t initdram (int board_type) { MCF_GPIO_SDRAM_SDCS_01); /* - * Wait 100us. We run the bus at 50Mhz, one cycle is 20ns. So 5 + * Wait 100us. We run the bus at 50MHz, one cycle is 20ns. So 5 * iterations will do, but we do 10 just to be safe. */ for (i = 0; i < 10; ++i) diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index 842bce6f3..b3692190b 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -5,7 +5,7 @@ * modified for Promess PRO - by Andy Joseph, andy@promessdev.com * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3 - * Also changed the refresh for 100Mhz operation + * Also changed the refresh for 100MHz operation * * See file CREDITS for list of people who contributed to this * project. diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index 9b564b892..fa0a33686 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -100,7 +100,7 @@ phys_size_t initdram (int board_type) #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ get_sys_info(&sysinfo); - /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ + /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) { lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000; } else { diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index 3be010470..8724e27af 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -252,7 +252,7 @@ int board_early_init_f (void) (datain[2] != 0x04) || /* if not SDRAM */ (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */ (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */ - (datain[126] == 0x66)) /* or a 66Mhz modules */ + (datain[126] == 0x66)) /* or a 66MHz modules */ SDRAM_err ("unsupported SDRAM"); #ifdef SDRAM_DEBUG serial_puts ("SDRAM sanity ok\n"); diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index db855df6f..fed0ed431 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -144,8 +144,8 @@ local_bus_init(void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index 50c42810b..932f1121e 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -300,8 +300,8 @@ local_bus_init(void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ diff --git a/board/prodrive/p3mx/pci.c b/board/prodrive/p3mx/pci.c index 85f7caab0..e36b67664 100644 --- a/board/prodrive/p3mx/pci.c +++ b/board/prodrive/p3mx/pci.c @@ -66,13 +66,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host) printf ("PCI %d bus mode: Conventional PCI\n", host); break; case 1: - printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 66 MHz PCIX\n", host); break; case 2: - printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 100 MHz PCIX\n", host); break; case 3: - printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 133 MHz PCIX\n", host); break; default: printf ("Unknown BUS %d\n", mode); diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index f01f87e1a..3d4008b00 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -297,7 +297,7 @@ phys_size_t initdram (int board_type) #if 0 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */ get_sys_info(&sysinfo); - /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ + /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) { lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000; } else { diff --git a/board/siemens/IAD210/IAD210.c b/board/siemens/IAD210/IAD210.c index e9e7f8472..e21bb245a 100644 --- a/board/siemens/IAD210/IAD210.c +++ b/board/siemens/IAD210/IAD210.c @@ -240,7 +240,7 @@ int board_early_init_f (void) iop->iop_padir = 0x0800; /* start timer 2 for the 4hz LED blink rate */ - timers->cpmt_tmr2 = 0xff2c; /* 4hz for 64mhz */ + timers->cpmt_tmr2 = 0xff2c; /* 4HZ for 64MHz */ timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */ timers->cpmt_tgcr = 0x00000810; /* run timer 2 */ diff --git a/board/siemens/IAD210/atm.c b/board/siemens/IAD210/atm.c index d1b75bca3..e599c1061 100644 --- a/board/siemens/IAD210/atm.c +++ b/board/siemens/IAD210/atm.c @@ -579,7 +579,7 @@ void atmUtpInit() /* 11 = divide by 7 */ /* */ /* Note that the UTOPIA clock must be programmed as to operate */ - /* within the range SYSCLK/10 .. 50Mhz. */ + /* within the range SYSCLK/10 .. 50MHz. */ /*-----------------------------------------------------------------*/ car->car_sccr &= 0xFFFFFFE0; car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */ diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index f69de9575..1f309bbc6 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -458,8 +458,8 @@ void local_bus_init (void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ diff --git a/cpu/ixp/npe/miiphy.c b/cpu/ixp/npe/miiphy.c index c63c54e28..20fee2d39 100644 --- a/cpu/ixp/npe/miiphy.c +++ b/cpu/ixp/npe/miiphy.c @@ -32,7 +32,7 @@ | Date Description of Change BY | --------- --------------------- --- | 05-May-99 Created MKW - | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to + | 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to | better match OPB speed. Also modified delay times. JWB | 29-Jul-99 Added Full duplex support MKW | 24-Aug-99 Removed printf from dp83843_duplex() JWB diff --git a/cpu/mips/incaip_clock.c b/cpu/mips/incaip_clock.c index d0515ca67..fc2c62180 100644 --- a/cpu/mips/incaip_clock.c +++ b/cpu/mips/incaip_clock.c @@ -33,8 +33,8 @@ * * RETURNS: * 150.000.000 for 150 MHz -* 133.333.333 for 133 Mhz (= 400MHz/3) -* 100.000.000 for 100 Mhz (= 400MHz/4) +* 133.333.333 for 133 MHz (= 400MHz/3) +* 100.000.000 for 100 MHz (= 400MHz/4) * NOTE: * This functions should be used by the hardware driver to get the correct * frequency of the CPU. Don't use the macros, which are set to init the CPU diff --git a/cpu/mpc8220/i2cCore.c b/cpu/mpc8220/i2cCore.c index accf43c10..b89ad034f 100644 --- a/cpu/mpc8220/i2cCore.c +++ b/cpu/mpc8220/i2cCore.c @@ -440,7 +440,7 @@ STATUS i2c_write2byte (SI2C * pi2c, UINT16 * writeb) return OK; } -/* FDR table base on 33Mhz - more detail please refer to Odini2c_dividers.xls +/* FDR table base on 33MHz - more detail please refer to Odini2c_dividers.xls FDR FDR scl sda scl2tap2 510 432 tap tap tap tap scl_per sda_hold I2C Freq 0 1 2 3 4 5 000 000 9 3 4 1 28 Clocks 9 Clocks 1190 KHz 0 0 0 0 0 0 diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 359a91558..42a4e675d 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -314,7 +314,7 @@ long int spd_sdram() + (spd.clk_cycle & 0x0f)); max_data_rate = max_bus_clk * 2; - debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate); + debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate); ddrc_clk = gd->mem_clk / 1000000; effective_data_rate = 0; @@ -401,7 +401,7 @@ long int spd_sdram() } } - debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate); + debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate); debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat); /* diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index 141425d8e..89c1ff939 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -398,7 +398,7 @@ static void fec_pin_init(int fecidx) * * the MII management interface clock must be less than or equal * * to 2.5 MHz. * * This MDC frequency is equal to system clock / (2 * MII_SPEED). - * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz. + * * Then MII_SPEED = system_clock / 2 * 2,5 MHz. * * All MII configuration is done via FEC1 registers: */ diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index cae90ddaf..bd90dcd3b 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -70,7 +70,7 @@ static void serial_setdivisor(volatile cpm8xx_t *cp) int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate; if(divisor/16>0x1000) { - /* bad divisor, assume 50Mhz clock and 9600 baud */ + /* bad divisor, assume 50MHz clock and 9600 baud */ divisor=(50*1000*1000 + 8*9600)/16/9600; } diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index eca92e83b..e8871fc45 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -286,7 +286,7 @@ void pci_405gp_init(struct pci_controller *hose) #endif /* CONFIG_SYS_PCI_CLASSCODE */ /*--------------------------------------------------------------------------+ - * If PCI speed = 66Mhz, set 66Mhz capable bit. + * If PCI speed = 66MHz, set 66MHz capable bit. *--------------------------------------------------------------------------*/ if (bd->bi_pci_busfreq >= 66000000) { pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short); diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index 84b1bbe54..01710e71d 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -301,7 +301,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value) sta_reg = reg; /* reg address */ - /* set clock (50Mhz) and read flags */ + /* set clock (50MHz) and read flags */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index d21bd82dc..ed6e55b69 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -148,7 +148,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO * to make sure it is within the proper range. * spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV - * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding. + * Note freqVCO is calculated in MHz to avoid errors introduced by rounding. */ if (sysInfo->pllFwdDiv == 1) { sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ; diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c index fd09bf910..2960f2f3a 100644 --- a/cpu/s3c44b0/cpu.c +++ b/cpu/s3c44b0/cpu.c @@ -256,7 +256,7 @@ void i2c_init(int speed, int slaveaddr) /* Enable ACK, IICCLK=MCLK/16, enable interrupt - 75Mhz/16/(12+1) = 390625 Hz + 75MHz/16/(12+1) = 390625 Hz */ rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC); IICCON = rIICCON; diff --git a/drivers/block/sym53c8xx.c b/drivers/block/sym53c8xx.c index 0c60bf80e..8094b415a 100644 --- a/drivers/block/sym53c8xx.c +++ b/drivers/block/sym53c8xx.c @@ -836,10 +836,10 @@ void scsi_chip_init(void) scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */ scsi_write_byte(SCNTL1,0x00); scsi_write_byte(SCNTL2,0x00); -#ifndef CONFIG_SYS_SCSI_SYM53C8XX_CCF /* config value for none 40 mhz clocks */ +#ifndef CONFIG_SYS_SCSI_SYM53C8XX_CCF /* config value for none 40 MHz clocks */ scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */ #else - scsi_write_byte(SCNTL3,CONFIG_SYS_SCSI_SYM53C8XX_CCF); /* config value for none 40 mhz clocks */ + scsi_write_byte(SCNTL3,CONFIG_SYS_SCSI_SYM53C8XX_CCF); /* config value for none 40 MHz clocks */ #endif scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */ scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */ diff --git a/drivers/i2c/omap1510_i2c.c b/drivers/i2c/omap1510_i2c.c index a4e6227c5..f91ee8884 100644 --- a/drivers/i2c/omap1510_i2c.c +++ b/drivers/i2c/omap1510_i2c.c @@ -32,7 +32,7 @@ void i2c_init (int speed, int slaveadd) udelay (5000); } - /* 12Mhz I2C module clock */ + /* 12MHz I2C module clock */ outw (0, I2C_PSC); outw (I2C_CON_EN, I2C_CON); outw (0, I2C_SYSTEST); diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 134dccb61..d2e8207c5 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -45,7 +45,7 @@ void i2c_init (int speed, int slaveadd) udelay (50000); } - /* 12Mhz I2C module clock */ + /* 12MHz I2C module clock */ outw (0, I2C_PSC); speed = speed/1000; /* 100 or 400 */ scl = ((12000/(speed*2)) - 7); /* use 7 when PSC = 0 */ diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c index ff8d2d7c0..ce12c3b62 100644 --- a/drivers/net/natsemi.c +++ b/drivers/net/natsemi.c @@ -409,7 +409,7 @@ natsemi_initialize(bd_t * bis) The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */ /* Delay between EEPROM clock transitions. - No extra delay is needed with 33Mhz PCI, but future 66Mhz + No extra delay is needed with 33MHz PCI, but future 66MHz access may need a delay. */ #define eeprom_delay(ee_addr) INL(dev, ee_addr) diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c index a2d61afec..198f73dee 100644 --- a/drivers/net/ns8382x.c +++ b/drivers/net/ns8382x.c @@ -445,7 +445,7 @@ ns8382x_initialize(bd_t * bis) Read and write MII registers using software-generated serial MDIO protocol. See the MII specifications or DP83840A data sheet for details. - The maximum data clock rate is 2.5 Mhz. To meet minimum timing we + The maximum data clock rate is 2.5 MHz. To meet minimum timing we must flush writes to the PCI bus with a PCI read. */ #define mdio_delay(mdio_addr) INL(dev, mdio_addr) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index d378ce39b..db8a727c8 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -287,7 +287,7 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) /* Delay between EEPROM clock transitions. - No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. + No extra delay is needed with 33MHz PCI, but 66MHz may change this. */ #define eeprom_delay() inl(ee_addr) diff --git a/drivers/net/tigon3.c b/drivers/net/tigon3.c index ab448b0f8..e4e004eed 100644 --- a/drivers/net/tigon3.c +++ b/drivers/net/tigon3.c @@ -2247,7 +2247,7 @@ LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice) REG_WR (pDevice, Grc.Mode, Value32); /* Setup the timer prescalar register. */ - REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */ + REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66MHz. */ /* Set up the MBUF pool base address and size. */ REG_WR (pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase); diff --git a/drivers/usb/usbdcore_mpc8xx.c b/drivers/usb/usbdcore_mpc8xx.c index fa02003d1..53bde0dca 100644 --- a/drivers/usb/usbdcore_mpc8xx.c +++ b/drivers/usb/usbdcore_mpc8xx.c @@ -1227,7 +1227,7 @@ static void mpc8xx_udc_clock_init (volatile immap_t * immr, return; } - /* Assume the brgclk is 'good enough', we want !(gd->cpu_clk%48Mhz) + /* Assume the brgclk is 'good enough', we want !(gd->cpu_clk%48MHz) * but, can /probably/ live with close-ish alternative rates. */ divisor = (gd->cpu_clk / 48000000L) - 1; |