diff options
| -rw-r--r-- | board/sbc8548/law.c | 5 | ||||
| -rw-r--r-- | board/sbc8548/tlb.c | 2 | ||||
| -rw-r--r-- | doc/README.sbc8548 | 21 | ||||
| -rw-r--r-- | include/configs/sbc8548.h | 13 |
4 files changed, 40 insertions, 1 deletions
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index c263191c3..322af76d6 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -59,8 +59,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif +#ifdef CONFIG_SYS_LBC_SDRAM_BASE /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#else + /* LBC window - maps 128M 0xf8000000 -> 0xffffffff */ + SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), +#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 4bf72147b..af927f165 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -76,6 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_64M, 1), +#ifdef CONFIG_SYS_LBC_SDRAM_BASE /* * TLB 3: 64M Cacheable, non-guarded * 0xf0000000 64M LBC SDRAM First half @@ -92,6 +93,7 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 4, BOOKE_PAGESZ_64M, 1), +#endif /* * TLB 5: 16M Cacheable, non-guarded diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index e6b8abe2b..f9e2dea57 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -62,6 +62,27 @@ a 33MHz PCI configuration is currently untested.) 02.00.00 0x1148 0x9e00 Network controller 0x00 => +Memory Size and using SPD: +========================== + +The default configuration uses hard coded memory configuration settings +for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD +EEPROM data to read what memory is installed. + +There is a hardware errata, which causes the older local bus SDRAM +SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so +that the SPD data can not be read reliably. + +If you want to upgrade to larger RAM size, you can simply enable + #define CONFIG_SPD_EEPROM + #define CONFIG_DDR_SPD +in include/configs/sbc8548.h file. (The lines are already there +but listed as #undef). + +Note that you will have to physically remove the LBC 128MB DIMM +from the board's socket to resolve the above i2c address overlap +issue and allow SPD autodetection of RAM to work. + Updating U-boot with U-boot: ============================ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 1df2225a7..44c75269c 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -119,9 +119,15 @@ /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +/* + * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD + * to collide, meaning you couldn't reliably read either. So + * physically remove the LBC PC100 SDRAM module from the board + * before enabling the two SPD options below. + */ #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #undef CONFIG_DDR_SPD -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -283,9 +289,14 @@ /* * SDRAM on the Local Bus (CS3 and CS4) + * Note that most boards have a hardware errata where both the + * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible + * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. */ +#ifndef CONFIG_DDR_SPD #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ +#endif /* * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. |