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-rw-r--r--drivers/mtd/spi/sf_internal.h2
-rw-r--r--drivers/mtd/spi/sf_ops.c2
-rw-r--r--drivers/mtd/spi/sf_probe.c178
-rw-r--r--include/spi.h9
-rw-r--r--include/spi_flash.h11
5 files changed, 113 insertions, 89 deletions
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 938a78efc..dcc9014e5 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -28,6 +28,7 @@
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
#define CMD_READ_STATUS 0x05
+#define CMD_QUAD_PAGE_PROGRAM 0x32
#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG 0x35
@@ -38,6 +39,7 @@
#define CMD_READ_ARRAY_FAST 0x0b
#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
#define CMD_READ_DUAL_IO_FAST 0xbb
+#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
#define CMD_READ_ID 0x9f
/* Bank addr access commands */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 49ceef0ed..3d304ce6a 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -210,7 +210,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
page_size = flash->page_size;
- cmd[0] = CMD_PAGE_PROGRAM;
+ cmd[0] = flash->write_cmd;
for (actual = 0; actual < len; actual += chunk_len) {
#ifdef CONFIG_SPI_FLASH_BAR
ret = spi_flash_bank(flash, offset);
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index c0baac620..3fa7363da 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -42,105 +42,105 @@ struct spi_flash_params {
static const struct spi_flash_params spi_flash_params_table[] = {
#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K},
- {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K},
- {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K},
- {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K},
- {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K},
- {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K},
+ {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K},
+ {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_EON /* EON */
- {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0},
- {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0},
- {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0},
+ {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0},
+ {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0},
+ {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0},
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
- {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0},
- {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0},
- {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0},
- {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0},
- {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0},
- {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0},
- {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0, 0},
- {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0, 0},
- {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, 0, 0},
- {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0, 0},
+ {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0},
+ {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0},
+ {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0},
+ {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0},
+ {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0},
+ {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0},
+ {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0, 0},
+ {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0, 0},
+ {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, 0, 0},
+ {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0, 0},
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
- {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0},
- {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0},
- {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0},
- {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0},
- {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, 0, 0},
- {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, 0, 0},
- {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0, 0},
- {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0, 0},
- {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0, 0},
- {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_EXTN, 0},
- {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_EXTN, 0},
- {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0, 0},
- {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0, 0},
+ {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0},
+ {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0},
+ {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0},
+ {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0},
+ {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, 0, 0},
+ {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, 0, 0},
+ {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0, 0},
+ {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0, 0},
+ {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0, 0},
+ {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0, 0},
+ {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0, 0},
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
- {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0},
- {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0},
- {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0},
- {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0},
- {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0},
- {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0},
- {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0},
- {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
- {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, 0, SECT_4K},
- {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, 0, SECT_4K},
- {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, 0, SECT_4K},
- {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, 0, SECT_4K},
- {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K},
- {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K},
- {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K},
- {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K},
+ {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0},
+ {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0},
+ {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0},
+ {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0},
+ {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0},
+ {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0},
+ {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0},
+ {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
+ {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, 0, SECT_4K},
+ {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, 0, SECT_4K},
+ {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, 0, SECT_4K},
+ {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, 0, SECT_4K},
+ {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K},
+ {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K},
+ {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K},
+ {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_SST /* SST */
- {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
- {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
- {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP},
- {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP},
- {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP},
- {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP},
- {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP},
- {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
- {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
+ {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
+ {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
+ {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP},
+ {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP},
+ {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP},
+ {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP},
+ {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP},
+ {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
+ {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
#endif
#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
- {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0},
- {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0},
- {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0},
- {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K},
- {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K},
- {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, 0, SECT_4K},
- {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, 0, SECT_4K},
- {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, 0, SECT_4K},
- {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, 0, SECT_4K},
- {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, 0, SECT_4K},
- {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, 0, SECT_4K},
- {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, 0, SECT_4K},
- {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, 0, SECT_4K},
- {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, 0, SECT_4K},
+ {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0},
+ {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0},
+ {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0},
+ {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K},
+ {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, 0, SECT_4K},
+ {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, 0, SECT_4K},
+ {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, 0, SECT_4K},
+ {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, 0, SECT_4K},
+ {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, 0, SECT_4K},
+ {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, 0, SECT_4K},
+ {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, 0, SECT_4K},
+ {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, 0, SECT_4K},
#endif
/*
* Note:
@@ -162,6 +162,7 @@ static u8 spi_read_cmds_array[] = {
CMD_READ_ARRAY_SLOW,
CMD_READ_DUAL_OUTPUT_FAST,
CMD_READ_DUAL_IO_FAST,
+ CMD_READ_QUAD_OUTPUT_FAST,
};
static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
@@ -242,6 +243,13 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
flash->read_cmd = CMD_READ_ARRAY_FAST;
}
+ /* Not require to look for fastest only two write cmds yet */
+ if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP)
+ flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
+ else
+ /* Go for default supported write cmd */
+ flash->write_cmd = CMD_PAGE_PROGRAM;
+
/* Poll cmd seclection */
flash->poll_cmd = CMD_READ_STATUS;
#ifdef CONFIG_SPI_FLASH_STMICRO
diff --git a/include/spi.h b/include/spi.h
index 31195a307..5dd490a66 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -31,11 +31,16 @@
#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */
#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
+/* SPI TX operation modes */
+#define SPI_OPM_TX_QPP 1 << 0
+
/* SPI RX operation modes */
#define SPI_OPM_RX_AS 1 << 0
#define SPI_OPM_RX_DOUT 1 << 1
#define SPI_OPM_RX_DIO 1 << 2
-#define SPI_OPM_RX_EXTN SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | SPI_OPM_RX_DIO
+#define SPI_OPM_RX_QOF 1 << 3
+#define SPI_OPM_RX_EXTN SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \
+ SPI_OPM_RX_DIO | SPI_OPM_RX_QOF
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
@@ -50,6 +55,7 @@
* @bus: ID of the bus that the slave is attached to.
* @cs: ID of the chip select connected to the slave.
* @op_mode_rx: SPI RX operation mode.
+ * @op_mode_tx: SPI TX operation mode.
* @wordlen: Size of SPI word in number of bits
* @max_write_size: If non-zero, the maximum number of bytes which can
* be written at once, excluding command bytes.
@@ -59,6 +65,7 @@ struct spi_slave {
unsigned int bus;
unsigned int cs;
u8 op_mode_rx;
+ u8 op_mode_tx;
unsigned int wordlen;
unsigned int max_write_size;
void *memory_map;
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 692e143b6..9fd9d3bd5 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -19,13 +19,18 @@
#include <linux/types.h>
#include <linux/compiler.h>
-/* Enum list - Extended read commands */
+/* No enum list for write commands only QPP */
+#define WR_QPP 1 << 4
+
+/* Enum list - Full read commands */
enum spi_read_cmds {
ARRAY_SLOW = 1 << 0,
DUAL_OUTPUT_FAST = 1 << 1,
DUAL_IO_FAST = 1 << 2,
+ QUAD_OUTPUT_FAST = 1 << 3,
};
#define RD_EXTN ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST
+#define RD_FULL RD_EXTN | QUAD_OUTPUT_FAST
/**
* struct spi_flash - SPI flash structure
@@ -41,7 +46,8 @@ enum spi_read_cmds {
* @bank_curr: Current flash bank
* @poll_cmd: Poll cmd - for flash erase/program
* @erase_cmd: Erase cmd 4K, 32K, 64K
- * @read_cmd: Read cmd - Array Fast and Extn read
+ * @read_cmd: Read cmd - Array Fast, Extn read and quad read.
+ * @write_cmd: Write cmd - page and quad program.
* @memory_map: Address of read-only SPI flash access
* @read: Flash read ops: Read len bytes at offset into buf
* Supported cmds: Fast Array Read
@@ -67,6 +73,7 @@ struct spi_flash {
u8 poll_cmd;
u8 erase_cmd;
u8 read_cmd;
+ u8 write_cmd;
void *memory_map;
int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
generated by cgit v1.2.3-70-g09d2 (git 2.51.2) at 2025-10-31 12:35:37 +0000