diff options
| -rw-r--r-- | config.mk | 9 | ||||
| -rw-r--r-- | include/configs/omap3_h1.h | 24 |
2 files changed, 24 insertions, 9 deletions
@@ -207,6 +207,12 @@ gccincdir := $(shell $(CC) -print-file-name=include) CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ -D__KERNEL__ +# For omap3_h1.h we let the UART boot flag also trigger BCH8 error correction. + +ifdef BOOT_DEVICE_UART +CPPFLAGS += -DBCH8_ECC +endif + # Enable garbage collection of un-used sections for SPL ifeq ($(CONFIG_SPL_BUILD),y) CPPFLAGS += -ffunction-sections -fdata-sections @@ -240,8 +246,9 @@ CPPFLAGS += -DCONFIG_SPL_BUILD ifeq ($(CONFIG_TPL_BUILD),y) CPPFLAGS += -DCONFIG_TPL_BUILD endif + ifeq ($(CONFIG_SPL_BOOT_DEVICE),uart) -CPPFLAGS += -DSPL_BOOT_DEVICE_UART +CPPFLAGS += -DSPL_BOOT_DEVICE_UART endif endif diff --git a/include/configs/omap3_h1.h b/include/configs/omap3_h1.h index 037c1c344..e32af6690 100644 --- a/include/configs/omap3_h1.h +++ b/include/configs/omap3_h1.h @@ -319,6 +319,9 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SPL_YMODEM_SUPPORT +/* --------------------------------------------------------------------------- */ +/* NAND flash settings */ + /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 @@ -326,25 +329,30 @@ #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + +#ifdef BCH8_ECC #define CONFIG_SYS_NAND_ECCPOS {12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, \ 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, \ 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, \ 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63} - -/* #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13} */ - -#define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 13 - -/* #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW */ -/* #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH_CODE_SW */ - #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW #define CONFIG_BCH +#else /* NOT BCH8_ECC - so, 1-bit HW_ECC */ + +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW + +#endif /* BCH8_ECC */ + +#define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +/* --------------------------------------------------------------------------- */ + /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM * 64 bytes before this address should be set aside for u-boot.img's |