diff options
| -rw-r--r-- | arch/arm/cpu/armv7/cache_v7.c | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 | ||||
| -rw-r--r-- | arch/arm/include/asm/system.h | 14 | ||||
| -rw-r--r-- | arch/arm/lib/cache-cp15.c | 7 |
4 files changed, 59 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 5f6d0396f..8748c145c 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -340,6 +340,9 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop) { } +void arm_init_domains(void) +{ +} #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 05ff2e868..70d16a816 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -34,6 +34,12 @@ #include <asm/emif.h> #include <asm/omap_common.h> #include <linux/compiler.h> +#include <asm/cache.h> +#include <asm/system.h> + +#define ARMV7_DCACHE_WRITEBACK 0xe +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0) DECLARE_GLOBAL_DATA_PTR; @@ -269,4 +275,33 @@ void enable_caches(void) /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } + +void dram_bank_mmu_setup(int bank) +{ + bd_t *bd = gd->bd; + int i; + + u32 start = bd->bi_dram[bank].start >> 20; + u32 size = bd->bi_dram[bank].size >> 20; + u32 end = start + size; + + debug("%s: bank: %d\n", __func__, bank); + for (i = start; i < end; i++) + set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); + +} + +void arm_init_domains(void) +{ + u32 reg; + + reg = get_dacr(); + /* + * Set DOMAIN to client access so that all permissions + * set in pagetables are validated by the mmu. + */ + reg &= ~ARMV7_DOMAIN_MASK; + reg |= ARMV7_DOMAIN_CLIENT; + set_dacr(reg); +} #endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 1918492ea..760345f84 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -81,6 +81,20 @@ static inline void set_cr(unsigned int val) isb(); } +static inline unsigned int get_dacr(void) +{ + unsigned int val; + asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); + return val; +} + +static inline void set_dacr(unsigned int val) +{ + asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" + : : "r" (val) : "cc"); + isb(); +} + /* options available for data cache on each page */ enum dcache_option { DCACHE_OFF = 0x12, diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 6ecbedfed..4abe1cf06 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -36,6 +36,10 @@ void __arm_init_before_mmu(void) void arm_init_before_mmu(void) __attribute__((weak, alias("__arm_init_before_mmu"))); +__weak void arm_init_domains(void) +{ +} + static void cp_delay (void) { volatile int i; @@ -117,6 +121,9 @@ static inline void mmu_setup(void) /* Set the access control to all-supervisor */ asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (~0)); + + arm_init_domains(); + /* and enable the mmu */ reg = get_cr(); /* get control reg. */ cp_delay(); |