diff options
105 files changed, 2592 insertions, 5770 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 5e3a3faaf..785fccf56 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -117,7 +117,6 @@ Wolfgang Denk <wd@denx.de> c2mon MPC855 hermes MPC860 lwmon MPC823 - pcu_e MPC855 CU824 MPC8240 Sandpoint8240 MPC8240 @@ -208,8 +207,6 @@ Wolfgang Grandegger <wg@denx.de> ipek01 MPC5200 - CCM MPC855 - PN62 MPC8240 IPHASE4539 MPC8260 SCM MPC8260 @@ -551,6 +548,7 @@ Stefano Babic <sbabic@denx.de> polaris xscale trizepsiv xscale mx51evk i.MX51 + vision2 i.MX51 Dirk Behme <dirk.behme@gmail.com> @@ -1781,7 +1781,7 @@ The following options need to be configured: ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL, HERMES, IP860, RPXlite, LWMON, LANTEC, - PCU_E, FLAGADM, TQM8260 + FLAGADM, TQM8260 - Error Recovery: CONFIG_PANIC_HANG diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index ae20299db..7743fefdb 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -27,6 +27,7 @@ LIB = $(obj)lib$(CPU).a START := start.o COBJS := cpu.o +COBJS += syslib.o SRCS := $(START:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) @@ -44,4 +45,4 @@ include $(SRCTREE)/rules.mk sinclude $(obj).depend -#########################################################################
\ No newline at end of file +######################################################################### diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index caee7263b..aedea7b95 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -28,7 +28,6 @@ LIB = $(obj)libomap-common.a SOBJS := reset.o COBJS := timer.o -COBJS += syslib.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/arm/cpu/armv7/omap-common/syslib.c b/arch/arm/cpu/armv7/syslib.c index f9ed9a307..f9ed9a307 100644 --- a/arch/arm/cpu/armv7/omap-common/syslib.c +++ b/arch/arm/cpu/armv7/syslib.c diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h b/arch/arm/include/asm/arch-mx31/mx31-regs.h index d72585c8a..f05e743d7 100644 --- a/arch/arm/include/asm/arch-mx31/mx31-regs.h +++ b/arch/arm/include/asm/arch-mx31/mx31-regs.h @@ -57,6 +57,14 @@ struct clock_control_regs { u32 pdr2; }; +/* GPIO Registers */ +struct gpio_regs { + u32 gpio_dr; + u32 gpio_dir; + u32 gpio_psr; +}; + + /* Bit definitions for RCSR register in CCM */ #define CCM_RCSR_NF16B (1 << 31) #define CCM_RCSR_NFMS (1 << 30) @@ -153,9 +161,9 @@ struct clock_control_regs { /* * GPIO */ -#define GPIO1_BASE 0x53FCC000 -#define GPIO2_BASE 0x53FD0000 -#define GPIO3_BASE 0x53FA4000 +#define GPIO1_BASE_ADDR 0x53FCC000 +#define GPIO2_BASE_ADDR 0x53FD0000 +#define GPIO3_BASE_ADDR 0x53FA4000 #define GPIO_DR 0x00000000 /* data register */ #define GPIO_GDIR 0x00000004 /* direction register */ #define GPIO_PSR 0x00000008 /* pad status register */ diff --git a/arch/arm/include/asm/arch-mx31/mx31.h b/arch/arm/include/asm/arch-mx31/mx31.h index f702d260f..5a5aa114a 100644 --- a/arch/arm/include/asm/arch-mx31/mx31.h +++ b/arch/arm/include/asm/arch-mx31/mx31.h @@ -28,31 +28,6 @@ extern u32 mx31_get_ipg_clk(void); #define imx_get_uartclk mx31_get_ipg_clk extern void mx31_gpio_mux(unsigned long mode); -enum mx31_gpio_direction { - MX31_GPIO_DIRECTION_IN, - MX31_GPIO_DIRECTION_OUT, -}; - -#ifdef CONFIG_MX31_GPIO -extern int mx31_gpio_direction(unsigned int gpio, - enum mx31_gpio_direction direction); -extern void mx31_gpio_set(unsigned int gpio, unsigned int value); -extern int mx31_gpio_get(unsigned int gpio); -#else -static inline int mx31_gpio_direction(unsigned int gpio, - enum mx31_gpio_direction direction) -{ - return 1; -} -static inline int mx31_gpio_get(unsigned int gpio) -{ - return 1; -} -static inline void mx31_gpio_set(unsigned int gpio, unsigned int value) -{ -} -#endif - void mx31_uart1_hw_init(void); void mx31_spi2_hw_init(void); diff --git a/arch/arm/include/asm/arch-mx51/imx-regs.h b/arch/arm/include/asm/arch-mx51/imx-regs.h index 3887d3cec..3ddda401f 100644 --- a/arch/arm/include/asm/arch-mx51/imx-regs.h +++ b/arch/arm/include/asm/arch-mx51/imx-regs.h @@ -23,9 +23,6 @@ #ifndef __ASM_ARCH_MXC_MX51_H__ #define __ASM_ARCH_MXC_MX51_H__ -#define __REG(x) (*((volatile u32 *)(x))) -#define __REG16(x) (*((volatile u16 *)(x))) -#define __REG8(x) (*((volatile u8 *)(x))) /* * IRAM */ @@ -207,7 +204,12 @@ #define BOARD_REV_1_0 0x0 #define BOARD_REV_2_0 0x1 -#ifndef __ASSEMBLY__ +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) struct clkctl { u32 ccr; @@ -256,6 +258,22 @@ struct weim { u32 cswcr2; }; +/* GPIO Registers */ +struct gpio_regs { + u32 gpio_dr; + u32 gpio_dir; + u32 gpio_psr; +}; + +/* System Reset Controller (SRC) */ +struct src { + u32 scr; + u32 sbmr; + u32 srsr; + u32 reserved1[2]; + u32 sisr; + u32 simr; +}; #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MXC_MX51_H__ */ diff --git a/arch/arm/include/asm/arch-mx51/mx51_pins.h b/arch/arm/include/asm/arch-mx51/mx51_pins.h index ca26f4166..b44ff252b 100644 --- a/arch/arm/include/asm/arch-mx51/mx51_pins.h +++ b/arch/arm/include/asm/arch-mx51/mx51_pins.h @@ -368,6 +368,50 @@ enum iomux_pins { MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810), MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814), MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818), + + /* The following are PADS used for drive strength */ + + MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820), + MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838), + MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890), + MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C), + MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C), + MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884), + MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C), + MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864), + MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C), + MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874), + MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878), + MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880), + MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C), + MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C), + MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4), + MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC), + MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8), + MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C), + MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0), + MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0), + MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4), + MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC), + MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C), + MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848), + MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868), + MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4), + MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8), + MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac), + MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0), + MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4), + MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8), + MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC), + MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0), + MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4), + MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8), + MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC), + MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0), + MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4), + MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8), + MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC), + MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0), }; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/arch-mx51/sys_proto.h b/arch/arm/include/asm/arch-mx51/sys_proto.h index bf500a8b3..f687503ca 100644 --- a/arch/arm/include/asm/arch-mx51/sys_proto.h +++ b/arch/arm/include/asm/arch-mx51/sys_proto.h @@ -26,5 +26,6 @@ u32 get_cpu_rev(void); #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +void sdelay(unsigned long); #endif diff --git a/arch/i386/config.mk b/arch/i386/config.mk index 4b990e04e..8743f1a66 100644 --- a/arch/i386/config.mk +++ b/arch/i386/config.mk @@ -25,4 +25,15 @@ CROSS_COMPILE ?= i386-linux- STANDALONE_LOAD_ADDR = 0x40000 +PLATFORM_CPPFLAGS += -fno-strict-aliasing +PLATFORM_CPPFLAGS += -Wstrict-prototypes +PLATFORM_CPPFLAGS += -mregparm=3 +PLATFORM_CPPFLAGS += -fomit-frame-pointer +PLATFORM_CPPFLAGS += $(call cc-option, -ffreestanding) +PLATFORM_CPPFLAGS += $(call cc-option, -fno-toplevel-reorder, $(call cc-option, -fno-unit-at-a-time)) +PLATFORM_CPPFLAGS += $(call cc-option, -fno-stack-protector) +PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2) PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ + +LDFLAGS += --cref --gc-sections +PLATFORM_RELFLAGS += -ffunction-sections diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c index bd6aced87..ae40384f0 100644 --- a/arch/i386/cpu/cpu.c +++ b/arch/i386/cpu/cpu.c @@ -37,6 +37,61 @@ #include <command.h> #include <asm/interrupt.h> +/* Constructor for a conventional segment GDT (or LDT) entry */ +/* This is a macro so it can be used in initializers */ +#define GDT_ENTRY(flags, base, limit) \ + ((((base) & 0xff000000ULL) << (56-24)) | \ + (((flags) & 0x0000f0ffULL) << 40) | \ + (((limit) & 0x000f0000ULL) << (48-16)) | \ + (((base) & 0x00ffffffULL) << 16) | \ + (((limit) & 0x0000ffffULL))) + +/* Simple and small GDT entries for booting only */ + +#define GDT_ENTRY_32BIT_CS 2 +#define GDT_ENTRY_32BIT_DS (GDT_ENTRY_32BIT_CS + 1) +#define GDT_ENTRY_16BIT_CS (GDT_ENTRY_32BIT_DS + 1) +#define GDT_ENTRY_16BIT_DS (GDT_ENTRY_16BIT_CS + 1) + +/* + * Set up the GDT + */ + +struct gdt_ptr { + u16 len; + u32 ptr; +} __attribute__((packed)); + +static void reload_gdt(void) +{ + /* There are machines which are known to not boot with the GDT + being 8-byte unaligned. Intel recommends 16 byte alignment. */ + static const u64 boot_gdt[] __attribute__((aligned(16))) = { + /* CS: code, read/execute, 4 GB, base 0 */ + [GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff), + /* DS: data, read/write, 4 GB, base 0 */ + [GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff), + /* 16-bit CS: code, read/execute, 64 kB, base 0 */ + [GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff), + /* 16-bit DS: data, read/write, 64 kB, base 0 */ + [GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff), + }; + static struct gdt_ptr gdt; + + gdt.len = sizeof(boot_gdt)-1; + gdt.ptr = (u32)&boot_gdt; + + asm volatile("lgdtl %0\n" \ + "movl $((2+1)*8), %%ecx\n" \ + "movl %%ecx, %%ds\n" \ + "movl %%ecx, %%es\n" \ + "movl %%ecx, %%fs\n" \ + "movl %%ecx, %%gs\n" \ + "movl %%ecx, %%ss" \ + : : "m" (gdt) : "ecx"); +} + + int cpu_init_f(void) { /* initialize FPU, reset EM, set MP and NE */ @@ -51,6 +106,8 @@ int cpu_init_f(void) int cpu_init_r(void) { + reload_gdt(); + /* Initialize core interrupt and exception functionality of CPU */ cpu_init_interrupts (); return 0; diff --git a/arch/i386/cpu/interrupts.c b/arch/i386/cpu/interrupts.c index 51023f3a8..e4d0868cd 100644 --- a/arch/i386/cpu/interrupts.c +++ b/arch/i386/cpu/interrupts.c @@ -104,7 +104,7 @@ static inline unsigned long get_debugreg(int regno) return val; } -void dump_regs(struct pt_regs *regs) +void dump_regs(struct irq_regs *regs) { unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; unsigned long d0, d1, d2, d3, d6, d7; @@ -225,7 +225,7 @@ int disable_interrupts(void) } /* IRQ Low-Level Service Routine */ -__isr__ irq_llsr(struct pt_regs *regs) +void irq_llsr(struct irq_regs *regs) { /* * For detailed description of each exception, refer to: @@ -234,7 +234,7 @@ __isr__ irq_llsr(struct pt_regs *regs) * Order Number: 253665-029US, November 2008 * Table 6-1. Exceptions and Interrupts */ - switch (regs->orig_eax) { + switch (regs->irq_id) { case 0x00: printf("Divide Error (Division by zero)\n"); dump_regs(regs); @@ -340,7 +340,7 @@ __isr__ irq_llsr(struct pt_regs *regs) default: /* Hardware or User IRQ */ - do_irq(regs->orig_eax); + do_irq(regs->irq_id); } } @@ -352,17 +352,30 @@ __isr__ irq_llsr(struct pt_regs *regs) * Interrupt entries are now very small (a push and a jump) but they are * now slower (all registers pushed on stack which provides complete * crash dumps in the low level handlers + * + * Interrupt Entry Point: + * - Interrupt has caused eflags, CS and EIP to be pushed + * - Interrupt Vector Handler has pushed orig_eax + * - pt_regs.esp needs to be adjusted by 40 bytes: + * 12 bytes pushed by CPU (EFLAGSF, CS, EIP) + * 4 bytes pushed by vector handler (irq_id) + * 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX) + * NOTE: Only longs are pushed on/popped off the stack! */ asm(".globl irq_common_entry\n" \ ".hidden irq_common_entry\n" \ ".type irq_common_entry, @function\n" \ "irq_common_entry:\n" \ "cld\n" \ + "pushl %ss\n" \ "pushl %gs\n" \ "pushl %fs\n" \ "pushl %es\n" \ "pushl %ds\n" \ "pushl %eax\n" \ + "movl %esp, %eax\n" \ + "addl $40, %eax\n" \ + "pushl %eax\n" \ "pushl %ebp\n" \ "pushl %edi\n" \ "pushl %esi\n" \ @@ -370,12 +383,7 @@ asm(".globl irq_common_entry\n" \ "pushl %ecx\n" \ "pushl %ebx\n" \ "mov %esp, %eax\n" \ - "pushl %ebp\n" \ - "movl %esp,%ebp\n" \ - "pushl %eax\n" \ "call irq_llsr\n" \ - "popl %eax\n" \ - "leave\n"\ "popl %ebx\n" \ "popl %ecx\n" \ "popl %edx\n" \ @@ -383,10 +391,12 @@ asm(".globl irq_common_entry\n" \ "popl %edi\n" \ "popl %ebp\n" \ "popl %eax\n" \ + "popl %eax\n" \ "popl %ds\n" \ "popl %es\n" \ "popl %fs\n" \ "popl %gs\n" \ + "popl %ss\n" \ "add $4, %esp\n" \ "iret\n" \ DECLARE_INTERRUPT(0) \ diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 519bfd8b0..7acd471d9 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -41,7 +41,8 @@ volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000; void init_sc520(void) { - /* Set the UARTxCTL register at it's slower, + /* + * Set the UARTxCTL register at it's slower, * baud clock giving us a 1.8432 MHz reference */ writeb(0x07, &sc520_mmcr->uart1ctl); @@ -50,25 +51,30 @@ void init_sc520(void) /* first set the timer pin mapping */ writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */ - /* enable PCI bus arbitrer */ - writeb(0x02, &sc520_mmcr->sysarbctl); /* enable concurrent mode */ + /* enable PCI bus arbiter (concurrent mode) */ + writeb(0x02, &sc520_mmcr->sysarbctl); - writeb(0x1f, &sc520_mmcr->sysarbmenb); /* enable external grants */ - writeb(0x04, &sc520_mmcr->hbctl); /* enable posted-writes */ + /* enable external grants */ + writeb(0x1f, &sc520_mmcr->sysarbmenb); + + /* enable posted-writes */ + writeb(0x04, &sc520_mmcr->hbctl); if (CONFIG_SYS_SC520_HIGH_SPEED) { - writeb(0x02, &sc520_mmcr->cpuctl); /* set it to 133 MHz and write back */ + /* set it to 133 MHz and write back */ + writeb(0x02, &sc520_mmcr->cpuctl); gd->cpu_clk = 133000000; printf("## CPU Speed set to 133MHz\n"); } else { - writeb(0x01, &sc520_mmcr->cpuctl); /* set it to 100 MHz and write back */ + /* set it to 100 MHz and write back */ + writeb(0x01, &sc520_mmcr->cpuctl); printf("## CPU Speed set to 100MHz\n"); gd->cpu_clk = 100000000; } /* wait at least one millisecond */ - asm("movl $0x2000,%%ecx\n" + asm("movl $0x2000, %%ecx\n" "0: pushl %%ecx\n" "popl %%ecx\n" "loop 0b\n": : : "ecx"); @@ -107,15 +113,15 @@ unsigned long init_sc520_dram(void) /* set SDRAM speed here */ - refresh_rate/=78; - if (refresh_rate<=1) { - val = 0; /* 7.8us */ - } else if (refresh_rate==2) { - val = 1; /* 15.6us */ - } else if (refresh_rate==3 || refresh_rate==4) { - val = 2; /* 31.2us */ + refresh_rate /= 78; + if (refresh_rate <= 1) { + val = 0; /* 7.8us */ + } else if (refresh_rate == 2) { + val = 1; /* 15.6us */ + } else if (refresh_rate == 3 || refresh_rate == 4) { + val = 2; /* 31.2us */ } else { - val = 3; /* 62.4us */ + val = 3; /* 62.4us */ } tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4); @@ -124,9 +130,9 @@ unsigned long init_sc520_dram(void) val = readb(&sc520_mmcr->drctmctl) & 0xf0; if (cas_precharge_delay==3) { - val |= 0x04; /* 3T */ + val |= 0x04; /* 3T */ } else if (cas_precharge_delay==4) { - val |= 0x08; /* 4T */ + val |= 0x08; /* 4T */ } else if (cas_precharge_delay>4) { val |= 0x0c; } @@ -139,8 +145,10 @@ unsigned long init_sc520_dram(void) writeb(val, &c520_mmcr->drctmctl); #endif - /* We read-back the configuration of the dram - * controller that the assembly code wrote */ + /* + * We read-back the configuration of the dram + * controller that the assembly code wrote + */ dram_ctrl = readl(&sc520_mmcr->drcbendadr); bd->bi_dram[0].start = 0; @@ -148,7 +156,6 @@ unsigned long init_sc520_dram(void) /* bank 0 enabled */ dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22; bd->bi_dram[0].size = bd->bi_dram[1].start; - } else { bd->bi_dram[0].size = 0; bd->bi_dram[1].start = bd->bi_dram[0].start; @@ -179,11 +186,6 @@ unsigned long init_sc520_dram(void) } else { bd->bi_dram[3].size = 0; } - - -#if 0 - printf("Configured %d bytes of dram\n", dram_present); -#endif gd->ram_size = dram_present; return dram_present; diff --git a/arch/i386/cpu/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S index fff56c00b..63c14b7eb 100644 --- a/arch/i386/cpu/sc520/sc520_asm.S +++ b/arch/i386/cpu/sc520/sc520_asm.S @@ -172,396 +172,373 @@ .equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */ .equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */ - - /* - * initialize dram controller registers - */ .globl mem_init mem_init: - xorw %ax,%ax - movl $DBCTL, %edi - movb %al, (%edi) /* disable write buffer */ + /* Preserve Boot Flags */ + movl %ebx, %ebp - movl $ECCCTL, %edi - movb %al, (%edi) /* disable ECC */ + /* initialize dram controller registers */ + xorw %ax, %ax + movl $DBCTL, %edi + movb %al, (%edi) /* disable write buffer */ - movl $DRCTMCTL, %edi - movb $0x1E,%al /* Set SDRAM timing for slowest */ - movb %al, (%edi) + movl $ECCCTL, %edi + movb %al, (%edi) /* disable ECC */ - /* - * setup loop to do 4 external banks starting with bank 3 - */ - movl $0xff000000,%eax /* enable last bank and setup */ - movl $DRCBENDADR, %edi /* ending address register */ - movl %eax, (%edi) + movl $DRCTMCTL, %edi + movb $0x1e, %al /* Set SDRAM timing for slowest */ + movb %al, (%edi) - movl $DRCCFG, %edi /* setup */ - movw $0xbbbb,%ax /* dram config register for */ - movw %ax, (%edi) + /* setup loop to do 4 external banks starting with bank 3 */ + movl $0xff000000, %eax /* enable last bank and setup */ + movl $DRCBENDADR, %edi /* ending address register */ + movl %eax, (%edi) - /* - * issue a NOP to all DRAMs - */ - movl $DRCCTL, %edi /* setup DRAM control register with */ - movb $0x1,%al /* Disable refresh,disable write buffer */ - movb %al, (%edi) - movl $CACHELINESZ, %esi /* just a dummy address to write for */ - movw %ax, (%esi) - /* - * delay for 100 usec? 200? - * ******this is a cludge for now ************* - */ - movw $100,%cx + movl $DRCCFG, %edi /* setup */ + movw $0xbbbb, %ax /* dram config register for */ + movw %ax, (%edi) + + /* issue a NOP to all DRAMs */ + movl $DRCCTL, %edi /* setup DRAM control register with */ + movb $0x01, %al /* Disable refresh,disable write buffer */ + movb %al, (%edi) + movl $CACHELINESZ, %esi /* just a dummy address to write for */ + movw %ax, (%esi) + + /* delay for 100 usec? */ + movw $100, %cx sizdelay: - loop sizdelay /* we need 100 usec here */ - /***********************************************/ + loop sizdelay - /* - * issue all banks precharge - */ - movb $0x2,%al /* All banks precharge */ - movb %al, (%edi) - movw %ax, (%esi) + /* issue all banks precharge */ + movb $0x02, %al + movb %al, (%edi) + movw %ax, (%esi) - /* - * issue 2 auto refreshes to all banks - */ - movb $0x4,%al /* Auto refresh cmd */ - movb %al, (%edi) - movw $2,%cx + /* issue 2 auto refreshes to all banks */ + movb $0x04, %al /* Auto refresh cmd */ + movb %al, (%edi) + movw $0x02, %cx refresh1: - movw %ax, (%esi) - loop refresh1 + movw %ax, (%esi) + loop refresh1 - /* - * issue LOAD MODE REGISTER command - */ - movb $0x3,%al /* Load mode register cmd */ - movb %al, (%edi) - movw %ax, (%esi) + /* issue LOAD MODE REGISTER command */ + movb $0x03, %al /* Load mode register cmd */ + movb %al, (%edi) + movw %ax, (%esi) - /* - * issue 8 more auto refreshes to all banks - */ - movb $0x4,%al /* Auto refresh cmd */ - movb %al, (%edi) - movw $8,%cx + /* issue 8 more auto refreshes to all banks */ + movb $0x04, %al /* Auto refresh cmd */ + movb %al, (%edi) + movw $0x0008, %cx refresh2: - movw %ax, (%esi) - loop refresh2 + movw %ax, (%esi) + loop refresh2 - /* - * set control register to NORMAL mode - */ - movb $0x0,%al /* Normal mode value */ - movb %al, (%edi) + /* set control register to NORMAL mode */ + movb $0x00, %al /* Normal mode value */ + movb %al, (%edi) - /* - * size dram starting with external bank 3 moving to external bank 0 - */ - movl $0x3,%ecx /* start with external bank 3 */ + /* + * size dram starting with external bank 3 + * moving to external bank 0 + */ + movl $0x3, %ecx /* start with external bank 3 */ nextbank: - /* - * write col 11 wrap adr - */ - movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ - movl $COL11_DATA, %eax /* pattern for max supported columns(11) */ - movl %eax, (%esi) /* write max col pattern at max col adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write col 10 wrap adr - */ + /* write col 11 wrap adr */ + movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ + movl $COL11_DATA, %eax /* pattern for max supported columns(11) */ + movl %eax, (%esi) /* write max col pattern at max col adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ - movl $COL10_ADR, %esi /* set address to 10 col wrap address */ - movl $COL10_DATA, %eax /* pattern for 10 col wrap */ - movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write col 9 wrap adr - */ - movl $COL09_ADR, %esi /* set address to 9 col wrap address */ - movl $COL09_DATA, %eax /* pattern for 9 col wrap */ - movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write col 8 wrap adr - */ - movl $COL08_ADR, %esi /* set address to min(8) col wrap address */ - movl $COL08_DATA, %eax /* pattern for min (8) col wrap */ - movl %eax, (%esi) /* write min col pattern @ min col adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 14 wrap adr - */ - movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */ - movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */ - movl %eax, (%esi) /* write max row pattern at max row adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 13 wrap adr - */ - movl $ROW13_ADR, %esi /* set address to 13 row wrap address */ - movl $ROW13_DATA, %eax /* pattern for 13 row wrap */ - movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 12 wrap adr - */ - movl $ROW12_ADR, %esi /* set address to 12 row wrap address */ - movl $ROW12_DATA, %eax /* pattern for 12 row wrap */ - movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 11 wrap adr - */ - movl $ROW11_ADR, %edi /* set address to 11 row wrap address */ - movl $ROW11_DATA, %eax /* pattern for 11 row wrap */ - movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */ - movl (%edi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 10 wrap adr --- this write is really to determine number of banks - */ - movl $ROW10_ADR, %edi /* set address to 10 row wrap address */ - movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */ - movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */ - movl (%edi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * read data @ row 12 wrap adr to determine * banks, - * and read data @ row 14 wrap adr to determine * rows. - * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM. - * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4 - * if data @ row 12 wrap == 11 or 12, we have 4 banks, - */ - xorw %di,%di /* value for 2 banks in DI */ - movl (%esi), %ebx /* read from 12 row wrap to check banks - * (esi is setup from the write to row 12 wrap) */ - cmpl %ebx,%eax /* check for AA pattern (eax holds the aa pattern) */ - jz only2 /* if pattern == AA, we only have 2 banks */ + /* write col 10 wrap adr */ + movl $COL10_ADR, %esi /* set address to 10 col wrap address */ + movl $COL10_DATA, %eax /* pattern for 10 col wrap */ + movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* write col 9 wrap adr */ + movl $COL09_ADR, %esi /* set address to 9 col wrap address */ + movl $COL09_DATA, %eax /* pattern for 9 col wrap */ + movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* write col 8 wrap adr */ + movl $COL08_ADR, %esi /* set address to min(8) col wrap address */ + movl $COL08_DATA, %eax /* pattern for min (8) col wrap */ + movl %eax, (%esi) /* write min col pattern @ min col adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* write row 14 wrap adr */ + movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */ + movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */ + movl %eax, (%esi) /* write max row pattern at max row adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* write row 13 wrap adr */ + movl $ROW13_ADR, %esi /* set address to 13 row wrap address */ + movl $ROW13_DATA, %eax /* pattern for 13 row wrap */ + movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* write row 12 wrap adr */ + movl $ROW12_ADR, %esi /* set address to 12 row wrap address */ + movl $ROW12_DATA, %eax /* pattern for 12 row wrap */ + movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* write row 11 wrap adr */ + movl $ROW11_ADR, %edi /* set address to 11 row wrap address */ + movl $ROW11_DATA, %eax /* pattern for 11 row wrap */ + movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */ + movl (%edi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* + * write row 10 wrap adr --- this write is really to determine + * number of banks + */ + movl $ROW10_ADR, %edi /* set address to 10 row wrap address */ + movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */ + movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */ + movl (%edi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* + * read data @ row 12 wrap adr to determine * banks, + * and read data @ row 14 wrap adr to determine * rows. + * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM. + * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4 + * if data @ row 12 wrap == 11 or 12, we have 4 banks, + */ + xorw %di, %di /* value for 2 banks in DI */ + movl (%esi), %ebx /* read from 12 row wrap to check banks */ + /* (esi is setup from the write to row 12 wrap) */ + cmpl %ebx, %eax /* check for AA pattern (eax holds the aa pattern) */ + jz only2 /* if pattern == AA, we only have 2 banks */ /* 4 banks */ - movw $8,%di /* value for 4 banks in DI (BNK_CNT bit) */ - cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */ - jz only2 - cmpl $ROW12_DATA, %ebx /* and 12 */ - jnz bad_ram /* its bad if not 11 or 12! */ + movw $0x008, %di /* value for 4 banks in DI (BNK_CNT bit) */ + cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */ + jz only2 + cmpl $ROW12_DATA, %ebx /* and 12 */ + jnz bad_ram /* its bad if not 11 or 12! */ /* fall through */ only2: /* * validate row mask */ - movl $ROW14_ADR, %esi /* set address back to max row wrap addr */ - movl (%esi), %eax /* read actual number of rows @ row14 adr */ + movl $ROW14_ADR, %esi /* set address back to max row wrap addr */ + movl (%esi), %eax /* read actual number of rows @ row14 adr */ - cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */ - jb bad_ram + cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */ + jb bad_ram - cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */ - ja bad_ram + cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */ + ja bad_ram - cmpb %ah,%al /* verify all 4 bytes of dword same */ - jnz bad_ram - movl %eax,%ebx - shrl $16,%ebx - cmpw %bx,%ax - jnz bad_ram - /* - * read col 11 wrap adr for real column data value - */ - movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ - movl (%esi), %eax /* read real col number at max col adr */ - /* - * validate column data - */ - cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */ - jb bad_ram + cmpb %ah, %al /* verify all 4 bytes of dword same */ + jnz bad_ram + movl %eax, %ebx + shrl $16, %ebx + cmpw %bx, %ax + jnz bad_ram - cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */ - ja bad_ram + /* + * read col 11 wrap adr for real column data value + */ + movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ + movl (%esi), %eax /* read real col number at max col adr */ + + /* + * validate column data + */ + cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */ + jb bad_ram + + cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */ + ja bad_ram + + subl $COL08_DATA, %eax /* normalize column data to zero */ + jc bad_ram + cmpb %ah, %al /* verify all 4 bytes of dword equal */ + jnz bad_ram + movl %eax, %edx + shrl $16, %edx + cmpw %dx, %ax + jnz bad_ram + + /* + * merge bank and col data together + */ + addw %di, %dx /* merge of bank and col info in dl */ + + /* + * fix ending addr mask based upon col info + */ + movb $0x03, %al + subb %dh, %al /* dh contains the overflow from the bank/col merge */ + movb %bl, %dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */ + xchgw %cx, %ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */ + shrb %cl, %dh + incb %dh /* ending addr is 1 greater than real end */ + xchgw %cx, %ax /* cx is bank number again */ - subl $COL08_DATA, %eax /* normalize column data to zero */ - jc bad_ram - cmpb %ah,%al /* verify all 4 bytes of dword equal */ - jnz bad_ram - movl %eax,%edx - shrl $16,%edx - cmpw %dx,%ax - jnz bad_ram - /* - * merge bank and col data together - */ - addw %di,%dx /* merge of bank and col info in dl */ - /* - * fix ending addr mask based upon col info - */ - movb $3,%al - subb %dh,%al /* dh contains the overflow from the bank/col merge */ - movb %bl,%dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */ - xchgw %cx,%ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */ - shrb %cl,%dh /* */ - incb %dh /* ending addr is 1 greater than real end */ - xchgw %cx,%ax /* cx is bank number again */ - /* - * issue all banks precharge - */ bad_reint: - movl $DRCCTL, %esi /* setup DRAM control register with */ - movb $0x2,%al /* All banks precharge */ - movb %al, (%esi) - movl $CACHELINESZ, %esi /* address to init read buffer */ - movw %ax, (%esi) + /* + * issue all banks precharge + */ + movl $DRCCTL, %esi /* setup DRAM control register with */ + movb $0x02, %al /* All banks precharge */ + movb %al, (%esi) + movl $CACHELINESZ, %esi /* address to init read buffer */ + movw %ax, (%esi) - /* - * update ENDING ADDRESS REGISTER - */ - movl $DRCBENDADR, %edi /* DRAM ending address register */ - movl %ecx,%ebx + /* + * update ENDING ADDRESS REGISTER + */ + movl $DRCBENDADR, %edi /* DRAM ending address register */ + movl %ecx, %ebx addl %ebx, %edi - movb %dh, (%edi) - /* - * update CONFIG REGISTER - */ - xorb %dh,%dh - movw $0x00f,%bx - movw %cx,%ax - shlw $2,%ax - xchgw %cx,%ax - shlw %cl,%dx - shlw %cl,%bx - notw %bx - xchgw %cx,%ax - movl $DRCCFG, %edi - mov (%edi), %ax - andw %bx,%ax - orw %dx,%ax - movw %ax, (%edi) - jcxz cleanup + movb %dh, (%edi) + + /* + * update CONFIG REGISTER + */ + xorb %dh, %dh + movw $0x000f, %bx + movw %cx, %ax + shlw $2, %ax + xchgw %cx, %ax + shlw %cl, %dx + shlw %cl, %bx + notw %bx + xchgw %cx, %ax + movl $DRCCFG, %edi + movw (%edi), %ax + andw %bx, %ax + orw %dx, %ax + movw %ax, (%edi) + jcxz cleanup - decw %cx - movl %ecx,%ebx - movl $DRCBENDADR, %edi /* DRAM ending address register */ - movb $0xff,%al + decw %cx + movl %ecx, %ebx + movl $DRCBENDADR, %edi /* DRAM ending address register */ + movb $0xff, %al addl %ebx, %edi - movb %al, (%edi) - /* - * set control register to NORMAL mode - */ - movl $DRCCTL, %esi /* setup DRAM control register with */ - movb $0x0,%al /* Normal mode value */ - movb %al, (%esi) - movl $CACHELINESZ, %esi /* address to init read buffer */ - movw %ax, (%esi) - jmp nextbank + movb %al, (%edi) + + /* + * set control register to NORMAL mode + */ + movl $DRCCTL, %esi /* setup DRAM control register with */ + movb $0x00, %al /* Normal mode value */ + movb %al, (%esi) + movl $CACHELINESZ, %esi /* address to init read buffer */ + movw %ax, (%esi) + jmp nextbank cleanup: - movl $DRCBENDADR, %edi /* DRAM ending address register */ - movw $4,%cx - xorw %ax,%ax + movl $DRCBENDADR, %edi /* DRAM ending address register */ + movw $0x04, %cx + xorw %ax, %ax cleanuplp: - movb (%edi), %al - orb %al,%al - jz emptybank + movb (%edi), %al + orb %al, %al + jz emptybank - addb %ah,%al - jns nottoomuch + addb %ah, %al + jns nottoomuch - movb $0x7f,%al + movb $0x7f, %al nottoomuch: - movb %al,%ah - orb $0x80,%al - movb %al, (%edi) + movb %al, %ah + orb $0x80, %al + movb %al, (%edi) emptybank: - incl %edi - loop cleanuplp + incl %edi + loop cleanuplp #if defined CONFIG_SYS_SDRAM_DRCTMCTL /* just have your hardware desinger _GIVE_ you what you need here! */ - movl $DRCTMCTL, %edi - movb $CONFIG_SYS_SDRAM_DRCTMCTL,%al - movb %al, (%edi) + movl $DRCTMCTL, %edi + movb $CONFIG_SYS_SDRAM_DRCTMCTL, %al + movb %al, (%edi) #else #if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T) - /* set the CAS latency now since it is hard to do - * when we run from the RAM */ - movl $DRCTMCTL, %edi /* DRAM timing register */ - movb (%edi), %al + /* + * Set the CAS latency now since it is hard to do + * when we run from the RAM + */ + movl $DRCTMCTL, %edi /* DRAM timing register */ + movb (%edi), %al #ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T - andb $0xef, %al + andb $0xef, %al #endif #ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T - orb $0x10, %al + orb $0x10, %al #endif - movb %al, (%edi) + movb %al, (%edi) #endif #endif - movl $DRCCTL, %edi /* DRAM Control register */ - movb $0x3,%al /* Load mode register cmd */ - movb %al, (%edi) - movw %ax, (%esi) + movl $DRCCTL, %edi /* DRAM Control register */ + movb $0x03, %al /* Load mode register cmd */ + movb %al, (%edi) + movw %ax, (%esi) - movl $DRCCTL, %edi /* DRAM Control register */ - movb $0x18,%al /* Enable refresh and NORMAL mode */ - movb %al, (%edi) + movl $DRCCTL, %edi /* DRAM Control register */ + movb $0x18, %al /* Enable refresh and NORMAL mode */ + movb %al, (%edi) - jmp dram_done + jmp dram_done bad_ram: - xorl %edx,%edx - xorl %edi,%edi - jmp bad_reint + xorl %edx, %edx + xorl %edi, %edi + jmp bad_reint dram_done: + /* Restore Boot Flags */ + movl %ebx, %ebp + jmp mem_init_ret #if CONFIG_SYS_SDRAM_ECC_ENABLE - /* - * We are in the middle of an existing 'call' - Need to store the - * existing return address before making another 'call' - */ - movl %ebp, %ebx - - /* Get the memory size */ - movl $init_ecc, %ebp - jmpl get_mem_size - +.globl init_ecc init_ecc: - /* Restore the orignal return address */ - movl %ebx, %ebp - /* A nominal memory test: just a byte at each address line */ - movl %eax, %ecx - shrl $0x1, %ecx + movl %eax, %ecx + shrl $0x1, %ecx movl $0x1, %edi memtest0: movb $0xa5, (%edi) - cmpb $0xa5, (%edi) + cmpb $0xa5, (%edi) jne out - shrl $1, %ecx - andl %ecx,%ecx + shrl $0x1, %ecx + andl %ecx, %ecx jz set_ecc - shll $1, %edi + shll $0x1, %edi jmp memtest0 set_ecc: @@ -570,25 +547,28 @@ set_ecc: xorl %esi, %esi xorl %edi, %edi xorl %eax, %eax - shrl $2, %ecx + shrl $0x2, %ecx cld rep stosl - /* enable read, write buffers */ - movb $0x11, %al - movl $DBCTL, %edi - movb %al, (%edi) - /* enable NMI mapping for ECC */ - movl $ECCINT, %edi - mov $0x10, %al - movb %al, (%edi) - /* Turn on ECC */ - movl $ECCCTL, %edi - mov $0x05, %al - movb %al, (%edi) -#endif + + /* enable read, write buffers */ + movb $0x11, %al + movl $DBCTL, %edi + movb %al, (%edi) + + /* enable NMI mapping for ECC */ + movl $ECCINT, %edi + movb $0x10, %al + movb %al, (%edi) + + /* Turn on ECC */ + movl $ECCCTL, %edi + movb $0x05, %al + movb %al,(%edi) out: - jmp *%ebp + jmp init_ecc_ret +#endif /* * Read and decode the sc520 DRCBENDADR MMCR and return the number of @@ -596,7 +576,7 @@ out: */ .globl get_mem_size get_mem_size: - movl $DRCBENDADR, %edi /* DRAM ending address register */ + movl $DRCBENDADR, %edi /* DRAM ending address register */ bank0: movl (%edi), %eax movl %eax, %ecx @@ -604,7 +584,7 @@ bank0: movl (%edi), %eax jz bank1 andl $0x0000007f, %eax shll $22, %eax - movl %eax, %ebx + movl %eax, %edx bank1: movl (%edi), %eax movl %eax, %ecx @@ -612,7 +592,7 @@ bank1: movl (%edi), %eax jz bank2 andl $0x00007f00, %eax shll $14, %eax - movl %eax, %ebx + movl %eax, %edx bank2: movl (%edi), %eax movl %eax, %ecx @@ -620,7 +600,7 @@ bank2: movl (%edi), %eax jz bank3 andl $0x007f0000, %eax shll $6, %eax - movl %eax, %ebx + movl %eax, %edx bank3: movl (%edi), %eax movl %eax, %ecx @@ -628,8 +608,8 @@ bank3: movl (%edi), %eax jz done andl $0x7f000000, %eax shrl $2, %eax - movl %eax, %ebx + movl %eax, %edx done: - movl %ebx, %eax - jmp *%ebp + movl %edx, %eax + jmp get_mem_size_ret diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 7def8def8..829468fe7 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -1,7 +1,7 @@ /* * U-boot - i386 Startup Code * - * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström <denaiel@omicron.se> + * Copyright (c) 2002 Omicron Ceti AB, Daniel Engstr�m <denaiel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. @@ -25,6 +25,7 @@ #include <config.h> #include <version.h> +#include <asm/global_data.h> .section .text @@ -45,175 +46,98 @@ _i386boot_start: /* Turn of cache (this might require a 486-class CPU) */ movl %cr0, %eax - orl $0x60000000,%eax + orl $0x60000000, %eax movl %eax, %cr0 wbinvd /* Tell 32-bit code it is being entered from an in-RAM copy */ - movw $0x0000, %bx + movw $GD_FLG_WARM_BOOT, %bx _start: /* This is the 32-bit cold-reset entry point */ - movl $0x18,%eax /* Load our segement registes, the + movl $0x18, %eax /* Load our segement registes, the * gdt have already been loaded by start16.S */ - movw %ax,%fs - movw %ax,%ds - movw %ax,%gs - movw %ax,%es - movw %ax,%ss + movw %ax, %fs + movw %ax, %ds + movw %ax, %gs + movw %ax, %es + movw %ax, %ss /* Clear the interupt vectors */ lidt blank_idt_ptr - /* - * Skip low-level board and memory initialization if not starting - * from cold-reset. This allows us to do a fail safe boot-strap - * into a new build of U-Boot from a known-good boot flash - */ - movw $0x0001, %ax - cmpw %ax, %bx - jne mem_init_ret - - /* We call a few functions in the board support package - * since we have no stack yet we'll have to use %ebp - * to store the return address */ + /* Skip low-level initialization if not starting from cold-reset */ + movl %ebx, %ecx + andl $GD_FLG_COLD_BOOT, %ecx + jz skip_mem_init /* Early platform init (setup gpio, etc ) */ - mov $early_board_init_ret, %ebp jmp early_board_init +.globl early_board_init_ret early_board_init_ret: - /* The __port80 entry-point should be usabe by now */ - /* so we try to indicate progress */ - movw $0x01, %ax - movl $.progress0, %ebp - jmp show_boot_progress_asm -.progress0: - /* size memory */ - mov $mem_init_ret, %ebp - jmp mem_init + jmp mem_init +.globl mem_init_ret mem_init_ret: +skip_mem_init: /* fetch memory size (into %eax) */ - mov $get_mem_size_ret, %ebp - jmp get_mem_size + jmp get_mem_size +.globl get_mem_size_ret get_mem_size_ret: - /* - * We are now in 'Flat Protected Mode' and we know how much memory - * the board has. The (temporary) Global Descriptor Table is not - * in a 'Safe' place (it is either in Flash which can be erased or - * reprogrammed or in a fail-safe boot-strap image which could be - * over-written). - * - * Move the final gdt to a safe place (top of RAM) and load it. - * This is not a trivial excercise - the lgdt instruction does not - * have a register operand (memory only) and we may well be - * running from Flash, so self modifying code will not work here. - * To overcome this, we copy a stub into upper memory along with - * the GDT. - */ +#if CONFIG_SYS_SDRAM_ECC_ENABLE + /* Skip ECC initialization if not starting from cold-reset */ + movl %ebx, %ecx + andl $GD_FLG_COLD_BOOT, %ecx + jz init_ecc_ret + jmp init_ecc - /* Reduce upper memory limit by (Stub + GDT Pointer + GDT) */ - subl $(end_gdt_setup - start_gdt_setup), %eax - - /* Copy the GDT and Stub */ - movl $start_gdt_setup, %esi - movl %eax, %edi - movl $(end_gdt_setup - start_gdt_setup), %ecx - shrl $2, %ecx - cld - rep movsl +.globl init_ecc_ret +init_ecc_ret: +#endif - /* write the lgdt 'parameter' */ - subl $(jmp_instr - start_gdt_setup - 4), %ebp - addl %eax, %ebp - movl $(gdt_ptr - start_gdt_setup), %ebx - addl %eax, %ebx - movl %ebx, (%ebp) - - /* write the gdt address into the pointer */ - movl $(gdt_addr - start_gdt_setup), %ebp - addl %eax, %ebp - movl $(gdt - start_gdt_setup), %ebx - addl %eax, %ebx - movl %ebx, (%ebp) - - /* Save the return address */ - movl $load_gdt_ret, %ebp - - /* Load the new (safe) Global Descriptor Table */ - jmp *%eax - -load_gdt_ret: /* Check we have enough memory for stack */ movl $CONFIG_SYS_STACK_SIZE, %ecx cmpl %ecx, %eax - jae mem_ok - - /* indicate (lack of) progress */ - movw $0x81, %ax - movl $.progress0a, %ebp - jmp show_boot_progress_asm -.progress0a: - jmp die + jb die mem_ok: /* Set stack pointer to upper memory limit*/ - movl %eax, %esp - - /* indicate progress */ - movw $0x02, %ax - movl $.progress1, %ebp - jmp show_boot_progress_asm -.progress1: + movl %eax, %esp /* Test the stack */ pushl $0 - popl %eax - cmpl $0, %eax - jne no_stack + popl %ecx + cmpl $0, %ecx + jne die push $0x55aa55aa - popl %ebx - cmpl $0x55aa55aa, %ebx - je stack_ok - -no_stack: - /* indicate (lack of) progress */ - movw $0x82, %ax - movl $.progress1a, %ebp - jmp show_boot_progress_asm -.progress1a: - jmp die + popl %ecx + cmpl $0x55aa55aa, %ecx + jne die + wbinvd -stack_ok: - /* indicate progress */ - movw $0x03, %ax - movl $.progress2, %ebp - jmp show_boot_progress_asm -.progress2: + /* Determine our load offset */ + call 1f +1: popl %ecx + subl $1b, %ecx - wbinvd + /* Set the upper memory limit parameter */ + subl $CONFIG_SYS_STACK_SIZE, %eax - /* Get upper memory limit */ - movl %esp, %ecx - subl $CONFIG_SYS_STACK_SIZE, %ecx + /* Reserve space for global data */ + subl $(GD_SIZE * 4), %eax - /* Create a Stack Frame */ - pushl %ebp - movl %esp, %ebp + /* %eax points to the global data structure */ + movl %esp, (GD_RAM_SIZE * 4)(%eax) + movl %ebx, (GD_FLAGS * 4)(%eax) + movl %ecx, (GD_LOAD_OFF * 4)(%eax) - /* stack_limit parameter */ - pushl %ecx call board_init_f /* Enter, U-boot! */ /* indicate (lack of) progress */ movw $0x85, %ax - movl $.progress4a, %ebp - jmp show_boot_progress_asm -.progress4a: - die: hlt jmp die hlt @@ -221,52 +145,3 @@ die: hlt blank_idt_ptr: .word 0 /* limit */ .long 0 /* base */ - -.align 4 -start_gdt_setup: - lgdt gdt_ptr -jmp_instr: - jmp *%ebp - -.align 4 -gdt_ptr: - .word 0x30 /* limit (48 bytes = 6 GDT entries) */ -gdt_addr: - .long gdt /* base */ - - /* The GDT table ... - * - * Selector Type - * 0x00 NULL - * 0x08 Unused - * 0x10 32bit code - * 0x18 32bit data/stack - * 0x20 16bit code - * 0x28 16bit data/stack - */ - -.align 4 -gdt: - .word 0, 0, 0, 0 /* NULL */ - .word 0, 0, 0, 0 /* unused */ - - .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ - .word 0 /* base address = 0 */ - .word 0x9B00 /* code read/exec */ - .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ - - .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ - .word 0x0 /* base address = 0 */ - .word 0x9300 /* data read/write */ - .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ - - .word 0xFFFF /* 64kb */ - .word 0 /* base address = 0 */ - .word 0x9b00 /* data read/write */ - .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ - - .word 0xFFFF /* 64kb */ - .word 0 /* base address = 0 */ - .word 0x9300 /* data read/write */ - .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ -end_gdt_setup: diff --git a/arch/i386/cpu/start16.S b/arch/i386/cpu/start16.S index ebe583584..0a5823d3c 100644 --- a/arch/i386/cpu/start16.S +++ b/arch/i386/cpu/start16.S @@ -22,6 +22,7 @@ * MA 02111-1307 USA */ +#include <asm/global_data.h> #define BOOT_SEG 0xffff0000 /* linear segment of boot code */ #define a32 .byte 0x67; @@ -31,16 +32,20 @@ .code16 .globl start16 start16: - /* First we let the BSP do some early initialization + /* Set the Cold Boot / Hard Reset flag */ + movl $GD_FLG_COLD_BOOT, %ebx + + /* + * First we let the BSP do some early initialization * this code have to map the flash to its final position */ - mov $board_init16_ret, %bp jmp board_init16 +.globl board_init16_ret board_init16_ret: /* Turn of cache (this might require a 486-class CPU) */ movl %cr0, %eax - orl $0x60000000,%eax + orl $0x60000000, %eax movl %eax, %cr0 wbinvd @@ -50,18 +55,15 @@ o32 cs lgdt gdt_ptr /* Now, we enter protected mode */ movl %cr0, %eax - orl $1,%eax + orl $1, %eax movl %eax, %cr0 /* Flush the prefetch queue */ jmp ff ff: - /* Tell 32-bit code it is being entered from hard-reset */ - movw $0x0001, %bx - /* Finally jump to the 32bit initialization code */ movw $code32start, %ax - movw %ax,%bp + movw %ax, %bp o32 cs ljmp *(%bp) /* 48-bit far pointer */ diff --git a/arch/i386/include/asm/config.h b/arch/i386/include/asm/config.h index 049c44eaf..1952de79f 100644 --- a/arch/i386/include/asm/config.h +++ b/arch/i386/include/asm/config.h @@ -21,4 +21,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_RELOC_FIXUP_WORKS + #endif diff --git a/arch/i386/include/asm/global_data.h b/arch/i386/include/asm/global_data.h index 3a9adc9c6..597112318 100644 --- a/arch/i386/include/asm/global_data.h +++ b/arch/i386/include/asm/global_data.h @@ -33,12 +33,15 @@ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) */ +#ifndef __ASSEMBLY__ + typedef struct { bd_t *bd; unsigned long flags; unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ unsigned long reloc_off; /* Relocation Offset */ + unsigned long load_off; /* Load Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long cpu_clk; /* CPU clock in Hz! */ @@ -49,6 +52,27 @@ typedef struct { char env_buf[32]; /* buffer for getenv() before reloc. */ } gd_t; +extern gd_t *gd; + +#endif + +/* Word Offsets into Global Data - MUST match struct gd_t */ +#define GD_BD 0 +#define GD_FLAGS 1 +#define GD_BAUDRATE 2 +#define GD_HAVE_CONSOLE 3 +#define GD_RELOC_OFF 4 +#define GD_LOAD_OFF 5 +#define GD_ENV_ADDR 6 +#define GD_ENV_VALID 7 +#define GD_CPU_CLK 8 +#define GD_BUS_CLK 9 +#define GD_RAM_SIZE 10 +#define GD_RESET_STATUS 11 +#define GD_JT 12 + +#define GD_SIZE 13 + /* * Global Data Flags */ @@ -60,8 +84,9 @@ typedef struct { #define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ #define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ +#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */ +#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */ -extern gd_t *gd; #define DECLARE_GLOBAL_DATA_PTR diff --git a/arch/i386/include/asm/interrupt.h b/arch/i386/include/asm/interrupt.h index 07426fe6a..d32ef8b19 100644 --- a/arch/i386/include/asm/interrupt.h +++ b/arch/i386/include/asm/interrupt.h @@ -27,6 +27,8 @@ #ifndef __ASM_INTERRUPT_H_ #define __ASM_INTERRUPT_H_ 1 +#include <asm/types.h> + /* arch/i386/cpu/interrupts.c */ void set_vector(u8 intnum, void *routine); @@ -41,6 +43,4 @@ void specific_eoi(int irq); extern char exception_stack[]; -#define __isr__ void __attribute__ ((regparm(0))) - #endif diff --git a/arch/i386/include/asm/ptrace.h b/arch/i386/include/asm/ptrace.h index 750e40d03..a727dbfb0 100644 --- a/arch/i386/include/asm/ptrace.h +++ b/arch/i386/include/asm/ptrace.h @@ -1,6 +1,8 @@ #ifndef _I386_PTRACE_H #define _I386_PTRACE_H +#include <asm/types.h> + #define EBX 0 #define ECX 1 #define EDX 2 @@ -43,6 +45,28 @@ struct pt_regs { int xss; } __attribute__ ((packed)); +struct irq_regs { + /* Pushed by irq_common_entry */ + long ebx; + long ecx; + long edx; + long esi; + long edi; + long ebp; + long esp; + long eax; + long xds; + long xes; + long xfs; + long xgs; + long xss; + /* Pushed by vector handler (irq_<num>) */ + long irq_id; + /* Pushed by cpu in response to interrupt */ + long eip; + long xcs; + long eflags; +} __attribute__ ((packed)); /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ #define PTRACE_GETREGS 12 diff --git a/arch/i386/lib/bios_setup.c b/arch/i386/lib/bios_setup.c index a92b77ea2..75407c173 100644 --- a/arch/i386/lib/bios_setup.c +++ b/arch/i386/lib/bios_setup.c @@ -45,8 +45,8 @@ DECLARE_GLOBAL_DATA_PTR; #define BIOS_BASE ((char*)0xf0000) #define BIOS_CS 0xf000 -extern ulong _i386boot_bios; -extern ulong _i386boot_bios_size; +extern ulong __bios_start; +extern ulong __bios_size; /* these are defined in a 16bit segment and needs * to be accessed with the RELOC_16_xxxx() macros below @@ -141,8 +141,8 @@ static void setvector(int vector, u16 segment, void *handler) int bios_setup(void) { - ulong i386boot_bios = (ulong)&_i386boot_bios + gd->reloc_off; - ulong i386boot_bios_size = (ulong)&_i386boot_bios_size; + ulong bios_start = (ulong)&__bios_start + gd->reloc_off; + ulong bios_size = (ulong)&__bios_size; static int done=0; int vector; @@ -154,13 +154,13 @@ int bios_setup(void) } done = 1; - if (i386boot_bios_size > 65536) { + if (bios_size > 65536) { printf("BIOS too large (%ld bytes, max is 65536)\n", - i386boot_bios_size); + bios_size); return -1; } - memcpy(BIOS_BASE, (void*)i386boot_bios, i386boot_bios_size); + memcpy(BIOS_BASE, (void*)bios_start, bios_size); /* clear bda */ memset(BIOS_DATA, 0, BIOS_DATA_SIZE); diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 5002203ec..1129918fe 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -48,13 +48,12 @@ DECLARE_GLOBAL_DATA_PTR; /* Exports from the Linker Script */ -extern ulong _i386boot_text_start; -extern ulong _i386boot_rel_dyn_start; -extern ulong _i386boot_rel_dyn_end; -extern ulong _i386boot_bss_start; -extern ulong _i386boot_bss_size; - -void ram_bootstrap (void *, ulong); +extern ulong __text_start; +extern ulong __data_end; +extern ulong __rel_dyn_start; +extern ulong __rel_dyn_end; +extern ulong __bss_start; +extern ulong __bss_end; const char version_string[] = U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"; @@ -164,85 +163,77 @@ init_fnc_t *init_sequence[] = { NULL, }; -static gd_t gd_data; gd_t *gd; /* * Load U-Boot into RAM, initialize BSS, perform relocation adjustments */ -void board_init_f (ulong stack_limit) +void board_init_f (ulong gdp) { - void *text_start = &_i386boot_text_start; - void *u_boot_cmd_end = &__u_boot_cmd_end; - Elf32_Rel *rel_dyn_start = (Elf32_Rel *)&_i386boot_rel_dyn_start; - Elf32_Rel *rel_dyn_end = (Elf32_Rel *)&_i386boot_rel_dyn_end; - void *bss_start = &_i386boot_bss_start; - ulong bss_size = (ulong)&_i386boot_bss_size; + void *text_start = &__text_start; + void *data_end = &__data_end; + void *rel_dyn_start = &__rel_dyn_start; + void *rel_dyn_end = &__rel_dyn_end; + void *bss_start = &__bss_start; + void *bss_end = &__bss_end; + + ulong *dst_addr; + ulong *src_addr; + ulong *end_addr; - ulong uboot_size; void *dest_addr; ulong rel_offset; - Elf32_Rel *re; - - void (*start_func)(void *, ulong); + Elf32_Rel *re_src; + Elf32_Rel *re_end; - uboot_size = (ulong)u_boot_cmd_end - (ulong)text_start; - dest_addr = (void *)stack_limit - (uboot_size + (ulong)bss_size); + /* Calculate destination RAM Address and relocation offset */ + dest_addr = (void *)gdp - (bss_end - text_start); rel_offset = text_start - dest_addr; - start_func = ram_bootstrap - rel_offset; - /* First stage CPU initialization */ - if (cpu_init_f() != 0) - hang(); + /* Perform low-level initialization only when cold booted */ + if (((gd_t *)gdp)->flags & GD_FLG_COLD_BOOT) { + /* First stage CPU initialization */ + if (cpu_init_f() != 0) + hang(); - /* First stage Board initialization */ - if (board_early_init_f() != 0) - hang(); + /* First stage Board initialization */ + if (board_early_init_f() != 0) + hang(); + } /* Copy U-Boot into RAM */ - memcpy(dest_addr, text_start, uboot_size); + dst_addr = (ulong *)dest_addr; + src_addr = (ulong *)(text_start + ((gd_t *)gdp)->load_off); + end_addr = (ulong *)(data_end + ((gd_t *)gdp)->load_off); + + while (src_addr < end_addr) + *dst_addr++ = *src_addr++; /* Clear BSS */ - memset(bss_start - rel_offset, 0, bss_size); + dst_addr = (ulong *)(bss_start - rel_offset); + end_addr = (ulong *)(bss_end - rel_offset); + + while (dst_addr < end_addr) + *dst_addr++ = 0x00000000; /* Perform relocation adjustments */ - for (re = rel_dyn_start; re < rel_dyn_end; re++) - { - if (re->r_offset >= TEXT_BASE) - if (*(ulong *)re->r_offset >= TEXT_BASE) - *(ulong *)(re->r_offset - rel_offset) -= (Elf32_Addr)rel_offset; - } + re_src = (Elf32_Rel *)(rel_dyn_start + ((gd_t *)gdp)->load_off); + re_end = (Elf32_Rel *)(rel_dyn_end + ((gd_t *)gdp)->load_off); - /* Enter the relocated U-Boot! */ - start_func(dest_addr, rel_offset); - /* NOTREACHED - board_init_f() does not return */ - while(1); -} + do { + if (re_src->r_offset >= TEXT_BASE) + if (*(Elf32_Addr *)(re_src->r_offset - rel_offset) >= TEXT_BASE) + *(Elf32_Addr *)(re_src->r_offset - rel_offset) -= rel_offset; + } while (re_src++ < re_end); -/* - * We cannot initialize gd_data in board_init_f() because we would be - * attempting to write to flash (I have even tried using manual relocation - * adjustments on pointers but it just won't work) and board_init_r() does - * not have enough arguments to allow us to pass the relocation offset - * straight up. This bootstrap function (which runs in RAM) is used to - * setup gd_data in order to pass the relocation offset to the rest of - * U-Boot. - * - * TODO: The compiler optimization barrier is intended to stop GCC from - * optimizing this function into board_init_f(). It seems to work without - * it, but I've left it in to be sure. I think also that the barrier in - * board_init_r() is no longer needed, but left it in 'just in case' - */ -void ram_bootstrap (void *dest_addr, ulong rel_offset) -{ - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); + ((gd_t *)gdp)->reloc_off = rel_offset; + ((gd_t *)gdp)->flags |= GD_FLG_RELOC; - /* tell others: relocation done */ - gd_data.reloc_off = rel_offset; - gd_data.flags |= GD_FLG_RELOC; + /* Enter the relocated U-Boot! */ + (board_init_r - rel_offset)((gd_t *)gdp, (ulong)dest_addr); - board_init_r(&gd_data, (ulong)dest_addr); + /* NOTREACHED - board_init_f() does not return */ + while(1); } void board_init_r(gd_t *id, ulong dest_addr) diff --git a/arch/i386/lib/realmode.c b/arch/i386/lib/realmode.c index b3f51230a..60fe1816a 100644 --- a/arch/i386/lib/realmode.c +++ b/arch/i386/lib/realmode.c @@ -31,23 +31,23 @@ #define REALMODE_MAILBOX ((char*)0xe00) -extern ulong _i386boot_realmode; -extern ulong _i386boot_realmode_size; +extern ulong __realmode_start; +extern ulong __realmode_size; extern char realmode_enter; int realmode_setup(void) { - ulong i386boot_realmode = (ulong)&_i386boot_realmode + gd->reloc_off; - ulong i386boot_realmode_size = (ulong)&_i386boot_realmode_size; + ulong realmode_start = (ulong)&__realmode_start + gd->reloc_off; + ulong realmode_size = (ulong)&__realmode_size; /* copy the realmode switch code */ - if (i386boot_realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) { + if (realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) { printf("realmode switch too large (%ld bytes, max is %d)\n", - i386boot_realmode_size, (REALMODE_MAILBOX-REALMODE_BASE)); + realmode_size, (REALMODE_MAILBOX-REALMODE_BASE)); return -1; } - memcpy(REALMODE_BASE, (void*)i386boot_realmode, i386boot_realmode_size); + memcpy(REALMODE_BASE, (void*)realmode_start, realmode_size); asm("wbinvd\n"); return 0; diff --git a/arch/i386/lib/zimage.c b/arch/i386/lib/zimage.c index 89fe015e6..0c4207269 100644 --- a/arch/i386/lib/zimage.c +++ b/arch/i386/lib/zimage.c @@ -248,7 +248,8 @@ void boot_zimage(void *setup_base) int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { void *base_ptr; - void *bzImage_addr; + void *bzImage_addr = NULL; + char *s; ulong bzImage_size = 0; disable_interrupts(); @@ -256,10 +257,17 @@ int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* Setup board for maximum PC/AT Compatibility */ setup_pcat_compatibility(); - /* argv[1] holds the address of the bzImage */ - bzImage_addr = (void *)simple_strtoul(argv[1], NULL, 16); + if (argc >= 2) + /* argv[1] holds the address of the bzImage */ + s = argv[1]; + else + s = getenv("fileaddr"); + + if (s) + bzImage_addr = (void *)simple_strtoul(s, NULL, 16); - if (argc == 3) + if (argc >= 3) + /* argv[2] holds the size of the bzImage */ bzImage_size = simple_strtoul(argv[2], NULL, 16); /* Lets look for*/ @@ -282,7 +290,7 @@ int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } U_BOOT_CMD( - zboot, 3, 0, do_zboot, + zboot, 2, 0, do_zboot, "Boot bzImage", "" ); diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index c29f5775b..eba2435a5 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -73,10 +73,6 @@ DECLARE_GLOBAL_DATA_PTR; static char *failed = "*** failed ***\n"; -#ifdef CONFIG_PCU_E -extern flash_info_t flash_info[]; -#endif - #include <environment.h> extern ulong __init_end; diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index a6cfaa597..df2504802 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -81,10 +81,16 @@ struct liodn_id_table fman2_liodn_tbl[] = { #endif struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JR_LIODN_ENTRY(0, 146, 154), - SET_SEC_JR_LIODN_ENTRY(1, 147, 155), - SET_SEC_JR_LIODN_ENTRY(2, 178, 186), - SET_SEC_JR_LIODN_ENTRY(3, 179, 187), + /* + * We assume currently that all JR are in the same partition + * and as such they need to represent the same LIODN due to + * a 4080 rev.2 h/w requirement that DECOs sharing from themselves + * or from another DECO have the two Non-SEQ LIODN values equal + */ + SET_SEC_JR_LIODN_ENTRY(0, 146, 154), /* (0, 146, 154), */ + SET_SEC_JR_LIODN_ENTRY(1, 146, 154), /* (1, 147, 155), */ + SET_SEC_JR_LIODN_ENTRY(2, 146, 154), /* (2, 178, 186), */ + SET_SEC_JR_LIODN_ENTRY(3, 146, 154), /* (3, 179, 187), */ SET_SEC_RTIC_LIODN_ENTRY(a, 144), SET_SEC_RTIC_LIODN_ENTRY(b, 145), SET_SEC_RTIC_LIODN_ENTRY(c, 176), diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index e97ae68c4..49b354d1a 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -156,7 +156,6 @@ void cpu_init_f (volatile immap_t * immr) defined(CONFIG_IVMS8) || \ defined(CONFIG_LWMON) || \ defined(CONFIG_MHPC) || \ - defined(CONFIG_PCU_E) || \ defined(CONFIG_R360MPI) || \ defined(CONFIG_RMU) || \ defined(CONFIG_RPXCLASSIC) || \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 3dd2b7f53..30c64ebb1 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1589,7 +1589,9 @@ typedef struct cpc_corenet { u32 cpcerreaddr; /* error extended address */ u32 cpcerraddr; /* error address */ u32 cpcerrctl; /* error control */ - u32 res9[105]; /* pad out to 4k */ + u32 res9[41]; /* pad out to 4k */ + u32 cpchdbcr0; /* hardware debug control register 0 */ + u32 res10[63]; /* pad out to 4k */ } cpc_corenet_t; #define CPC_CSR0_CE 0x80000000 /* Cache Enable */ @@ -1616,6 +1618,7 @@ typedef struct cpc_corenet { #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a #define CPC_SRCR0_SRAMEN 0x00000001 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ +#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 #endif /* CONFIG_SYS_FSL_CPC */ /* Global Utilities Block */ diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 8f6a7c9d4..bfdfa8624 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -107,7 +107,7 @@ void doc_init (void); static char *failed = "*** failed ***\n"; -#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU) +#if defined(CONFIG_OXC) || defined(CONFIG_RMU) extern flash_info_t flash_info[]; #endif @@ -681,11 +681,10 @@ void board_init_r (gd_t *id, ulong dest_addr) unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */ #endif -#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT) /* - * Do PCI configuration on BAB7xx and CPC45 _before_ the flash - * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus - * bridge there. + * Do early PCI configuration _before_ the flash gets initialised, + * because PCU ressources are crucial for flash access on some boards. */ pci_init (); #endif @@ -735,7 +734,7 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif -# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU) +# if defined(CONFIG_OXC) || defined(CONFIG_RMU) /* flash mapped at end of memory map */ bd->bi_flashoffset = TEXT_BASE + flash_size; # elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE @@ -856,7 +855,7 @@ void board_init_r (gd_t *id, ulong dest_addr) WATCHDOG_RESET (); -#if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx) && !defined(CONFIG_CPC45) +#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT) /* * Do pci configuration */ diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index e509383e8..9abc29c5f 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -27,6 +27,7 @@ #include <asm/arch/mx31-regs.h> #include <nand.h> #include <fsl_pmic.h> +#include <mxc_gpio.h> #include "qong_fpga.h" DECLARE_GLOBAL_DATA_PTR; @@ -41,9 +42,9 @@ int dram_init (void) static void qong_fpga_reset(void) { - mx31_gpio_set(QONG_FPGA_RST_PIN, 0); + mxc_gpio_set(QONG_FPGA_RST_PIN, 0); udelay(30); - mx31_gpio_set(QONG_FPGA_RST_PIN, 1); + mxc_gpio_set(QONG_FPGA_RST_PIN, 1); udelay(300); } @@ -66,11 +67,11 @@ int board_early_init_f (void) /* FPGA reset Pin */ /* rstn = 0 */ - mx31_gpio_set(QONG_FPGA_RST_PIN, 0); - mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT); + mxc_gpio_set(QONG_FPGA_RST_PIN, 0); + mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT); /* set interrupt pin as input */ - mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN); + mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN); #endif @@ -206,27 +207,27 @@ static void board_nand_setup(void) qong_fpga_reset(); /* Enable NAND flash */ - mx31_gpio_set(15, 1); - mx31_gpio_set(14, 1); - mx31_gpio_direction(15, MX31_GPIO_DIRECTION_OUT); - mx31_gpio_direction(16, MX31_GPIO_DIRECTION_IN); - mx31_gpio_direction(14, MX31_GPIO_DIRECTION_IN); - mx31_gpio_set(15, 0); + mxc_gpio_set(15, 1); + mxc_gpio_set(14, 1); + mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN); + mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN); + mxc_gpio_set(15, 0); } int qong_nand_rdy(void *chip) { udelay(1); - return mx31_gpio_get(16); + return mxc_gpio_get(16); } void qong_nand_select_chip(struct mtd_info *mtd, int chip) { if (chip >= 0) - mx31_gpio_set(15, 0); + mxc_gpio_set(15, 0); else - mx31_gpio_set(15, 1); + mxc_gpio_set(15, 1); } diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S index 1b07d622f..137fe41b4 100644 --- a/board/eNET/eNET_start.S +++ b/board/eNET/eNET_start.S @@ -27,19 +27,7 @@ .globl early_board_init early_board_init: /* No 32-bit board specific initialisation */ - jmp *%ebp /* return to caller */ - -.globl show_boot_progress_asm -show_boot_progress_asm: - - movb %al, %dl /* Create Working Copy */ - andb $0x80, %dl /* Mask in only Error bit */ - shrb $0x02, %dl /* Shift Error bit to Error LED */ - andb $0x0f, %al /* Mask out 'Error' bit */ - orb %dl, %al /* Mask in ERR LED */ - movw $LED_LATCH_ADDRESS, %dx - outb %al, %dx - jmp *%ebp /* return to caller */ + jmp early_board_init_ret .globl cpu_halt_asm cpu_halt_asm: diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S index af2c13215..06cfd558d 100644 --- a/board/eNET/eNET_start16.S +++ b/board/eNET/eNET_start16.S @@ -65,8 +65,7 @@ board_init16: movl $0x000000cb, %eax outl %eax, %dx - /* the return address is stored in bp */ - jmp *%bp + jmp board_init16_ret .section .bios, "ax" .code16 diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds index 7b0ffaa6c..b414079bc 100644 --- a/board/eNET/u-boot.lds +++ b/board/eNET/u-boot.lds @@ -27,66 +27,62 @@ ENTRY(_start) SECTIONS { - . = 0x06000000; /* Location of bootcode in flash */ - _i386boot_text_start = .; - .text : { *(.text); } + . = TEXT_BASE; /* Location of bootcode in flash */ + __text_start = .; + .text : { *(.text*); } . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - _i386boot_text_size = SIZEOF(.text) + SIZEOF(.rodata); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } . = ALIGN(4); + __u_boot_cmd_end = .; - .data : { *(.data) } . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - .interp : { *(.interp) } . = ALIGN(4); + .data : { *(.data*) } - .dynsym : { *(.dynsym) } . = ALIGN(4); + .dynsym : { *(.dynsym*) } - .dynstr : { *(.dynstr) } . = ALIGN(4); + .hash : { *(.hash*) } - .hash : { *(.hash) } . = ALIGN(4); + .got : { *(.got*) } - .got : { *(.got) } . = ALIGN(4); + __data_end = .; - .got.plt : { *(.got.plt) } . = ALIGN(4); - - .dynamic (NOLOAD) : { *(.dynamic) } + __bss_start = ABSOLUTE(.); + .bss (NOLOAD) : { *(.bss) } . = ALIGN(4); + __bss_end = ABSOLUTE(.); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } . = ALIGN(4); - __u_boot_cmd_end = .; - _i386boot_cmd_start = LOADADDR(.u_boot_cmd); - - _i386boot_rel_dyn_start = .; + __rel_dyn_start = .; .rel.dyn : { *(.rel.dyn) } - _i386boot_rel_dyn_end = .; + __rel_dyn_end = .; - . = ALIGN(4); - _i386boot_bss_start = ABSOLUTE(.); - .bss (NOLOAD) : { *(.bss) } - _i386boot_bss_size = SIZEOF(.bss); + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } /* 16bit realmode trampoline code */ - .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { *(.realmode) } + .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) } - _i386boot_realmode = LOADADDR(.realmode); - _i386boot_realmode_size = SIZEOF(.realmode); + __realmode_start = LOADADDR(.realmode); + __realmode_size = SIZEOF(.realmode); /* 16bit BIOS emulation code (just enough to boot Linux) */ - .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) } + .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { KEEP(*(.bios)) } - _i386boot_bios = LOADADDR(.bios); - _i386boot_bios_size = SIZEOF(.bios); + __bios_start = LOADADDR(.bios); + __bios_size = SIZEOF(.bios); /* The load addresses below assumes that the flash * will be mapped so that 0x387f0000 == 0xffff0000 @@ -98,12 +94,11 @@ SECTIONS * The fff0 offset of resetvec is important, however. */ . = 0xfffffe00; - .start32 : AT (0x0603fe00) { *(.start32); } + .start32 : AT (TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); } . = 0xf800; - .start16 : AT (0x0603f800) { *(.start16); } + .start16 : AT (TEXT_BASE + 0x3f800) { KEEP(*(.start16)); } . = 0xfff0; - .resetvec : AT (0x0603fff0) { *(.resetvec); } - _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) ); + .resetvec : AT (TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); } } diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 3929ad0aa..11dfd84fe 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -28,13 +28,21 @@ #include <i2c.h> #include <linux/ctype.h> +#ifdef CONFIG_SYS_I2C_EEPROM_CCID #include "../common/eeprom.h" +#define MAX_NUM_PORTS 8 +#endif -#if !defined(CONFIG_SYS_I2C_EEPROM_CCID) && !defined(CONFIG_SYS_I2C_EEPROM_NXID) -#error "Please define either CONFIG_SYS_I2C_EEPROM_CCID or CONFIG_SYS_I2C_EEPROM_NXID" +#ifdef CONFIG_SYS_I2C_EEPROM_NXID +#define MAX_NUM_PORTS 8 +#define NXID_VERSION 0 #endif -#define MAX_NUM_PORTS 8 /* This value must be 8 as defined in doc */ +#ifdef CONFIG_SYS_I2C_EEPROM_NXID_1 +#define CONFIG_SYS_I2C_EEPROM_NXID +#define MAX_NUM_PORTS 23 +#define NXID_VERSION 1 +#endif /** * static eeprom: EEPROM layout for CCID or NXID formats @@ -68,8 +76,8 @@ static struct __attribute__ ((__packed__)) eeprom { u8 res_1[21]; /* 0x2b - 0x3f Reserved */ u8 mac_count; /* 0x40 Number of MAC addresses */ u8 mac_flag; /* 0x41 MAC table flags */ - u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */ - u32 crc; /* 0x72 CRC32 checksum */ + u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */ + u32 crc; /* x+1 CRC32 checksum */ #endif } e; @@ -204,7 +212,7 @@ static void update_crc(void) */ static int prog_eeprom(void) { - int ret = 0; /* shut up gcc */ + int ret = 0; int i; void *p; #ifdef CONFIG_SYS_EEPROM_BUS_NUM @@ -225,6 +233,11 @@ static int prog_eeprom(void) i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); #endif + /* + * The AT24C02 datasheet says that data can only be written in page + * mode, which means 8 bytes at a time, and it takes up to 5ms to + * complete a given write. + */ for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, p, min((sizeof(e) - i), 8)); @@ -233,12 +246,23 @@ static int prog_eeprom(void) udelay(5000); /* 5ms write cycle timing */ } + if (!ret) { + /* Verify the write by reading back the EEPROM and comparing */ + struct eeprom e2; + + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2)); + if (!ret && memcmp(&e, &e2, sizeof(e))) + ret = -1; + } + #ifdef CONFIG_SYS_EEPROM_BUS_NUM i2c_set_bus_num(bus); #endif if (ret) { printf("Programming failed.\n"); + has_been_read = 0; return -1; } @@ -300,7 +324,7 @@ static void set_mac_address(unsigned int index, const char *string) char *p = (char *) string; unsigned int i; - if (!string) { + if ((index >= MAX_NUM_PORTS) || !string) { printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n"); return; } @@ -333,7 +357,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (cmd == 'i') { #ifdef CONFIG_SYS_I2C_EEPROM_NXID memcpy(e.id, "NXID", sizeof(e.id)); - e.version = 0; + e.version = NXID_VERSION; #else memcpy(e.id, "CCID", sizeof(e.id)); #endif @@ -382,8 +406,8 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) e.mac_count = simple_strtoul(argv[2], NULL, 16); update_crc(); break; - case '0' ... '7': /* "mac 0" through "mac 7" */ - set_mac_address(cmd - '0', argv[2]); + case '0' ... '9': /* "mac 0" through "mac 22" */ + set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]); break; case 'h': /* help */ default: diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c index 2994e366c..e1bca1984 100644 --- a/board/freescale/corenet_ds/pci.c +++ b/board/freescale/corenet_ds/pci.c @@ -40,10 +40,14 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif +#ifdef CONFIG_PCIE4 +static struct pci_controller pcie4_hose; +#endif + void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[3]; + struct fsl_pci_info pci_info[4]; u32 devdisr; int first_free_busno = 0; int num = 0; @@ -119,6 +123,28 @@ void pci_init_board(void) #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */ #endif + +#ifdef CONFIG_PCIE4 + pcie_configured = is_serdes_configured(PCIE4); + + if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) { + set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M, + LAW_TRGT_IF_PCIE_4); + set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_4); + SET_STD_PCIE_INFO(pci_info[num], 4); + pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs); + printf(" PCIE4 connected to as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie4_hose, first_free_busno); + } else { + printf (" PCIE4: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */ +#endif } void pci_of_setup(void *blob, bd_t *bd) diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index e938788f0..e3f5b4aa2 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -77,8 +77,18 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 2; /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed + * Enable half drive strength */ - popts->half_strength_driver_enable = 0; + popts->half_strength_driver_enable = 1; + + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xa; + popts->wrlvl_start = 0x4; + + /* Rtt and Rtt_W override */ + popts->rtt_override = 1; + popts->rtt_override_value = DDR3_RTT_60_OHM; + popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ } diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 01b7dcb70..795e5654e 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -27,6 +27,7 @@ #include <pci.h> #include <asm/processor.h> #include <asm/mmu.h> +#include <asm/cache.h> #include <asm/immap_85xx.h> #include <asm/fsl_pci.h> #include <asm/fsl_ddr_sdram.h> @@ -211,6 +212,31 @@ int board_early_init_f (void) return 0; } +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_NAND_BASE; + const u8 flash_esel = 0; + + /* + * Remap Boot flash to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ + 0, flash_esel, /* ts, esel */ + BOOKE_PAGESZ_64M, 1); /* tsize, iprot */ + + return 0; +} + int checkboard (void) { printf ("Board: 8569 MDS\n"); diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c index 73dcc3e66..f852fc35c 100644 --- a/board/freescale/mpc8569mds/tlb.c +++ b/board/freescale/mpc8569mds/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -46,15 +46,20 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 Initializations */ /* - * TLBe 0: 64M Non-cacheable, guarded + * TLBe 0: 64M write-through, guarded * Out of reset this entry is only 4K. - * 0xfc000000 256K NAND FLASH (CS3) - * 0xfe000000 32M NOR FLASH (CS0) + * 0xfc000000 32MB NAND FLASH (CS3) + * 0xfe000000 32MB NOR FLASH (CS0) */ +#ifdef CONFIG_NAND_SPL SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 0, 0, BOOKE_PAGESZ_64M, 1), - +#endif /* * TLBe 1: 256KB Non-cacheable, guarded * 0xf8000000 32K BCSR diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 75d642bf4..84386e6c8 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -33,12 +33,10 @@ #include <fsl_esdhc.h> #include <fsl_pmic.h> #include <mc13892.h> -#include "mx51evk.h" DECLARE_GLOBAL_DATA_PTR; static u32 system_rev; -struct io_board_ctrl *mx51_io_board; #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[2] = { diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 5cdee9ff7..ee93e8b81 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -27,6 +27,7 @@ #include <asm/mp.h> #include <netdev.h> #include <i2c.h> +#include <hwconfig.h> #include "../common/ngpixis.h" @@ -90,34 +91,58 @@ phys_size_t initdram(int board_type) #define CONFIG_TFP410_I2C_ADDR 0x38 +/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ +#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c +#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03 + +/* Route the I2C1 pins to the SSI port instead. */ +#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08 + +/* Choose the 12.288Mhz codec reference clock */ +#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02 + +/* Choose the 11.2896Mhz codec reference clock */ +#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01 + int misc_init_r(void) { u8 temp; + const char *audclk; + size_t arglen; - /* Enable the TFP410 Encoder */ + /* For DVI, enable the TFP410 Encoder. */ temp = 0xBF; if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) return -1; - - /* Verify if enabled */ - temp = 0; if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) return -1; - debug("DVI Encoder Read: 0x%02x\n", temp); temp = 0x10; if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) return -1; - - /* Verify if enabled */ - temp = 0; if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) return -1; - debug("DVI Encoder Read: 0x%02x\n",temp); + /* + * Enable the reference clock for the WM8776 codec, and route the MUX + * pins for SSI. The default is the 12.288 MHz clock + */ + + temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK | + CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK); + temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI; + + audclk = hwconfig_arg("audclk", &arglen); + /* Check the first two chars only */ + if (audclk && (strncmp(audclk, "11", 2) == 0)) + temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11; + else + temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12; + out_8(&pixis->brdcfg1, temp); + return 0; } @@ -310,6 +335,27 @@ int board_eth_init(bd_t *bis) } #ifdef CONFIG_OF_BOARD_SETUP +/** + * ft_codec_setup - fix up the clock-frequency property of the codec node + * + * Update the clock-frequency property based on the value of the 'audclk' + * hwconfig option. If audclk is not specified, then default to 12.288MHz. + */ +static void ft_codec_setup(void *blob, const char *compatible) +{ + const char *audclk; + size_t arglen; + u32 freq; + + audclk = hwconfig_arg("audclk", &arglen); + if (audclk && (strncmp(audclk, "11", 2) == 0)) + freq = 11289600; + else + freq = 12288000; + + do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1); +} + void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -327,6 +373,9 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + + /* Update the WM8776 node's clock frequency property */ + ft_codec_setup(blob, "wlf,wm8776"); } #endif diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 624c7088a..d3300ed68 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -430,12 +430,12 @@ void check_env(void) int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - ulong size,src,ld_addr; + ulong ld_addr; int result; #if !defined(CONFIG_PATI) + ulong size = IMAGE_SIZE; + ulong src = MULTI_PURPOSE_SOCKET_ADDR; backup_t back; - src = MULTI_PURPOSE_SOCKET_ADDR; - size = IMAGE_SIZE; #endif if (strcmp(argv[1], "flash") == 0) @@ -480,30 +480,6 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif /* #if !defined(CONFIG_PATI) */ } - if (strcmp(argv[1], "mem") == 0) - { - result=0; - if(argc==3) - { - result = (int)simple_strtol(argv[2], NULL, 16); - } - src=(unsigned long)&result; - src-=CONFIG_SYS_MEMTEST_START; - src-=(100*1024); /* - 100k */ - src&=0xfff00000; - size=0; - do { - size++; - printf("\n\nPass %ld\n",size); - mem_test(CONFIG_SYS_MEMTEST_START,src,1); - if(ctrlc()) - break; - if(result>0) - result--; - - }while(result); - return 0; - } #if !defined(CONFIG_PATI) if (strcmp(argv[1], "clearenvvalues") == 0) { diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c deleted file mode 100644 index 9c0806599..000000000 --- a/board/mpl/common/memtst.c +++ /dev/null @@ -1,565 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* NOT Used yet... - add following code to PIP405.c : -int testdram (void) -{ - unsigned char s[32]; - int i; - - i = getenv_f("testmem", s, 32); - if (i != 0) { - i = (int) simple_strtoul (s, NULL, 10); - if ((i > 0) && (i < 0xf)) { - printf ("testing "); - i = mem_test (0, ramsize, i); - if (i > 0) - printf ("ERROR "); - else - printf ("Ok "); - } - } - return (1); -} -*/ - - -#include <common.h> -#include <asm/processor.h> -#include <asm/ppc4xx-i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define FALSE 0 -#define TRUE 1 - -#define TEST_QUIET 8 -#define TEST_SHOW_PROG 4 -#define TEST_SHOW_ERR 2 -#define TEST_SHOW_ALL 1 - -#define TESTPAT1 0xAA55AA55 -#define TESTPAT2 0x55AA55AA -#define TEST_PASSED 0 -#define TEST_FAILED 1 -#define MEGABYTE (1024*1024) - - -typedef struct { - volatile unsigned long pat1; - volatile unsigned long pat2; -} RAM_MEMTEST_PATTERN2; - -typedef struct { - volatile unsigned long addr; -} RAM_MEMTEST_ADDRLINE; - -static __inline unsigned long Swap_32 (unsigned long val) -{ - return (((val << 16) & 0xFFFF0000) | ((val >> 16) & 0x0000FFFF)); -} - -void testm_puts (int quiet, char *buf) -{ - if ((quiet & TEST_SHOW_ALL) == TEST_SHOW_ALL) - puts (buf); -} - - -void Write_Error (int mode, unsigned long addr, unsigned long expected, - unsigned long actual) -{ - - char dispbuf[64]; - - sprintf (dispbuf, "\n ERROR @ 0x%08lX: (exp: 0x%08lX act: 0x%08lX) ", - addr, expected, actual); - testm_puts (((mode & TEST_SHOW_ERR) == - TEST_SHOW_ERR) ? TEST_SHOW_ALL : mode, dispbuf); -} - - -/* - * fills the memblock of <size> bytes from <startaddr> with pat1 and pat2 - */ - - -void RAM_MemTest_WritePattern2 (unsigned long startaddr, - unsigned long size, unsigned long pat1, - unsigned long pat2) -{ - RAM_MEMTEST_PATTERN2 *p, *pe; - - p = (RAM_MEMTEST_PATTERN2 *) startaddr; - pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size); - - while (p < pe) { - p->pat1 = pat1; - p->pat2 = pat2; - p++; - } /* endwhile */ -} - -/* - * checks the memblock of <size> bytes from <startaddr> with pat1 and pat2 - * returns the address of the first error or NULL if all is well - */ - -void *RAM_MemTest_CheckPattern2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long pat1, - unsigned long pat2) -{ - RAM_MEMTEST_PATTERN2 *p, *pe; - unsigned long actual1, actual2; - - p = (RAM_MEMTEST_PATTERN2 *) startaddr; - pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size); - - while (p < pe) { - actual1 = p->pat1; - actual2 = p->pat2; - - if (actual1 != pat1) { - Write_Error (mode, (unsigned long) &(p->pat1), pat1, actual1); - return ((void *) &(p->pat1)); - } - /* endif */ - if (actual2 != pat2) { - Write_Error (mode, (unsigned long) &(p->pat2), pat2, actual2); - return ((void *) &(p->pat2)); - } - /* endif */ - p++; - } /* endwhile */ - - return (NULL); -} - -/* - * fills the memblock of <size> bytes from <startaddr> with the address - */ - -void RAM_MemTest_WriteAddrLine (unsigned long startaddr, - unsigned long size, int swapped) -{ - RAM_MEMTEST_ADDRLINE *p, *pe; - - p = (RAM_MEMTEST_ADDRLINE *) startaddr; - pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size); - - if (!swapped) { - while (p < pe) { - p->addr = (unsigned long) p; - p++; - } /* endwhile */ - } else { - while (p < pe) { - p->addr = Swap_32 ((unsigned long) p); - p++; - } /* endwhile */ - } /* endif */ -} - -/* - * checks the memblock of <size> bytes from <startaddr> - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckAddrLine (int mode, unsigned long startaddr, - unsigned long size, int swapped) -{ - RAM_MEMTEST_ADDRLINE *p, *pe; - unsigned long actual, expected; - - p = (RAM_MEMTEST_ADDRLINE *) startaddr; - pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size); - - if (!swapped) { - while (p < pe) { - actual = p->addr; - expected = (unsigned long) p; - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p++; - } /* endwhile */ - } else { - while (p < pe) { - actual = p->addr; - expected = Swap_32 ((unsigned long) p); - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p++; - } /* endwhile */ - } /* endif */ - - return (NULL); -} - -/* - * checks the memblock of <size> bytes from <startaddr+size> - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckAddrLineReverse (int mode, unsigned long startaddr, - unsigned long size, int swapped) -{ - RAM_MEMTEST_ADDRLINE *p, *pe; - unsigned long actual, expected; - - p = (RAM_MEMTEST_ADDRLINE *) (startaddr + size - sizeof (p->addr)); - pe = (RAM_MEMTEST_ADDRLINE *) startaddr; - - if (!swapped) { - while (p > pe) { - actual = p->addr; - expected = (unsigned long) p; - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p--; - } /* endwhile */ - } else { - while (p > pe) { - actual = p->addr; - expected = Swap_32 ((unsigned long) p); - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p--; - } /* endwhile */ - } /* endif */ - - return (NULL); -} - -/* - * fills the memblock of <size> bytes from <startaddr> with walking bit pattern - */ - -void RAM_MemTest_WriteWalkBit (unsigned long startaddr, unsigned long size) -{ - volatile unsigned long *p, *pe; - unsigned long i; - - p = (unsigned long *) startaddr; - pe = (unsigned long *) (startaddr + size); - i = 0; - - while (p < pe) { - *p = 1UL << i; - i = (i + 1 + (((unsigned long) p) >> 7)) % 32; - p++; - } /* endwhile */ -} - -/* - * checks the memblock of <size> bytes from <startaddr> - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckWalkBit (int mode, unsigned long startaddr, - unsigned long size) -{ - volatile unsigned long *p, *pe; - unsigned long actual, expected; - unsigned long i; - - p = (unsigned long *) startaddr; - pe = (unsigned long *) (startaddr + size); - i = 0; - - while (p < pe) { - actual = *p; - expected = (1UL << i); - if (actual != expected) { - Write_Error (mode, (unsigned long) p, expected, actual); - return ((void *) p); - } /* endif */ - i = (i + 1 + (((unsigned long) p) >> 7)) % 32; - p++; - } /* endwhile */ - - return (NULL); -} - -/* - * fills the memblock of <size> bytes from <startaddr> with "random" pattern - */ - -void RAM_MemTest_WriteRandomPattern (unsigned long startaddr, - unsigned long size, - unsigned long *pat) -{ - unsigned long i, p; - - p = *pat; - - for (i = 0; i < (size / 4); i++) { - *(unsigned long *) (startaddr + i * 4) = p; - if ((p % 2) > 0) { - p ^= i; - p >>= 1; - p |= 0x80000000; - } else { - p ^= ~i; - p >>= 1; - } /* endif */ - } /* endfor */ - *pat = p; -} - -/* - * checks the memblock of <size> bytes from <startaddr> - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckRandomPattern (int mode, unsigned long startaddr, - unsigned long size, - unsigned long *pat) -{ - void *perr = NULL; - unsigned long i, p, p1; - - p = *pat; - - for (i = 0; i < (size / 4); i++) { - p1 = *(unsigned long *) (startaddr + i * 4); - if (p1 != p) { - if (perr == NULL) { - Write_Error (mode, startaddr + i * 4, p, p1); - perr = (void *) (startaddr + i * 4); - } /* endif */ - } - /* endif */ - if ((p % 2) > 0) { - p ^= i; - p >>= 1; - p |= 0x80000000; - } else { - p ^= ~i; - p >>= 1; - } /* endif */ - } /* endfor */ - - *pat = p; - return (perr); -} - - -void RAM_MemTest_WriteData1 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT1, TESTPAT2); -} - -void *RAM_MemTest_CheckData1 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckPattern2 - (mode, startaddr, size, TESTPAT1, TESTPAT2)); -} - -void RAM_MemTest_WriteData2 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT2, TESTPAT1); -} - -void *RAM_MemTest_CheckData2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckPattern2 - (mode, startaddr, size, TESTPAT2, TESTPAT1)); -} - -void RAM_MemTest_WriteAddr1 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WriteAddrLine (startaddr, size, FALSE); -} - -void *RAM_MemTest_Check1Addr1 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, FALSE)); -} - -void *RAM_MemTest_Check2Addr1 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLineReverse - (mode, startaddr, size, FALSE)); -} - -void RAM_MemTest_WriteAddr2 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WriteAddrLine (startaddr, size, TRUE); -} - -void *RAM_MemTest_Check1Addr2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, TRUE)); -} - -void *RAM_MemTest_Check2Addr2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLineReverse - (mode, startaddr, size, TRUE)); -} - - -typedef struct { - void (*test_write) (unsigned long startaddr, unsigned long size, - unsigned long *pat); - char *test_write_desc; - void *(*test_check1) (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat); - void *(*test_check2) (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat); -} RAM_MEMTEST_FUNC; - - -#define TEST_STAGES 5 -static RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = { - {RAM_MemTest_WriteData1, "data test 1...\n", RAM_MemTest_CheckData1, - NULL}, - {RAM_MemTest_WriteData2, "data test 2...\n", RAM_MemTest_CheckData2, - NULL}, - {RAM_MemTest_WriteAddr1, "address line test...\n", - RAM_MemTest_Check1Addr1, RAM_MemTest_Check2Addr1}, - {RAM_MemTest_WriteAddr2, "address line test (swapped)...\n", - RAM_MemTest_Check1Addr2, RAM_MemTest_Check2Addr2}, - {RAM_MemTest_WriteRandomPattern, "random data test...\n", - RAM_MemTest_CheckRandomPattern, NULL} -}; - - -int mem_test (unsigned long start, unsigned long ramsize, int quiet) -{ - unsigned long errors, stage; - unsigned long startaddr, size, i; - const unsigned long blocksize = 0x80000; /* check in 512KB blocks */ - unsigned long *perr; - unsigned long rdatapat; - char dispbuf[80]; - int status = TEST_PASSED; - int prog = 0; - - errors = 0; - startaddr = start; - size = ramsize; - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - sprintf (dispbuf, "\nMemory Test: addr = 0x%lx size = 0x%lx\n", - startaddr, size); - testm_puts (quiet, dispbuf); - for (stage = 0; stage < TEST_STAGES; stage++) { - sprintf (dispbuf, test_stage[stage].test_write_desc); - testm_puts (quiet, dispbuf); - /* fill SDRAM */ - rdatapat = 0x12345678; - sprintf (dispbuf, "writing block: "); - testm_puts (quiet, dispbuf); - for (i = 0; i < size; i += blocksize) { - sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); - testm_puts (quiet, dispbuf); - test_stage[stage].test_write (startaddr + i, blocksize, - &rdatapat); - } /* endfor */ - sprintf (dispbuf, "\n"); - testm_puts (quiet, dispbuf); - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - /* check SDRAM */ - rdatapat = 0x12345678; - sprintf (dispbuf, "checking block: "); - testm_puts (quiet, dispbuf); - for (i = 0; i < size; i += blocksize) { - sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); - testm_puts (quiet, dispbuf); - if ((perr = - test_stage[stage].test_check1 (quiet, startaddr + i, - blocksize, - &rdatapat)) != NULL) { - status = TEST_FAILED; - } /* endif */ - } /* endfor */ - sprintf (dispbuf, "\n"); - testm_puts (quiet, dispbuf); - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - if (test_stage[stage].test_check2 != NULL) { - /* check2 SDRAM */ - sprintf (dispbuf, "2nd checking block: "); - rdatapat = 0x12345678; - testm_puts (quiet, dispbuf); - for (i = 0; i < size; i += blocksize) { - sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); - testm_puts (quiet, dispbuf); - if ((perr = - test_stage[stage].test_check2 (quiet, startaddr + i, - blocksize, - &rdatapat)) != NULL) { - status = TEST_FAILED; - } /* endif */ - } /* endfor */ - sprintf (dispbuf, "\n"); - testm_puts (quiet, dispbuf); - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - } - - } /* next stage */ - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - while (prog-- > 0) - printf ("\b \b"); - } - - if (status == TEST_FAILED) - errors++; - - return (errors); -} diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile index 18a8d8656..21e3cdaec 100644 --- a/board/mpl/mip405/Makefile +++ b/board/mpl/mip405/Makefile @@ -29,7 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a COBJS = $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \ - ../common/usb_uhci.o ../common/memtst.o ../common/common_util.o + ../common/usb_uhci.o ../common/common_util.o SOBJS = init.o diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c index 8ddb54db1..f7cc37b84 100644 --- a/board/mpl/mip405/cmd_mip405.c +++ b/board/mpl/mip405/cmd_mip405.c @@ -59,8 +59,7 @@ U_BOOT_CMD( "flash mem [SrcAddr] - updates U-Boot with image in memory\n" "mip405 flash mps - updates U-Boot with image from MPS\n" "mip405 info - displays board information\n" - "mip405 led <on> - switches LED on (on=1) or off (on=0)\n" - "mip405 mem [cnt] - Memory Test <cnt>-times, <cnt> = -1 loop forever" + "mip405 led <on> - switches LED on (on=1) or off (on=0)" ); /* ------------------------------------------------------------------------- */ diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile index adeba69ee..9f38d706c 100644 --- a/board/mpl/pati/Makefile +++ b/board/mpl/pati/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := pati.o ../common/flash.o ../common/memtst.o cmd_pati.o ../common/common_util.o +COBJS := pati.o ../common/flash.o cmd_pati.o ../common/common_util.o #### cmd_pati.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile index 774b59f84..fb39ec3ec 100644 --- a/board/mpl/pip405/Makefile +++ b/board/mpl/pip405/Makefile @@ -32,7 +32,7 @@ COBJS = $(BOARD).o \ ../common/flash.o cmd_pip405.o ../common/pci.o \ ../common/isa.o ../common/kbd.o \ ../common/usb_uhci.o \ - ../common/memtst.o ../common/common_util.o + ../common/common_util.o SOBJS = init.o diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index 10bcb3b0a..3f629fc09 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -29,7 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a COBJS := vcma9.o flash.o cmd_vcma9.o -COBJS += ../common/common_util.o ../common/memtst.o +COBJS += ../common/common_util.o SOBJS := lowlevel_init.o diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index e41c84c76..4dc0237b9 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -96,7 +96,6 @@ static void pm9263_nand_hw_init(void) static void pm9263_macb_hw_init(void) { at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; /* * PB27 enables the 50MHz oscillator for Ethernet PHY diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 3b4d9a345..f3d48f233 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -96,7 +96,6 @@ static void pm9g45_nand_hw_init(void) static void pm9g45_macb_hw_init(void) { at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; /* * PD2 enables the 50MHz oscillator for Ethernet PHY diff --git a/board/siemens/CCM/Makefile b/board/siemens/CCM/Makefile deleted file mode 100644 index c5695f98c..000000000 --- a/board/siemens/CCM/Makefile +++ /dev/null @@ -1,56 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -$(shell mkdir -p $(obj)../../tqc/tqm8xx) -endif - -LIB = $(obj)lib$(BOARD).a - -COBJS = ccm.o flash.o fpga_ccm.o ../common/fpga.o \ - ../../tqc/tqm8xx/load_sernum_ethaddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c deleted file mode 100644 index e91ceb079..000000000 --- a/board/siemens/CCM/ccm.c +++ /dev/null @@ -1,408 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <command.h> - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -void can_driver_enable (void); -void can_driver_disable (void); - -int fpga_init(void); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, - 0x1FF5FC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Always return 1 (no second DRAM bank since based on TQM8xxL module) - */ - -int checkboard (void) -{ - unsigned char *s; - unsigned char buf[64]; - - s = (getenv_f("serial#", (char *)&buf, sizeof(buf)) > 0) ? buf : NULL; - - puts ("Board: Siemens CCM"); - - if (s) { - puts (" ("); - - for (; *s; ++s) { - if (*s == ' ') - break; - putc (*s); - } - putc (')'); - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * If Power-On-Reset switch off the Red and Green LED: At reset, the - * data direction registers are cleared and must therefore be restored. - */ -#define RSR_CSRS 0x08000000 - -int power_on_reset(void) -{ - /* Test Reset Status Register */ - return ((volatile immap_t *)CONFIG_SYS_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1; -} - -#define PB_LED_GREEN 0x10000 /* red LED is on PB.15 */ -#define PB_LED_RED 0x20000 /* red LED is on PB.14 */ -#define PB_LEDS (PB_LED_GREEN | PB_LED_RED); - -static void init_leds (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - - immap->im_cpm.cp_pbpar &= ~PB_LEDS; - immap->im_cpm.cp_pbodr &= ~PB_LEDS; - immap->im_cpm.cp_pbdir |= PB_LEDS; - /* Check stop reset status */ - if (power_on_reset()) { - immap->im_cpm.cp_pbdat &= ~PB_LEDS; - } -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9; - long int size = 0; - unsigned long reg; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay(1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size = size9; -/* debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay(500); -/* debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type - * For types > 128 MBit leave it at the current (fast) rate - */ - if (size < 0x02000000) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay(1000); - } - - /* - * Final mapping - */ - - memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - can_driver_enable (); - init_leds (); - - udelay(10000); - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Warning - both the PUMA load mode and the CAN driver use UPM B, - * so make sure only one of both is active. - */ -void can_driver_enable (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* Initialize MBMR */ - memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ - - /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFC004; - memctl->memc_mcr = 0x0100 | UPMB; - - memctl->memc_mdr = 0x0FFFD004; - memctl->memc_mcr = 0x0101 | UPMB; - - memctl->memc_mdr = 0x0FFFC000; - memctl->memc_mcr = 0x0102 | UPMB; - - memctl->memc_mdr = 0x3FFFC004; - memctl->memc_mcr = 0x0103 | UPMB; - - memctl->memc_mdr = 0xFFFFDC05; - memctl->memc_mcr = 0x0104 | UPMB; - - /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCC004; - memctl->memc_mcr = 0x0118 | UPMB; - - memctl->memc_mdr = 0xCFFCD004; - memctl->memc_mcr = 0x0119 | UPMB; - - memctl->memc_mdr = 0x0FFCC000; - memctl->memc_mcr = 0x011A | UPMB; - - memctl->memc_mdr = 0x7FFCC004; - memctl->memc_mcr = 0x011B | UPMB; - - memctl->memc_mdr = 0xFFFDCC05; - memctl->memc_mcr = 0x011C | UPMB; - - /* Initialize OR3 / BR3 for CAN Bus Controller */ - memctl->memc_or3 = CONFIG_SYS_OR3_CAN; - memctl->memc_br3 = CONFIG_SYS_BR3_CAN; -} - -void can_driver_disable (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* Reset OR3 / BR3 to disable CAN Bus Controller */ - memctl->memc_br3 = 0; - memctl->memc_or3 = 0; - - memctl->memc_mbmr = 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) - -#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN) - -void reset_phy(void) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - ulong value; - - /* Configure all needed port pins for GPIO */ -#ifdef CONFIG_SYS_ETH_MDDIS_VALUE - immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS; -#else - immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* Set low */ -#endif - immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* GPIO */ - immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* active output */ - immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET; /* output */ - - immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ - - value = immr->im_cpm.cp_pbdat; - - /* Assert Powerdown and Reset signals */ - value |= CONFIG_SYS_PB_ETH_POWERDOWN; - - /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ -#ifdef CONFIG_SYS_ETH_CFG1_VALUE - value |= CONFIG_SYS_PB_ETH_CFG1; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG1); -#endif -#ifdef CONFIG_SYS_ETH_CFG2_VALUE - value |= CONFIG_SYS_PB_ETH_CFG2; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG2); -#endif -#ifdef CONFIG_SYS_ETH_CFG3_VALUE - value |= CONFIG_SYS_PB_ETH_CFG3; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG3); -#endif - - /* Drive output signals to initial state */ - immr->im_cpm.cp_pbdat = value; - immr->im_cpm.cp_pbdir |= ETH_ALL_BITS; - udelay (10000); - - /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */ - udelay (10000); - - /* de-assert RESET signal of PHY */ - immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_RESET; - udelay (1000); -} - - -int misc_init_r (void) -{ - fpga_init(); - return (0); -} -/* ------------------------------------------------------------------------- */ diff --git a/board/siemens/CCM/config.mk b/board/siemens/CCM/config.mk deleted file mode 100644 index 9c72c79d3..000000000 --- a/board/siemens/CCM/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# TQM8xxL boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/siemens/CCM/flash.c b/board/siemens/CCM/flash.c deleted file mode 100644 index ad1ed793d..000000000 --- a/board/siemens/CCM/flash.c +++ /dev/null @@ -1,553 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - - if (size_b1 > size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/siemens/CCM/fpga_ccm.c b/board/siemens/CCM/fpga_ccm.c deleted file mode 100644 index 50b08abce..000000000 --- a/board/siemens/CCM/fpga_ccm.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <common.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <common.h> - -#include "../common/fpga.h" - -fpga_t fpga_list[] = { - { "PUMA" , PUMA_CONF_BASE , - CONFIG_SYS_PC_PUMA_INIT , CONFIG_SYS_PC_PUMA_PROG , CONFIG_SYS_PC_PUMA_DONE } -}; -int fpga_count = sizeof(fpga_list) / sizeof(fpga_t); - -void can_driver_enable (void); -void can_driver_disable (void); - -#define _NOT_USED_ 0xFFFFFFFF - -/* - * PUMA access using UPM B - */ -const uint puma_table[] = -{ - /* - * Single Read. (Offset 0 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, - /* - * Precharge and MRS - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x0FFCF804, 0x0FFCF400, 0x3FFDFC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - - -ulong fpga_control (fpga_t* fpga, int cmd) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - switch (cmd) { - case FPGA_INIT_IS_HIGH: - immr->im_ioport.iop_pcdir &= ~fpga->init_mask; /* input */ - return (immr->im_ioport.iop_pcdat & fpga->init_mask) ? 1:0; - - case FPGA_INIT_SET_LOW: - immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */ - immr->im_ioport.iop_pcdat &= ~fpga->init_mask; - break; - - case FPGA_INIT_SET_HIGH: - immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */ - immr->im_ioport.iop_pcdat |= fpga->init_mask; - break; - - case FPGA_PROG_SET_LOW: - immr->im_ioport.iop_pcdat &= ~fpga->prog_mask; - break; - - case FPGA_PROG_SET_HIGH: - immr->im_ioport.iop_pcdat |= fpga->prog_mask; - break; - - case FPGA_DONE_IS_HIGH: - return (immr->im_ioport.iop_pcdat & fpga->done_mask) ? 1:0; - - case FPGA_READ_MODE: - /* disable FPGA in memory controller */ - memctl->memc_br4 = 0; - memctl->memc_or4 = PUMA_CONF_OR_READ; - memctl->memc_br4 = PUMA_CONF_BR_READ; - - /* (re-) enable CAN drivers */ - can_driver_enable (); - - break; - - case FPGA_LOAD_MODE: - /* disable FPGA in memory controller */ - memctl->memc_br4 = 0; - /* - * We must disable the CAN drivers first because - * they use UPM B, too. - */ - can_driver_disable (); - /* - * Configure UPMB for FPGA - */ - upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint)); - memctl->memc_or4 = PUMA_CONF_OR_LOAD; - memctl->memc_br4 = PUMA_CONF_BR_LOAD; - break; - - case FPGA_GET_ID: - return *(volatile ulong *)fpga->conf_base; - - case FPGA_INIT_PORTS: - immr->im_ioport.iop_pcpar &= ~fpga->init_mask; /* INIT I/O */ - immr->im_ioport.iop_pcso &= ~fpga->init_mask; - immr->im_ioport.iop_pcdir &= ~fpga->init_mask; - - immr->im_ioport.iop_pcpar &= ~fpga->prog_mask; /* PROG Output */ - immr->im_ioport.iop_pcso &= ~fpga->prog_mask; - immr->im_ioport.iop_pcdir |= fpga->prog_mask; - - immr->im_ioport.iop_pcpar &= ~fpga->done_mask; /* DONE Input */ - immr->im_ioport.iop_pcso &= ~fpga->done_mask; - immr->im_ioport.iop_pcdir &= ~fpga->done_mask; - - break; - - } - return 0; -} diff --git a/board/siemens/CCM/u-boot.lds b/board/siemens/CCM/u-boot.lds deleted file mode 100644 index 36dd55dee..000000000 --- a/board/siemens/CCM/u-boot.lds +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - lib/zlib.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/CCM/u-boot.lds.debug b/board/siemens/CCM/u-boot.lds.debug deleted file mode 100644 index 7e066b11e..000000000 --- a/board/siemens/CCM/u-boot.lds.debug +++ /dev/null @@ -1,135 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) -/* - . = env_offset; - common/env_embedded.o(.text) -*/ - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/pcu_e/flash.c b/board/siemens/pcu_e/flash.c deleted file mode 100644 index 3ce7bb329..000000000 --- a/board/siemens/pcu_e/flash.c +++ /dev/null @@ -1,700 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - * - * The PCU E uses an address map where flash banks are aligned top - * down, so that the "first" flash bank ends at top of memory, and - * the monitor entry point is at address (0xFFF00100). The second - * flash bank is mapped immediately below bank 0. - * - * This is NOT in conformance to the "official" memory map! - * - */ - -#define PCU_MONITOR_BASE ( (flash_info[0].start[0] + flash_info[0].size - 1) \ - - (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE) ) - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long base, size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - /* - * Warning: - * - * Since the PCU E memory map assigns flash banks top down, - * we swap the numbering later if both banks are equipped, - * so they look like a contiguous area of memory. - */ - DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM); - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE6_PRELIM); - size_b1 = flash_get_size((vu_long *)FLASH_BASE6_PRELIM, &flash_info[1]); - - DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n", size_b0, size_b1); - - if (size_b1 > size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - DEBUGF ("## Before remap: " - "BR0: 0x%08x OR0: 0x%08x " - "BR6: 0x%08x OR6: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br6, memctl->memc_or6); - - /* Remap FLASH according to real size */ - base = 0 - size_b0; - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; - - DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)base, &flash_info[0]); - base = 0 - size_b0; - - flash_info[0].size = size_b0; - - flash_get_offsets (base, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - PCU_MONITOR_BASE, - PCU_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - flash_info_t tmp_info; - - memctl->memc_or6 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) | - BR_PS_16 | BR_MS_GPCM | BR_V; - - DEBUGF("## New BR6: 0x%08x OR6: 0x%08x\n", - memctl->memc_br6, memctl->memc_or6); - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(base - size_b1), - &flash_info[1]); - base -= size_b1; - - flash_get_offsets (base, &flash_info[1]); - - flash_info[1].size = size_b1; - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[1]); -#endif - /* - * Swap bank numbers so that addresses are in ascending order - */ - tmp_info = flash_info[0]; - flash_info[0] = flash_info[1]; - flash_info[1] = tmp_info; - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - - DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - short n; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) { - return; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL322T: - case FLASH_AMDL323T: - case FLASH_AMDL324T: - /* set sector offsets for top boot block type */ - - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - return; - case FLASH_AMDL322B: - case FLASH_AMDL323B: - case FLASH_AMDL324B: - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (base < info->size) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - return; - case FLASH_AMDL640: - /* set sector offsets for dual boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - n = info->sector_count - 8; - while (i < n) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - while (i < info->sector_count) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - ++i; - } - return; - default: - return; - } - /* NOTREACHED */ -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL322B: printf ("AM29DL322B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AMDL323T: printf ("AM29DL323T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL324B: printf ("AM29DL324B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AMDL324T: printf ("AM29DL324T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL640: printf ("AM29DL640D (64 Mbit, dual boot sector)\n"); - break; - default: printf ("Unknown Chip Type 0x%lX\n", - info->flash_id); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ushort value; - vu_short *saddr = (vu_short *)addr; - - /* Write auto select command: read Manufacturer ID */ - saddr[0x0555] = 0x00AA; - saddr[0x02AA] = 0x0055; - saddr[0x0555] = 0x0090; - - value = saddr[0]; - - DEBUGF("Manuf. ID @ 0x%08lx: 0x%04x\n", (ulong)addr, value); - - switch (value) { - case (AMD_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_FUJ; - break; - default: - DEBUGF("Unknown Manufacturer ID\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = saddr[1]; /* device ID */ - - DEBUGF("Device ID @ 0x%08lx: 0x%04x\n", (ulong)(&addr[1]), value); - - switch (value) { - - case (AMD_ID_DL322T & 0xFFFF): - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL322B & 0xFFFF): - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL323T & 0xFFFF): - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL323B & 0xFFFF): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL324T & 0xFFFF): - info->flash_id += FLASH_AMDL324T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL324B & 0xFFFF): - info->flash_id += FLASH_AMDL324B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - case (AMD_ID_DL640 & 0xFFFF): - info->flash_id += FLASH_AMDL640; - info->sector_count = 142; - info->size = 0x00800000; - break; - default: - DEBUGF("Unknown Device ID\n"); - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - flash_get_offsets ((ulong)addr, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { -#if 0 - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - saddr = (vu_short *)(info->start[i]); - info->protect[i] = saddr[2] & 1; -#else - info->protect[i] =0; -#endif - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - saddr = (vu_short *)info->start[0]; - *saddr = 0x00F0; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr = (vu_short*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0080; - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short*)(info->start[sect]); - addr[0] = 0x0030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_short*)(info->start[l_sect]); - while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = 0x00F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -#define FLASH_WIDTH 2 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<FLASH_WIDTH && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_data(info, wp, data)) != 0) { - return (rc); - } - wp += FLASH_WIDTH; - } - - /* - * handle FLASH_WIDTH aligned part - */ - while (cnt >= FLASH_WIDTH) { - data = 0; - for (i=0; i<FLASH_WIDTH; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data(info, wp, data)) != 0) { - return (rc); - } - wp += FLASH_WIDTH; - cnt -= FLASH_WIDTH; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<FLASH_WIDTH; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_data(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, ulong data) -{ - vu_short *addr = (vu_short*)(info->start[0]); - vu_short *sdest = (vu_short *)dest; - ushort sdata = (ushort)data; - ushort sval; - ulong start, passed; - int flag, rc; - - /* Check if Flash is (sufficiently) erased */ - if ((*sdest & sdata) != sdata) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x00A0; - -#ifdef WORKAROUND_FOR_BROKEN_HARDWARE - /* work around the timeout bugs */ - udelay(20); -#endif - - *sdest = sdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - rc = 0; - /* data polling for D7 */ - start = get_timer (0); - - for (passed=0; passed < CONFIG_SYS_FLASH_WRITE_TOUT; passed=get_timer(start)) { - - sval = *sdest; - - if ((sval & 0x0080) == (sdata & 0x0080)) - break; - - if ((sval & 0x0020) == 0) /* DQ5: Timeout? */ - continue; - - sval = *sdest; - - if ((sval & 0x0080) != (sdata & 0x0080)) - rc = 1; - - break; - } - - if (rc) { - DEBUGF ("Program cycle failed @ addr 0x%08lX: val %04X data %04X\n", - dest, sval, sdata); - } - - if (passed >= CONFIG_SYS_FLASH_WRITE_TOUT) { - DEBUGF ("Timeout @ addr 0x%08lX: val %04X data %04X\n", - dest, sval, sdata); - rc = 1; - } - - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = 0x00F0; /* reset bank */ - - return (rc); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c deleted file mode 100644 index 97952844f..000000000 --- a/board/siemens/pcu_e/pcu_e.c +++ /dev/null @@ -1,562 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <i2c.h> -#include <command.h> - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -static void puma_status (void); -static void puma_set_mode (int mode); -static int puma_init_done (void); -static void puma_load (ulong addr, ulong len); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -/* - * 50 MHz SDRAM access using UPM A - */ -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00, - 0x1ffddc47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPM RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */ - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00, - 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - 0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - -/* - * PUMA access using UPM B - */ -const uint puma_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, - /* - * Precharge and MRS - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - */ - -int checkboard (void) -{ - puts ("Board: Siemens PCU E\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - long int size_b0, reg; - int i; - - /* - * Configure UPMA for SDRAM - */ - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* burst length=4, burst type=sequential, CAS latency=2 */ - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 2 to the SDRAM bank at preliminary address. - */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; - memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; -#else /* XXX */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; -#endif /* XXX */ - - /* initialize memory address register */ - memctl->memc_mamr = CONFIG_SYS_MAMR; /* refresh not enabled yet */ - - /* mode initialization (offset 5) */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - udelay (200); /* 0x8000A105 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05); -#else /* XXX */ - udelay (200); /* 0x80004105 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05); -#endif /* XXX */ - - /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - udelay (1); /* 0x8000A830 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30); -#else /* XXX */ - udelay (1); /* 0x80004830 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30); -#endif /* XXX */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - udelay (1); /* 0x8000A106 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06); -#else /* XXX */ - udelay (1); /* 0x80004106 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06); -#endif /* XXX */ - - reg = memctl->memc_mamr; - reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */ - reg |= MAMR_TLFA_4X; /* ... to 4x */ - reg |= MAMR_PTAE; /* enable refresh */ - memctl->memc_mamr = reg; - - udelay (200); - - /* Need at least 10 DRAM accesses to stabilize */ - for (i = 0; i < 10; ++i) { -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - volatile unsigned long *addr = - (volatile unsigned long *) SDRAM_BASE5_PRELIM; -#else /* XXX */ - volatile unsigned long *addr = - (volatile unsigned long *) SDRAM_BASE2_PRELIM; -#endif /* XXX */ - unsigned long val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* - * Check Bank 0 Memory Size for re-configuration - */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE); -#else /* XXX */ - size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); -#endif /* XXX */ - - memctl->memc_mamr = CONFIG_SYS_MAMR | MAMR_PTAE; - - /* - * Final mapping: - */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br5 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; -#else /* XXX */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; -#endif /* XXX */ - udelay (1000); - - /* - * Configure UPMB for PUMA - */ - upmconfig (UPMB, (uint *) puma_table, - sizeof (puma_table) / sizeof (uint)); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) -#else /* XXX */ -#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_MDDIS | CONFIG_SYS_PB_ETH_CFG1 | \ - CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) -#endif /* XXX */ - -#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN | CONFIG_SYS_PB_ETH_RESET) - -void reset_phy (void) -{ - immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - ulong value; - - /* Configure all needed port pins for GPIO */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -# ifdef CONFIG_SYS_ETH_MDDIS_VALUE - immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS; -# else - immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* Set low */ -# endif - immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* GPIO */ - immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* active output */ - immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS; /* output */ -#endif /* XXX */ - immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ - - value = immr->im_cpm.cp_pbdat; - - /* Assert Powerdown and Reset signals */ - value |= CONFIG_SYS_PB_ETH_POWERDOWN; - value &= ~(CONFIG_SYS_PB_ETH_RESET); - - /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ -#if !PCU_E_WITH_SWAPPED_CS -# ifdef CONFIG_SYS_ETH_MDDIS_VALUE - value |= CONFIG_SYS_PB_ETH_MDDIS; -# else - value &= ~(CONFIG_SYS_PB_ETH_MDDIS); -# endif -#endif -#ifdef CONFIG_SYS_ETH_CFG1_VALUE - value |= CONFIG_SYS_PB_ETH_CFG1; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG1); -#endif -#ifdef CONFIG_SYS_ETH_CFG2_VALUE - value |= CONFIG_SYS_PB_ETH_CFG2; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG2); -#endif -#ifdef CONFIG_SYS_ETH_CFG3_VALUE - value |= CONFIG_SYS_PB_ETH_CFG3; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG3); -#endif - - /* Drive output signals to initial state */ - immr->im_cpm.cp_pbdat = value; - immr->im_cpm.cp_pbdir |= ETH_ALL_BITS; - udelay (10000); - - /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */ - udelay (10000); - - /* de-assert RESET signal of PHY */ - immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_ETH_RESET; - udelay (1000); -} - -/*----------------------------------------------------------------------- - * Board Special Commands: access functions for "PUMA" FPGA - */ -#if defined(CONFIG_CMD_BSP) - -#define PUMA_READ_MODE 0 -#define PUMA_LOAD_MODE 1 - -int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr, len; - - switch (argc) { - case 2: /* PUMA reset */ - if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */ - puma_status (); - return 0; - } - break; - case 4: /* PUMA load addr len */ - if (strcmp (argv[1], "load") != 0) - break; - - addr = simple_strtoul (argv[2], NULL, 16); - len = simple_strtoul (argv[3], NULL, 16); - - printf ("PUMA load: addr %08lX len %ld (0x%lX): ", - addr, len, len); - puma_load (addr, len); - - return 0; - default: - break; - } - return cmd_usage(cmdtp); -} - -U_BOOT_CMD (puma, 4, 1, do_puma, - "access PUMA FPGA", - "status - print PUMA status\n" - "puma load addr len - load PUMA configuration data" -); -#endif - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static void puma_set_mode (int mode) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - /* disable PUMA in memory controller */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_br3 = 0; -#else /* XXX */ - memctl->memc_br4 = 0; -#endif /* XXX */ - - switch (mode) { - case PUMA_READ_MODE: -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or3 = PUMA_CONF_OR_READ; - memctl->memc_br3 = PUMA_CONF_BR_READ; -#else /* XXX */ - memctl->memc_or4 = PUMA_CONF_OR_READ; - memctl->memc_br4 = PUMA_CONF_BR_READ; -#endif /* XXX */ - break; - case PUMA_LOAD_MODE: -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or3 = PUMA_CONF_OR_LOAD; - memctl->memc_br3 = PUMA_CONF_BR_LOAD; -#else /* XXX */ - memctl->memc_or4 = PUMA_CONF_OR_READ; - memctl->memc_br4 = PUMA_CONF_BR_READ; -#endif /* XXX */ - break; - } -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */ - -static void puma_load (ulong addr, ulong len) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */ - uchar *data = (uchar *) addr; - int i; - - /* align length */ - if (len & 1) - ++len; - - /* Reset FPGA */ - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_INIT); /* make input */ - immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_INIT); - immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_INIT); - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_PUMA_PROG); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_PUMA_PROG); /* active output */ - immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_PUMA_PROG); /* Set low */ - immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_PUMA_PROG; /* output */ -#else - immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_PUMA_PROG); /* GPIO */ - immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_PUMA_PROG); /* Set low */ - immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_PUMA_PROG); /* active output */ - immr->im_ioport.iop_padir |= CONFIG_SYS_PA_PUMA_PROG; /* output */ -#endif /* XXX */ - udelay (100); - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_PUMA_PROG; /* release reset */ -#else - immr->im_ioport.iop_padat |= CONFIG_SYS_PA_PUMA_PROG; /* release reset */ -#endif /* XXX */ - - /* wait until INIT indicates completion of reset */ - for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) { - udelay (1000); - if (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_INIT) - break; - } - if (i == PUMA_INIT_TIMEOUT) { - printf ("*** PUMA init timeout ***\n"); - return; - } - - puma_set_mode (PUMA_LOAD_MODE); - - while (len--) - *fpga_addr = *data++; - - puma_set_mode (PUMA_READ_MODE); - - puma_status (); -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static void puma_status (void) -{ - /* Check state */ - printf ("PUMA initialization is %scomplete\n", - puma_init_done ()? "" : "NOT "); -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static int puma_init_done (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* make sure pin is GPIO input */ - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_DONE); - immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_DONE); - immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_DONE); - - return (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_DONE) ? 1 : 0; -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r (void) -{ - ulong addr = 0; - ulong len = 0; - char *s; - - printf ("PUMA: "); - if (puma_init_done ()) { - printf ("initialized\n"); - return 0; - } - - if ((s = getenv ("puma_addr")) != NULL) - addr = simple_strtoul (s, NULL, 16); - - if ((s = getenv ("puma_len")) != NULL) - len = simple_strtoul (s, NULL, 16); - - if ((!addr) || (!len)) { - printf ("net list undefined\n"); - return 0; - } - - printf ("loading... "); - - puma_load (addr, len); - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/siemens/pcu_e/u-boot.lds b/board/siemens/pcu_e/u-boot.lds deleted file mode 100644 index b871958f1..000000000 --- a/board/siemens/pcu_e/u-boot.lds +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/env_embedded.o(.text) - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/pcu_e/u-boot.lds.debug b/board/siemens/pcu_e/u-boot.lds.debug deleted file mode 100644 index 131ad23c7..000000000 --- a/board/siemens/pcu_e/u-boot.lds.debug +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/pcu_e/Makefile b/board/ttcontrol/vision2/Makefile index dcb190703..309e3a3df 100644 --- a/board/siemens/pcu_e/Makefile +++ b/board/ttcontrol/vision2/Makefile @@ -1,9 +1,7 @@ # -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> # -# See file CREDITS for list of people who contributed to this -# project. +# (C) Copyright 2009 Freescale Semiconductor, Inc. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as @@ -25,14 +23,20 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS := vision2.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend ######################################################################### diff --git a/board/siemens/pcu_e/config.mk b/board/ttcontrol/vision2/config.mk index 10f37734a..59f3367cf 100644 --- a/board/siemens/pcu_e/config.mk +++ b/board/ttcontrol/vision2/config.mk @@ -1,6 +1,5 @@ # -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. # # See file CREDITS for list of people who contributed to this # project. @@ -21,8 +20,6 @@ # MA 02111-1307 USA # -# -# Siemens PCU E Boards -# - -TEXT_BASE = 0xFFF00000 +LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds +TEXT_BASE = 0x97800000 +IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage_hynix.cfg diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg new file mode 100644 index 000000000..ed531db0b --- /dev/null +++ b/board/ttcontrol/vision2/imximage_hynix.cfg @@ -0,0 +1,209 @@ +# +# (C) Copyright 2009 +# Stefano Babic DENX Software Engineering sbabic@denx.de. +# +# (C) Copyright 2010 +# Klaus Steinhammer TTECH Control Gmbh kst@tttech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# Boot Device : one of +# spi, nand, onenand, sd + +BOOT_FROM spi + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register + +####################### +### Disable WDOG ### +####################### +DATA 2 0x73f98000 0x30 + +####################### +### SET DDR Clk ### +####################### + +# CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) +DATA 4 0x73FD4018 0x000024C0 + +# DOUBLE SPI CLK (13MHz->26 MHz Clock) +DATA 4 0x73FD4038 0x2010241 + +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa8600 0x00000107 +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa8604 0x00000107 +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa8608 0x00000187 +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa860c 0x00000187 +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa8614 0x00000107 +#IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) +DATA 4 0x73fa86a8 0x00000187 + +####################### +### Settings IOMUXC ### +####################### + +# DDR IOMUX configuration +# Control, Data, Address pads are in their default state: HIGH DS, FAST SR. +# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS +DATA 4 0x73fa84b8 0x000000e7 +# PVTC MAX (at GPC, PGR reg) +#DATA 4 0x73FD8004 0x1fc00000 + +#DQM0 DS high slew rate slow +DATA 4 0x73fa84d4 0x000000e4 +#DQM1 DS high slew rate slow +DATA 4 0x73fa84d8 0x000000e4 +#DQM2 DS high slew rate slow +DATA 4 0x73fa84dc 0x000000e4 +#DQM3 DS high slew rate slow +DATA 4 0x73fa84e0 0x000000e4 + +#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow +DATA 4 0x73fa84bc 0x000000c4 +#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow +DATA 4 0x73fa84c0 0x000000c4 +#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow +DATA 4 0x73fa84c4 0x000000c4 +#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow +DATA 4 0x73fa84c8 0x000000c4 + +#DRAM_DATA B0 +DATA 4 0x73fa88a4 0x00000004 +#DRAM_DATA B1 +DATA 4 0x73fa88ac 0x00000004 +#DRAM_DATA B2 +DATA 4 0x73fa88b8 0x00000004 +#DRAM_DATA B3 +DATA 4 0x73fa882c 0x00000004 + +#DRAM_DATA B0 slew rate +DATA 4 0x73fa8878 0x00000000 +#DRAM_DATA B1 slew rate +DATA 4 0x73fa8880 0x00000000 +#DRAM_DATA B2 slew rate +DATA 4 0x73fa888c 0x00000000 +#DRAM_DATA B3 slew rate +DATA 4 0x73fa889c 0x00000000 + +####################### +### Configure SDRAM ### +####################### + +# Configure CS0 +####################### + +# ESDCTL0: Enable controller +DATA 4 0x83fd9000 0x83220000 + +# Init DRAM on CS0 +# ESDSCR: Precharge command +DATA 4 0x83fd9014 0x04008008 +# ESDSCR: Refresh command +DATA 4 0x83fd9014 0x00008010 +# ESDSCR: Refresh command +DATA 4 0x83fd9014 0x00008010 +# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) +DATA 4 0x83fd9014 0x00338018 +# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) +DATA 4 0x83fd9014 0x0020801a +# ESDSCR +DATA 4 0x83fd9014 0x00008000 + +# ESDSCR: EMR with full Drive strength +#DATA 4 0x83fd9014 0x0000801a + +# ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 +DATA 4 0x83fd9000 0xC3220000 + +# ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks +# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks +#DATA 4 0x83fd9004 0xC33574AA + +#micron mDDR +# ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks +# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks +#DATA 4 0x83FD9004 0x101564a8 + +#hynix mDDR +# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks +# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks +DATA 4 0x83FD9004 0x704564a8 + +# ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 +DATA 4 0x83fd9010 0x000a1700 + +# Configure CS1 +####################### + +# ESDCTL1: Enable controller +DATA 4 0x83fd9008 0x83220000 + +# Init DRAM on CS1 +# ESDSCR: Precharge command +DATA 4 0x83fd9014 0x0400800c +# ESDSCR: Refresh command +DATA 4 0x83fd9014 0x00008014 +# ESDSCR: Refresh command +DATA 4 0x83fd9014 0x00008014 +# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) +DATA 4 0x83fd9014 0x0033801c +# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) +DATA 4 0x83fd9014 0x0020801e +# ESDSCR +DATA 4 0x83fd9014 0x00008004 + +# ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 +DATA 4 0x83fd9008 0xC3220000 + +# ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks +# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks +#DATA 4 0x83fd900c 0xC33574AA + +#micron mDDR +# ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks +# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks +#DATA 4 0x83FD900C 0x101564a8 + +#hynix mDDR +# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks +# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks +DATA 4 0x83FD900C 0x704564a8 + +# ESDSCR (mDRAM configuration finished) +DATA 4 0x83FD9014 0x00000004 + +# ESDSCR - clear "configuration request" bit +DATA 4 0x83fd9014 0x00000000 diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c new file mode 100644 index 000000000..c991ee271 --- /dev/null +++ b/board/ttcontrol/vision2/vision2.c @@ -0,0 +1,711 @@ +/* + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx51_pins.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <mxc_gpio.h> +#include <asm/arch/sys_proto.h> +#include <asm/errno.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <fsl_pmic.h> +#include <mc13892.h> + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; + +#ifdef CONFIG_HW_WATCHDOG +#include <watchdog.h> + +void hw_watchdog_reset(void) +{ + int val; + + /* toggle watchdog trigger pin */ + val = mxc_gpio_get(66); + val = val ? 0 : 1; + mxc_gpio_set(66, val); +} +#endif + +static void init_drive_strength(void) +{ + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS, + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS, + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM); + + /* Setting pad options */ + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); +} + +u32 get_board_rev(void) +{ + system_rev = get_cpu_rev(); + + return system_rev; +} + +int dram_init(void) +{ +#ifdef CONFIG_SYS_ARM_WITHOUT_RELOC + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); +#if (CONFIG_NR_DRAM_BANKS > 1) + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); +#endif +#else + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); +#endif + + return 0; +} + +static void setup_weim(void) +{ + struct weim *pweim = (struct weim *)WEIM_BASE_ADDR; + + pweim->csgcr1 = 0x004100b9; + pweim->csgcr2 = 0x00000001; + pweim->csrcr1 = 0x0a018000; + pweim->csrcr2 = 0; + pweim->cswcr1 = 0x0704a240; +} + +static void setup_uart(void) +{ + unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST; + /* console RX on Pin EIM_D25 */ + mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad); + /* console TX on Pin EIM_D26 */ + mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad); +} + +#ifdef CONFIG_MXC_SPI +void spi_io_init(void) +{ + /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ + mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* + * SS1 will be used as GPIO because of uninterrupted + * long SPI transmissions (GPIO4_25) + */ + mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7); + mxc_iomux_set_pad(MX51_PIN_DI1_PIN11, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); +} + +static void reset_peripherals(int reset) +{ + if (reset) { + + /* reset_n is on NANDF_D15 */ + mxc_gpio_set(89, 0); + mxc_gpio_direction(89, MXC_GPIO_DIRECTION_OUT); + +#ifdef CONFIG_VISION2_HW_1_0 + /* + * set FEC Configuration lines + * set levels of FEC config lines + */ + mxc_gpio_set(75, 0); + mxc_gpio_set(74, 1); + mxc_gpio_set(95, 1); + mxc_gpio_direction(75, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(74, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(95, MXC_GPIO_DIRECTION_OUT); + + /* set direction of FEC config lines */ + mxc_gpio_set(59, 0); + mxc_gpio_set(60, 0); + mxc_gpio_set(61, 0); + mxc_gpio_set(55, 1); + mxc_gpio_direction(59, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(60, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(61, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(55, MXC_GPIO_DIRECTION_OUT); + + /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */ + mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1); + /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */ + mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1); + /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */ + mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1); + /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */ + mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1); + /* FEC_COL - sel GPIO (3-10) for configuration -> 1 */ + mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3); + /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */ + mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3); + /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */ + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3); +#endif + + /* + * activate reset_n pin + * Select mux mode: ALT3 mux port: NAND D15 + */ + mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_NANDF_D15, + PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX); + } else { + /* set FEC Control lines */ + mxc_gpio_direction(89, MXC_GPIO_DIRECTION_IN); + udelay(500); + +#ifdef CONFIG_VISION2_HW_1_0 + /* FEC RDATA[3] */ + mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); + + /* FEC RDATA[2] */ + mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); + + /* FEC RDATA[1] */ + mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); + + /* FEC RDATA[0] */ + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); + + /* FEC RX_CLK */ + mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); + + /* FEC RX_ER */ + mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); + + /* FEC COL */ + mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); +#endif + } +} + +static void power_init_mx51(void) +{ + unsigned int val; + + /* Write needed to Power Gate 2 register */ + val = pmic_reg_read(REG_POWER_MISC); + + /* enable VCAM with 2.775V to enable read from PMIC */ + val = VCAMCONFIG | VCAMEN; + pmic_reg_write(REG_MODE_1, val); + + /* + * Set switchers in Auto in NORMAL mode & STANDBY mode + * Setup the switcher mode for SW1 & SW2 + */ + val = pmic_reg_read(REG_SW_4); + val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | + (SWMODE_MASK << SWMODE2_SHIFT))); + val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); + pmic_reg_write(REG_SW_4, val); + + /* Setup the switcher mode for SW3 & SW4 */ + val = pmic_reg_read(REG_SW_5); + val &= ~((SWMODE_MASK << SWMODE4_SHIFT) | + (SWMODE_MASK << SWMODE3_SHIFT)); + val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE3_SHIFT); + pmic_reg_write(REG_SW_5, val); + + + /* Set VGEN3 to 1.8V, VCAM to 3.0V */ + val = pmic_reg_read(REG_SETTING_0); + val &= ~(VCAM_MASK | VGEN3_MASK); + val |= VCAM_3_0; + pmic_reg_write(REG_SETTING_0, val); + + /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */ + val = pmic_reg_read(REG_SETTING_1); + val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); + val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8; + pmic_reg_write(REG_SETTING_1, val); + + /* Configure VGEN3 and VCAM regulators to use external PNP */ + val = VGEN3CONFIG | VCAMCONFIG; + pmic_reg_write(REG_MODE_1, val); + udelay(200); + + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ + val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | + VVIDEOEN | VAUDIOEN | VSDEN; + pmic_reg_write(REG_MODE_1, val); + + val = pmic_reg_read(REG_POWER_CTL2); + val |= WDIRESET; + pmic_reg_write(REG_POWER_CTL2, val); + + udelay(2500); + +} +#endif + +static void setup_gpios(void) +{ + unsigned int i; + + /* CAM_SUP_DISn, GPIO1_7 */ + mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82); + + /* DAB Display EN, GPIO3_1 */ + mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82); + + /* WDOG_TRIGGER, GPIO3_2 */ + mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82); + + /* Now we need to trigger the watchdog */ + WATCHDOG_RESET(); + + /* Display2 TxEN, GPIO3_3 */ + mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82); + + /* DAB Light EN, GPIO3_4 */ + mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82); + + /* AUDIO_MUTE, GPIO3_5 */ + mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82); + + /* SPARE_OUT, GPIO3_6 */ + mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82); + + /* BEEPER_EN, GPIO3_26 */ + mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82); + + /* POWER_OFF, GPIO3_27 */ + mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82); + + /* FRAM_WE, GPIO3_30 */ + mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82); + + /* EXPANSION_EN, GPIO4_26 */ + mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82); + + /* + * Set GPIO1_4 to high and output; it is used to reset + * the system on reboot + */ + mxc_gpio_set(4, 1); + mxc_gpio_direction(4, MXC_GPIO_DIRECTION_OUT); + + mxc_gpio_set(7, 0); + mxc_gpio_direction(7, MXC_GPIO_DIRECTION_OUT); + for (i = 65; i < 71; i++) { + mxc_gpio_set(i, 0); + mxc_gpio_direction(i, MXC_GPIO_DIRECTION_OUT); + } + + mxc_gpio_set(94, 0); + mxc_gpio_direction(94, MXC_GPIO_DIRECTION_OUT); + + /* Set POWER_OFF high */ + mxc_gpio_set(91, 1); + mxc_gpio_direction(91, MXC_GPIO_DIRECTION_OUT); + + mxc_gpio_set(90, 0); + mxc_gpio_direction(90, MXC_GPIO_DIRECTION_OUT); + + mxc_gpio_set(122, 0); + mxc_gpio_direction(122, MXC_GPIO_DIRECTION_OUT); + + mxc_gpio_set(121, 1); + mxc_gpio_direction(121, MXC_GPIO_DIRECTION_OUT); + + WATCHDOG_RESET(); +} + +static void setup_fec(void) +{ + /*FEC_MDIO*/ + mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD); + + /*FEC_MDC*/ + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004); + + /* FEC RDATA[3] */ + mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); + + /* FEC RDATA[2] */ + mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); + + /* FEC RDATA[1] */ + mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); + + /* FEC RDATA[0] */ + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); + + /* FEC TDATA[3] */ + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004); + + /* FEC TDATA[2] */ + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004); + + /* FEC TDATA[1] */ + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004); + + /* FEC TDATA[0] */ + mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004); + + /* FEC TX_EN */ + mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004); + + /* FEC TX_ER */ + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004); + + /* FEC TX_CLK */ + mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180); + + /* FEC TX_COL */ + mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); + + /* FEC RX_CLK */ + mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); + + /* FEC RX_CRS */ + mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180); + + /* FEC RX_ER */ + mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); + + /* FEC RX_DV */ + mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180); +} + +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {MMC_SDHC1_BASE_ADDR, 1}, +}; + +int get_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) + *cd = mxc_gpio_get(0); + else + *cd = 0; + + return 0; +} + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_init(bd_t *bis) +{ + mxc_request_iomux(MX51_PIN_SD1_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD1_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_GPIO1_0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_0, + PAD_CTL_HYS_ENABLE); + mxc_request_iomux(MX51_PIN_GPIO1_1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_1, + PAD_CTL_HYS_ENABLE); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} +#endif + +int board_early_init_f(void) +{ + + + init_drive_strength(); + + /* Setup debug led */ + mxc_gpio_set(6, 0); + mxc_gpio_direction(6, MXC_GPIO_DIRECTION_OUT); + mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* wait a little while to give the pll time to settle */ + sdelay(100000); + + setup_weim(); + setup_uart(); + setup_fec(); + setup_gpios(); + + spi_io_init(); + + return 0; +} + +int board_init(void) +{ +#ifdef CONFIG_SYS_ARM_WITHOUT_RELOC + board_early_init_f(); +#endif + gd->bd->bi_arch_number = MACH_TYPE_TTC_VISION2; /* board id for linux */ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int board_late_init(void) +{ + power_init_mx51(); + + reset_peripherals(1); + udelay(2000); + reset_peripherals(0); + udelay(2000); + + /* Early revisions require a second reset */ +#ifdef CONFIG_VISION2_HW_1_0 + reset_peripherals(1); + udelay(2000); + reset_peripherals(0); + udelay(2000); +#endif + + return 0; +} + +int checkboard(void) +{ + u32 system_rev = get_cpu_rev(); + u32 cause; + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + + puts("Board: TTControl Vision II CPU V"); + + switch (system_rev & 0xff) { + case CHIP_REV_3_0: + puts("3.0 ["); + break; + case CHIP_REV_2_5: + puts("2.5 ["); + break; + case CHIP_REV_2_0: + puts("2.0 ["); + break; + case CHIP_REV_1_1: + puts("1.1 ["); + break; + case CHIP_REV_1_0: + default: + puts("1.0 ["); + break; + } + + cause = src_regs->srsr; + switch (cause) { + case 0x0001: + puts("POR"); + break; + case 0x0009: + puts("RST"); + break; + case 0x0010: + case 0x0011: + puts("WDOG"); + break; + default: + printf("unknown 0x%x", cause); + } + puts("]\n"); + + return 0; +} + diff --git a/boards.cfg b/boards.cfg index 99096855a..62ffa420e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -47,6 +47,7 @@ jadecpu arm arm926ejs jadecpu syteco mb86r0x suen3 arm arm926ejs km_arm keymile kirkwood rd6281a arm arm926ejs - Marvell kirkwood mx51evk arm armv7 mx51evk freescale mx51 +vision2 arm armv7 vision2 ttcontrol mx51 actux1 arm ixp actux2 arm ixp actux3 arm ixp @@ -161,9 +162,7 @@ mgsuvd powerpc mpc8xx km8xx keymile KUP4K powerpc mpc8xx kup4k kup KUP4X powerpc mpc8xx kup4x kup ELPT860 powerpc mpc8xx elpt860 LEOX -CCM powerpc mpc8xx - siemens IAD210 powerpc mpc8xx - siemens -pcu_e powerpc mpc8xx - siemens QS823 powerpc mpc8xx qs850 snmc QS850 powerpc mpc8xx qs850 snmc QS860T powerpc mpc8xx qs860t snmc diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 6b611b148..1326c8fac 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -385,7 +385,6 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) bd_t *bd = gd->bd; char buf[32]; - print_num ("env_t", (ulong)bd->bi_env); print_num ("boot_params", (ulong)bd->bi_boot_params); print_num ("bi_memstart", bd->bi_memstart); print_num ("bi_memsize", bd->bi_memsize); diff --git a/common/cmd_elf.c b/common/cmd_elf.c index 104d6e68b..bf3261256 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -25,7 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; #endif int valid_elf_image (unsigned long addr); -unsigned long load_elf_image (unsigned long addr); +static unsigned long load_elf_image_phdr(unsigned long addr); +static unsigned long load_elf_image_shdr(unsigned long addr); /* Allow ports to override the default behavior */ __attribute__((weak)) @@ -61,19 +62,34 @@ int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned long addr; /* Address of the ELF image */ unsigned long rc; /* Return value from user code */ + char *sload, *saddr; /* -------------------------------------------------- */ int rcode = 0; - if (argc < 2) - addr = load_addr; + sload = saddr = NULL; + if (argc == 3) { + sload = argv[1]; + saddr = argv[2]; + } else if (argc == 2) { + if (argv[1][0] == '-') + sload = argv[1]; + else + saddr = argv[1]; + } + + if (saddr) + addr = simple_strtoul(saddr, NULL, 16); else - addr = simple_strtoul (argv[1], NULL, 16); + addr = load_addr; if (!valid_elf_image (addr)) return 1; - addr = load_elf_image (addr); + if (sload && sload[1] == 'p') + addr = load_elf_image_phdr(addr); + else + addr = load_elf_image_shdr(addr); printf ("## Starting application at 0x%08lx ...\n", addr); @@ -204,7 +220,7 @@ int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ if (valid_elf_image (addr)) { - addr = load_elf_image (addr); + addr = load_elf_image_shdr (addr); } else { puts ("## Not an ELF image, assuming binary\n"); /* leave addr as load_addr */ @@ -258,7 +274,33 @@ int valid_elf_image (unsigned long addr) * A very simple elf loader, assumes the image is valid, returns the * entry point address. * ====================================================================== */ -unsigned long load_elf_image (unsigned long addr) +static unsigned long load_elf_image_phdr(unsigned long addr) +{ + Elf32_Ehdr *ehdr; /* Elf header structure pointer */ + Elf32_Phdr *phdr; /* Program header structure pointer */ + int i; + + ehdr = (Elf32_Ehdr *) addr; + phdr = (Elf32_Phdr *) (addr + ehdr->e_phoff); + + /* Load each program header */ + for (i = 0; i < ehdr->e_phnum; ++i) { + void *dst = (void *) phdr->p_paddr; + void *src = (void *) addr + phdr->p_offset; + debug("Loading phdr %i to 0x%p (%i bytes)\n", + i, dst, phdr->p_filesz); + if (phdr->p_filesz) + memcpy(dst, src, phdr->p_filesz); + if (phdr->p_filesz != phdr->p_memsz) + memset(dst + phdr->p_filesz, 0x00, phdr->p_memsz - phdr->p_filesz); + flush_cache((unsigned long)dst, phdr->p_filesz); + ++phdr; + } + + return ehdr->e_entry; +} + +static unsigned long load_elf_image_shdr(unsigned long addr) { Elf32_Ehdr *ehdr; /* Elf header structure pointer */ Elf32_Shdr *shdr; /* Section header structure pointer */ @@ -312,9 +354,11 @@ unsigned long load_elf_image (unsigned long addr) /* ====================================================================== */ U_BOOT_CMD( - bootelf, 2, 0, do_bootelf, + bootelf, 3, 0, do_bootelf, "Boot from an ELF image in memory", - " [address] - load address of ELF image." + "[-p|-s] [address]\n" + "\t- load ELF image at [address] via program headers (-p)\n" + "\t or via section headers (-s)" ); U_BOOT_CMD( diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index c3d63b8a4..3d30c321d 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -837,6 +837,13 @@ static cmd_tbl_t cmd_env_sub[] = { U_BOOT_CMD_MKENT(set, CONFIG_SYS_MAXARGS, 0, do_env_set, "", ""), }; +#if !defined(CONFIG_RELOC_FIXUP_WORKS) +void env_reloc(void) +{ + fixup_cmdtable(cmd_env_sub, ARRAY_SIZE(cmd_env_sub)); +} +#endif + static int do_env (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { cmd_tbl_t *cp; diff --git a/common/cmd_spi.c b/common/cmd_spi.c index bafa217d0..8c623c9fc 100644 --- a/common/cmd_spi.c +++ b/common/cmd_spi.c @@ -47,7 +47,9 @@ /* * Values from last command. */ -static unsigned int device; +static unsigned int bus; +static unsigned int cs; +static unsigned int mode; static int bitlen; static uchar dout[MAX_SPI_BYTES]; static uchar din[MAX_SPI_BYTES]; @@ -78,8 +80,18 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((flag & CMD_FLAG_REPEAT) == 0) { - if (argc >= 2) - device = simple_strtoul(argv[1], NULL, 10); + if (argc >= 2) { + mode = CONFIG_DEFAULT_SPI_MODE; + bus = simple_strtoul(argv[1], &cp, 10); + if (*cp == ':') { + cs = simple_strtoul(cp+1, &cp, 10); + } else { + cs = bus; + bus = CONFIG_DEFAULT_SPI_BUS; + } + if (*cp == '.'); + mode = simple_strtoul(cp+1, NULL, 10); + } if (argc >= 3) bitlen = simple_strtoul(argv[2], NULL, 10); if (argc >= 4) { @@ -91,7 +103,7 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if(tmp > 15) tmp -= ('a' - 'A'); if(tmp > 15) { - printf("Hex conversion error on %c, giving up.\n", *cp); + printf("Hex conversion error on %c\n", *cp); return 1; } if((j % 2) == 0) @@ -103,24 +115,20 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } if ((bitlen < 0) || (bitlen > (MAX_SPI_BYTES * 8))) { - printf("Invalid bitlen %d, giving up.\n", bitlen); + printf("Invalid bitlen %d\n", bitlen); return 1; } - /* FIXME: Make these parameters run-time configurable */ - slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, device, 1000000, - CONFIG_DEFAULT_SPI_MODE); + slave = spi_setup_slave(bus, cs, 1000000, mode); if (!slave) { - printf("Invalid device %d, giving up.\n", device); + printf("Invalid device %d:%d\n", bus, cs); return 1; } - debug ("spi chipsel = %08X\n", device); - spi_claim_bus(slave); if(spi_xfer(slave, bitlen, dout, din, SPI_XFER_BEGIN | SPI_XFER_END) != 0) { - printf("Error with the SPI transaction.\n"); + printf("Error during SPI transaction\n"); rcode = 1; } else { for(j = 0; j < ((bitlen + 7) / 8); j++) { @@ -138,9 +146,11 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( sspi, 5, 1, do_spi, - "SPI utility commands", - "<device> <bit_len> <dout> - Send <bit_len> bits from <dout> out the SPI\n" - "<device> - Identifies the chip select of the device\n" + "SPI utility command", + "[<bus>:]<cs>[.<mode>] <bit_len> <dout> - Send and receive bits\n" + "<bus> - Identifies the SPI bus\n" + "<cs> - Identifies the chip select\n" + "<mode> - Identifies the SPI mode to use\n" "<bit_len> - Number of bits to send (base 10)\n" "<dout> - Hexadecimal string that gets sent" ); diff --git a/common/env_common.c b/common/env_common.c index a415ef8ef..88f068cc3 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -227,6 +227,11 @@ int env_import(const char *buf, int check) void env_relocate (void) { +#if !defined(CONFIG_RELOC_FIXUP_WORKS) + extern void env_reloc(void); + + env_reloc(); +#endif if (gd->env_valid == 0) { #if defined(CONFIG_ENV_IS_NOWHERE) /* Environment not changable */ set_default_env(NULL); diff --git a/common/env_mmc.c b/common/env_mmc.c index 14203b6e2..cc288d487 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -147,7 +147,6 @@ void env_relocate_spec(void) #if !defined(ENV_IS_EMBEDDED) static void use_default() { - puts ("*** Warning - bad CRC or MMC, using default environment\n\n"); - set_default_env(); + set_default_env(NULL); } #endif diff --git a/common/main.c b/common/main.c index 8d548dbc8..d97ccd7dd 100644 --- a/common/main.c +++ b/common/main.c @@ -518,9 +518,6 @@ void reset_cmd_timeout(void) } while (0) #define CTL_CH(c) ((c) - 'a' + 1) - -#define MAX_CMDBUF_SIZE CONFIG_SYS_CBSIZE - #define CTL_BACKSPACE ('\b') #define DEL ((char)255) #define DEL7 ((char)127) @@ -531,7 +528,7 @@ void reset_cmd_timeout(void) #define getcmd_cbeep() getcmd_putch('\a') #define HIST_MAX 20 -#define HIST_SIZE MAX_CMDBUF_SIZE +#define HIST_SIZE CONFIG_SYS_CBSIZE static int hist_max = 0; static int hist_add_idx = 0; @@ -947,7 +944,7 @@ int readline_into_buffer (const char *const prompt, char * buffer) { char *p = buffer; #ifdef CONFIG_CMDLINE_EDITING - unsigned int len=MAX_CMDBUF_SIZE; + unsigned int len = CONFIG_SYS_CBSIZE; int rc; static int initted = 0; diff --git a/common/serial.c b/common/serial.c index 25b235aa1..7bebc12a6 100644 --- a/common/serial.c +++ b/common/serial.c @@ -54,6 +54,7 @@ struct serial_device *__default_serial_console (void) #else #error "Bad CONFIG_CONS_INDEX." #endif +#else return &serial0_device; #endif #elif defined(CONFIG_MPC512X) diff --git a/doc/README.fsl-hwconfig b/doc/README.fsl-hwconfig new file mode 100644 index 000000000..03fea74db --- /dev/null +++ b/doc/README.fsl-hwconfig @@ -0,0 +1,21 @@ +Freescale-specific 'hwconfig' options. + +This file documents Freescale-specific key:value pairs for the 'hwconfig' +option. See README.hwconfig for general information about 'hwconfig'. + +audclk + Specific to the P1022DS reference board. + + This option specifies which of the two oscillator frequencies should be + routed to the Wolfson WM8776 codec. The ngPIXIS can be programmed to + route either a 11.2896MHz or a 12.288MHz clock. The default is + 12.288MHz. This option has two effects. First, the MUX on the board + will be programmed accordingly. Second, the clock-frequency property + in the codec node in the device tree will be updated to the correct + value. + + 'audclk:11' + Select the 11.2896MHz clock + + 'audclk:12' + Select the 12.288MHz clock diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 07d395d89..a0f455223 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,7 +27,7 @@ LIB := $(obj)libgpio.a COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o -COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o +COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o COBJS-$(CONFIG_S5P) += s5p_gpio.o diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mxc_gpio.c index b07f03815..663141f1b 100644 --- a/drivers/gpio/mx31_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -21,19 +21,29 @@ * MA 02111-1307 USA */ #include <common.h> -#include <asm/arch/mx31.h> +#ifdef CONFIG_MX31 #include <asm/arch/mx31-regs.h> +#endif +#ifdef CONFIG_MX51 +#include <asm/arch/imx-regs.h> +#endif +#include <asm/io.h> +#include <mxc_gpio.h> /* GPIO port description */ static unsigned long gpio_ports[] = { - [0] = GPIO1_BASE, - [1] = GPIO2_BASE, - [2] = GPIO3_BASE, + [0] = GPIO1_BASE_ADDR, + [1] = GPIO2_BASE_ADDR, + [2] = GPIO3_BASE_ADDR, +#ifdef CONFIG_MX51 + [3] = GPIO4_BASE_ADDR, +#endif }; -int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction) +int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction) { unsigned int port = gpio >> 5; + struct gpio_regs *regs; u32 l; if (port >= ARRAY_SIZE(gpio_ports)) @@ -41,22 +51,26 @@ int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction) gpio &= 0x1f; - l = __REG(gpio_ports[port] + GPIO_GDIR); + regs = (struct gpio_regs *)gpio_ports[port]; + + l = readl(®s->gpio_dir); + switch (direction) { - case MX31_GPIO_DIRECTION_OUT: + case MXC_GPIO_DIRECTION_OUT: l |= 1 << gpio; break; - case MX31_GPIO_DIRECTION_IN: + case MXC_GPIO_DIRECTION_IN: l &= ~(1 << gpio); } - __REG(gpio_ports[port] + GPIO_GDIR) = l; + writel(l, ®s->gpio_dir); return 0; } -void mx31_gpio_set(unsigned int gpio, unsigned int value) +void mxc_gpio_set(unsigned int gpio, unsigned int value) { unsigned int port = gpio >> 5; + struct gpio_regs *regs; u32 l; if (port >= ARRAY_SIZE(gpio_ports)) @@ -64,17 +78,20 @@ void mx31_gpio_set(unsigned int gpio, unsigned int value) gpio &= 0x1f; - l = __REG(gpio_ports[port] + GPIO_DR); + regs = (struct gpio_regs *)gpio_ports[port]; + + l = readl(®s->gpio_dr); if (value) l |= 1 << gpio; else l &= ~(1 << gpio); - __REG(gpio_ports[port] + GPIO_DR) = l; + writel(l, ®s->gpio_dr); } -int mx31_gpio_get(unsigned int gpio) +int mxc_gpio_get(unsigned int gpio) { unsigned int port = gpio >> 5; + struct gpio_regs *regs; u32 l; if (port >= ARRAY_SIZE(gpio_ports)) @@ -82,7 +99,9 @@ int mx31_gpio_get(unsigned int gpio) gpio &= 0x1f; - l = (__REG(gpio_ports[port] + GPIO_DR) >> gpio) & 0x01; + regs = (struct gpio_regs *)gpio_ports[port]; + + l = (readl(®s->gpio_dr) >> gpio) & 0x01; return l; } diff --git a/drivers/hwmon/ds1621.c b/drivers/hwmon/ds1621.c index d15a082df..5a2ea6289 100644 --- a/drivers/hwmon/ds1621.c +++ b/drivers/hwmon/ds1621.c @@ -22,7 +22,7 @@ */ /* - * Dallas Semiconductor's DS1621 Digital Thermometer and Thermostat. + * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat. */ #include <common.h> @@ -32,7 +32,7 @@ /* * Device code */ -#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */ +#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */ #define DTT_READ_TEMP 0xAA #define DTT_READ_COUNTER 0xA8 #define DTT_READ_SLOPE 0xA9 @@ -42,148 +42,147 @@ #define DTT_TEMP_LOW 0xA2 #define DTT_CONFIG 0xAC +/* + * Config register bits + */ +#define DTT_CONFIG_1SHOT 0x01 +#define DTT_CONFIG_POLARITY 0x02 +#define DTT_CONFIG_R0 0x04 /* ds1631 only */ +#define DTT_CONFIG_R1 0x08 /* ds1631 only */ +#define DTT_CONFIG_NVB 0x10 +#define DTT_CONFIG_TLF 0x20 +#define DTT_CONFIG_THF 0x40 +#define DTT_CONFIG_DONE 0x80 + + int dtt_read(int sensor, int reg) { - int dlen; - uchar data[2]; + int dlen; + uchar data[2]; - /* - * Calculate sensor address and command. - * - */ - sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1621*/ + /* Calculate sensor address and command */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1621*/ - /* - * Prepare to handle 2 byte result. - */ - if ((reg == DTT_READ_TEMP) || - (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW)) - dlen = 2; - else - dlen = 1; + /* Prepare to handle 2 byte result */ + switch(reg) { + case DTT_READ_TEMP: + case DTT_TEMP_HIGH: + case DTT_TEMP_LOW: + dlen = 2; + break; + default: + dlen = 1; + } - /* - * Now try to read the register. - */ - if (i2c_read(sensor, reg, 1, data, dlen) != 0) - return 1; + /* Now try to read the register */ + if (i2c_read(sensor, reg, 1, data, dlen) != 0) + return 1; - /* - * Handle 2 byte result. - */ - if (dlen == 2) - return ((int)((short)data[1] + (((short)data[0]) << 8))); + /* Handle 2 byte result */ + if (dlen == 2) + return (short)((data[0] << 8) | data[1]); - return (int)data[0]; -} /* dtt_read() */ + return (int)data[0]; +} int dtt_write(int sensor, int reg, int val) { - int dlen; - uchar data[2]; + int dlen; + uchar data[2]; + + /* Calculate sensor address and register */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); - /* - * Calculate sensor address and register. - * - */ - sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); + /* Handle various data sizes. */ + switch(reg) { + case DTT_READ_TEMP: + case DTT_TEMP_HIGH: + case DTT_TEMP_LOW: + dlen = 2; + data[0] = (char)((val >> 8) & 0xff); /* MSB first */ + data[1] = (char)(val & 0xff); + break; + case DTT_WRITE_START_CONV: + case DTT_WRITE_STOP_CONV: + dlen = 0; + data[0] = (char)0; + data[1] = (char)0; + break; + default: + dlen = 1; + data[0] = (char)(val & 0xff); + } - /* - * Handle various data sizes. - */ - if ((reg == DTT_READ_TEMP) || - (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW)) { - dlen = 2; - data[0] = (char)((val >> 8) & 0xff); /* MSB first */ - data[1] = (char)(val & 0xff); - } - else if ((reg == DTT_WRITE_START_CONV) || (reg == DTT_WRITE_STOP_CONV)) { - dlen = 0; - data[0] = (char)0; - data[1] = (char)0; - } - else { - dlen = 1; - data[0] = (char)(val & 0xff); - } + /* Write value to device */ + if (i2c_write(sensor, reg, 1, data, dlen) != 0) + return 1; - /* - * Write value to device. - */ - if (i2c_write(sensor, reg, 1, data, dlen) != 0) - return 1; + /* Poll NV memory busy bit in case write was to register stored in EEPROM */ + while(i2c_reg_read(sensor, DTT_CONFIG) & DTT_CONFIG_NVB) + ; - return 0; -} /* dtt_write() */ + return 0; +} static int _dtt_init(int sensor) { - int val; + int val; - /* - * Setup High Temp. - */ - val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80; - if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0) - return 1; - udelay(50000); /* Max 50ms */ + /* Setup High Temp */ + val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80; + if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0) + return 1; - /* - * Setup Low Temp - hysteresis. - */ - val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80; - if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0) - return 1; - udelay(50000); /* Max 50ms */ + /* Setup Low Temp - hysteresis */ + val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80; + if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0) + return 1; - /* - * Setup configuraton register - * - * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES - * - * We run in polled mode, since there isn't any way to know if this - * lousy device is ready to provide temperature readings on power up. - */ - val = 0x9; - if (dtt_write(sensor, DTT_CONFIG, val) != 0) - return 1; - udelay(50000); /* Max 50ms */ + /* + * Setup configuraton register + * + * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES + * + * We run in polled mode, since there isn't any way to know if this + * lousy device is ready to provide temperature readings on power up. + */ + val = 0x9; + if (dtt_write(sensor, DTT_CONFIG, val) != 0) + return 1; - return 0; -} /* _dtt_init() */ + return 0; +} int dtt_init (void) { - int i; - unsigned char sensors[] = CONFIG_DTT_SENSORS; + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; - for (i = 0; i < sizeof(sensors); i++) { - if (_dtt_init(sensors[i]) != 0) - printf("DTT%d: FAILED\n", i+1); - else - printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i])); - } + for (i = 0; i < sizeof(sensors); i++) { + if (_dtt_init(sensors[i]) != 0) + printf("DTT%d: FAILED\n", i + 1); + else + printf("DTT%d: %i C\n", i + 1, dtt_get_temp(sensors[i])); + } - return (0); -} /* dtt_init() */ + return (0); +} int dtt_get_temp(int sensor) { - int i; + int i; - /* - * Start a conversion, may take up to 1 second. - */ - dtt_write(sensor, DTT_WRITE_START_CONV, 0); - for (i = 0; i <= 10; i++) { - udelay(100000); - if (dtt_read(sensor, DTT_CONFIG) & 0x80) - break; - } + /* Start a conversion, may take up to 1 second. */ + dtt_write(sensor, DTT_WRITE_START_CONV, 0); + for (i = 0; i <= 10; i++) { + udelay(100000); + if (dtt_read(sensor, DTT_CONFIG) & DTT_CONFIG_DONE) + break; + } - return (dtt_read(sensor, DTT_READ_TEMP) / 256); -} /* dtt_get_temp() */ + return (dtt_read(sensor, DTT_READ_TEMP) / 256); +} diff --git a/drivers/misc/fsl_pmic.c b/drivers/misc/fsl_pmic.c index dca0a1d57..5ee1de176 100644 --- a/drivers/misc/fsl_pmic.c +++ b/drivers/misc/fsl_pmic.c @@ -46,6 +46,7 @@ void pmic_spi_free(struct spi_slave *slave) u32 pmic_reg(u32 reg, u32 val, u32 write) { u32 pmic_tx, pmic_rx; + u32 tmp; if (!slave) { slave = pmic_spi_probe(); @@ -65,7 +66,9 @@ u32 pmic_reg(u32 reg, u32 val, u32 write) pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF); - if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx, + tmp = cpu_to_be32(pmic_tx); + + if (spi_xfer(slave, 4 << 3, &tmp, &pmic_rx, SPI_XFER_BEGIN | SPI_XFER_END)) { spi_release_bus(slave); return -1; @@ -73,7 +76,8 @@ u32 pmic_reg(u32 reg, u32 val, u32 write) if (write) { pmic_tx &= ~(1 << 31); - if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx, + tmp = cpu_to_be32(pmic_tx); + if (spi_xfer(slave, 4 << 3, &tmp, &pmic_rx, SPI_XFER_BEGIN | SPI_XFER_END)) { spi_release_bus(slave); return -1; @@ -81,7 +85,7 @@ u32 pmic_reg(u32 reg, u32 val, u32 write) } spi_release_bus(slave); - return pmic_rx; + return cpu_to_be32(pmic_rx); } void pmic_reg_write(u32 reg, u32 value) diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c index d6c1a5f9d..c0900f978 100644 --- a/drivers/mtd/spi/spansion.c +++ b/drivers/mtd/spi/spansion.c @@ -52,6 +52,7 @@ #define SPSN_ID_S25FL128P 0x2018 #define SPSN_EXT_ID_S25FL128P_256KB 0x0300 #define SPSN_EXT_ID_S25FL128P_64KB 0x0301 +#define SPSN_EXT_ID_S25FL032P 0x4d00 #define SPANSION_SR_WIP (1 << 0) /* Write-in-Progress */ @@ -124,6 +125,14 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { .nr_sectors = 64, .name = "S25FL128P_256K", }, + { + .idcode1 = SPSN_ID_S25FL032A, + .idcode2 = SPSN_EXT_ID_S25FL032P, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 64, + .name = "S25FL032P", + }, }; static int spansion_wait_ready(struct spi_flash *flash, unsigned long timeout) @@ -262,7 +271,6 @@ int spansion_erase(struct spi_flash *flash, u32 offset, size_t len) return -1; } - len /= sector_size; cmd[0] = CMD_S25FLXX_SE; cmd[2] = 0x00; cmd[3] = 0x00; @@ -274,8 +282,8 @@ int spansion_erase(struct spi_flash *flash, u32 offset, size_t len) } ret = 0; - for (actual = 0; actual < len; actual++) { - cmd[1] = (offset / sector_size) + actual; + for (actual = 0; actual < len; actual += sector_size) { + cmd[1] = (offset + actual) >> 16; ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0); if (ret < 0) { @@ -298,7 +306,7 @@ int spansion_erase(struct spi_flash *flash, u32 offset, size_t len) } debug("SF: SPANSION: Successfully erased %u bytes @ 0x%x\n", - len * sector_size, offset); + len, offset); spi_release_bus(flash->spi); return ret; diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c index ff1df25a1..de3aeb810 100644 --- a/drivers/mtd/spi/winbond.c +++ b/drivers/mtd/spi/winbond.c @@ -27,6 +27,7 @@ #define WINBOND_ID_W25X16 0x3015 #define WINBOND_ID_W25X32 0x3016 #define WINBOND_ID_W25X64 0x3017 +#define WINBOND_ID_W25Q64 0x4017 #define WINBOND_SR_WIP (1 << 0) /* Write-in-Progress */ @@ -77,6 +78,14 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .nr_blocks = 128, .name = "W25X64", }, + { + .id = WINBOND_ID_W25Q64, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "W25Q64", + }, }; static int winbond_wait_ready(struct spi_flash *flash, unsigned long timeout) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 4b93e7b97..f96b21f7b 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -18,6 +18,7 @@ */ #include <common.h> +#include <watchdog.h> #ifdef CONFIG_MX31 #include <asm/arch/mx31.h> #else @@ -189,7 +190,8 @@ void serial_setbrg (void) int serial_getc (void) { - while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); + while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + WATCHDOG_RESET(); return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ } @@ -198,7 +200,8 @@ void serial_putc (const char c) __REG(UART_PHYS + UTXD) = c; /* wait for transmitter to be ready */ - while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)); + while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) + WATCHDOG_RESET(); /* If \n, also do \r */ if (c == '\n') diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index e15a63cac..d558137c9 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -23,6 +23,7 @@ #include <spi.h> #include <asm/errno.h> #include <asm/io.h> +#include <mxc_gpio.h> #ifdef CONFIG_MX27 /* i.MX27 has a completely wrong register layout and register definitions in the @@ -61,6 +62,7 @@ #define MXC_CSPICTRL_MAXBITS 0x1f #define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 static unsigned long spi_bases[] = { 0x43fa4000, @@ -68,9 +70,6 @@ static unsigned long spi_bases[] = { 0x53f84000, }; -#define OUT MX31_GPIO_DIRECTION_OUT -#define mxc_gpio_direction mx31_gpio_direction -#define mxc_gpio_set mx31_gpio_set #elif defined(CONFIG_MX51) #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> @@ -97,6 +96,7 @@ static unsigned long spi_bases[] = { #define MXC_CSPICTRL_RXOVF (1 << 6) #define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 32 /* Bit position inside CTRL register to be associated with SS */ #define MXC_CSPICTRL_CHAN 18 @@ -111,13 +111,12 @@ static unsigned long spi_bases[] = { CSPI2_BASE_ADDR, CSPI3_BASE_ADDR, }; -#define mxc_gpio_direction(gpio, dir) (0) -#define mxc_gpio_set(gpio, value) {} -#define OUT 1 #else #error "Unsupported architecture" #endif +#define OUT MXC_GPIO_DIRECTION_OUT + struct mxc_spi_slave { struct spi_slave slave; unsigned long base; @@ -126,6 +125,7 @@ struct mxc_spi_slave { u32 cfg_reg; #endif int gpio; + int ss_pol; }; static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) @@ -147,7 +147,7 @@ void spi_cs_activate(struct spi_slave *slave) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); if (mxcs->gpio > 0) - mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL); + mxc_gpio_set(mxcs->gpio, mxcs->ss_pol); } void spi_cs_deactivate(struct spi_slave *slave) @@ -155,7 +155,7 @@ void spi_cs_deactivate(struct spi_slave *slave) struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); if (mxcs->gpio > 0) mxc_gpio_set(mxcs->gpio, - !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL)); + !(mxcs->ss_pol)); } #ifdef CONFIG_MX51 @@ -217,7 +217,7 @@ static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, if (mode & SPI_CS_HIGH) ss_pol = 1; - if (!(mode & SPI_CPOL)) + if (mode & SPI_CPOL) sclkpol = 1; if (mode & SPI_CPHA) @@ -254,13 +254,15 @@ static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, } #endif -static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, - unsigned long flags) +int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, + const u8 *dout, u8 *din, unsigned long flags) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); + int nbytes = (bitlen + 7) / 8; + u32 data, cnt, i; - if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); + debug("%s: bitlen %d dout 0x%x din 0x%x\n", + __func__, bitlen, (u32)dout, (u32)din); mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | @@ -275,8 +277,46 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, reg_write(mxcs->base + MXC_CSPISTAT, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); - debug("Sending SPI 0x%x\n", data); - reg_write(mxcs->base + MXC_CSPITXDATA, data); + /* + * The SPI controller works only with words, + * check if less than a word is sent. + * Access to the FIFO is only 32 bit + */ + if (bitlen % 32) { + data = 0; + cnt = (bitlen % 32) / 8; + if (dout) { + for (i = 0; i < cnt; i++) { + data = (data << 8) | (*dout++ & 0xFF); + } + } + debug("Sending SPI 0x%x\n", data); + + reg_write(mxcs->base + MXC_CSPITXDATA, data); + nbytes -= cnt; + } + + data = 0; + + while (nbytes > 0) { + data = 0; + if (dout) { + /* Buffer is not 32-bit aligned */ + if ((unsigned long)dout & 0x03) { + data = 0; + for (i = 0; i < 4; i++, data <<= 8) { + data = (data << 8) | (*dout++ & 0xFF); + } + } else { + data = *(u32 *)dout; + data = cpu_to_be32(data); + } + dout += 4; + } + debug("Sending SPI 0x%x\n", data); + reg_write(mxcs->base + MXC_CSPITXDATA, data); + nbytes -= 4; + } /* FIFO is written, now starts the transfer setting the XCH bit */ reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | @@ -290,49 +330,78 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, reg_write(mxcs->base + MXC_CSPISTAT, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); - data = reg_read(mxcs->base + MXC_CSPIRXDATA); - debug("SPI Rx: 0x%x\n", data); + nbytes = (bitlen + 7) / 8; - if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); + cnt = nbytes % 32; + + if (bitlen % 32) { + data = reg_read(mxcs->base + MXC_CSPIRXDATA); + cnt = (bitlen % 32) / 8; + debug("SPI Rx unaligned: 0x%x\n", data); + if (din) { + for (i = 0; i < cnt; i++, data >>= 8) { + *din++ = data & 0xFF; + } + } + nbytes -= cnt; + } - return data; + while (nbytes > 0) { + u32 tmp; + tmp = reg_read(mxcs->base + MXC_CSPIRXDATA); + data = cpu_to_be32(tmp); + debug("SPI Rx: 0x%x 0x%x\n", tmp, data); + cnt = min(nbytes, sizeof(data)); + if (din) { + memcpy(din, &data, cnt); + din += cnt; + } + nbytes -= cnt; + } + + return 0; } + int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { - int n_blks = (bitlen + 31) / 32; - u32 *out_l, *in_l; - int i; + int n_bytes = (bitlen + 7) / 8; + int n_bits; + int ret; + u32 blk_size; + u8 *p_outbuf = (u8 *)dout; + u8 *p_inbuf = (u8 *)din; - if ((int)dout & 3 || (int)din & 3) { - printf("Error: unaligned buffers in: %p, out: %p\n", din, dout); - return 1; - } + if (!slave) + return -1; - /* This driver is currently partly broken, alert the user */ - if (bitlen > 16 && (bitlen % 32)) { - printf("Error: SPI transfer with bitlen=%d is broken.\n", - bitlen); - return 1; - } + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); - for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout; - i < n_blks; - i++, in_l++, out_l++, bitlen -= 32) { - u32 data = spi_xchg_single(slave, *out_l, bitlen, flags); + while (n_bytes > 0) { - /* Check if we're only transfering 8 or 16 bits */ - if (!i) { - if (bitlen < 9) - *(u8 *)din = data; - else if (bitlen < 17) - *(u16 *)din = data; - else - *in_l = data; - } + if (n_bytes < MAX_SPI_BYTES) + blk_size = n_bytes; + else + blk_size = MAX_SPI_BYTES; + + n_bits = blk_size * 8; + + ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0); + + if (ret) + return ret; + if (dout) + p_outbuf += blk_size; + if (din) + p_inbuf += blk_size; + n_bytes -= blk_size; + } + + if (flags & SPI_XFER_END) { + spi_cs_deactivate(slave); } return 0; @@ -380,8 +449,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; mxcs = malloc(sizeof(struct mxc_spi_slave)); - if (!mxcs) + if (!mxcs) { + puts("mxc_spi: SPI Slave not allocated !\n"); return NULL; + } ret = decode_cs(mxcs, cs); if (ret < 0) { @@ -394,6 +465,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, mxcs->slave.bus = bus; mxcs->slave.cs = cs; mxcs->base = spi_bases[bus]; + mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; #ifdef CONFIG_MX51 /* Can be used for i.MX31 too ? */ @@ -413,7 +485,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (mode & SPI_CPHA) ctrl_reg |= MXC_CSPICTRL_PHA; - if (!(mode & SPI_CPOL)) + if (mode & SPI_CPOL) ctrl_reg |= MXC_CSPICTRL_POL; if (mode & SPI_CS_HIGH) ctrl_reg |= MXC_CSPICTRL_SSPOL; diff --git a/include/commproc.h b/include/commproc.h index 762238ebe..a69a80913 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -579,34 +579,6 @@ typedef struct scc_enet { /*********************************************************************/ - -/*** CCM and PCU E ***********************************************/ - -/* The PCU E and CCM use the FEC on a MPC860T for Ethernet */ - -#if defined (CONFIG_PCU_E) || defined(CONFIG_CCM) - -#define FEC_ENET /* use FEC for EThernet */ -#undef SCC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -#endif /* CONFIG_PCU_E, CONFIG_CCM */ - /*** ELPT860 *********************************************************/ #ifdef CONFIG_ELPT860 diff --git a/include/compiler.h b/include/compiler.h index 23f4b834d..91dbe5699 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -47,7 +47,6 @@ #elif defined(__MACH__) # include <machine/endian.h> typedef unsigned long ulong; -typedef unsigned int uint; #endif typedef uint8_t __u8; diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h index 4d8378676..555145e18 100644 --- a/include/configs/BAB7xx.h +++ b/include/configs/BAB7xx.h @@ -269,6 +269,7 @@ * PCI stuff */ #define CONFIG_PCI /* include pci support */ +#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP /* pci plug-and-play */ #define CONFIG_PCI_HOST PCI_HOST_AUTO #undef CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/CCM.h b/include/configs/CCM.h deleted file mode 100644 index 3f4a2c103..000000000 --- a/include/configs/CCM.h +++ /dev/null @@ -1,488 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * configuration options, board specific, for Siemens Card Controller Module - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef CCM_80MHz /* define for 80 MHz CPU only */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU ... */ -#define CONFIG_CCM 1 /* on a Card Controller Module */ -#define CONFIG_MISC_INIT_R /* Call misc_init_r() */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -/* ENVIRONMENT */ - -#define CONFIG_BAUDRATE 19200 /* console baudrate in bps */ -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ - -#define CONFIG_IPADDR 192.168.0.42 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 0.0.0.0 -#define CONFIG_SERVERIP 192.168.0.254 - -#define CONFIG_HOSTNAME CCM - -#define CONFIG_LOADADDR 40180000 - -#undef CONFIG_BOOTARGS - -#define CONFIG_BOOTCOMMAND "setenv bootargs " \ - "mem=${mem} " \ - "root=/dev/ram rw ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ - "wt_8xx=timeout:3600; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ - -#undef CONFIG_STATUS_LED /* Status LED disabled */ - -#define CONFIG_PRAM 512 /* reserve 512kB "protected RAM"*/ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_SPI /* enable SPI driver */ -#define CONFIG_SPI_X /* 16 bit EEPROM addressing */ - -/* ---------------------------------------------------------------- - * Offset to initial SPI buffers in DPRAM (used if the environment - * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to - * use at an early stage. It is used between the two initialization - * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it - * far enough from the start of the data area (as well as from the - * stack pointer). - * ---------------------------------------------------------------- */ -#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 - -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-byte page size */ - - -#define CONFIG_MAC_PARTITION /* nod used yet */ -#define CONFIG_DOS_PARTITION - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -/* Ethernet hardware configuration done using port pins */ -#define CONFIG_SYS_PA_ETH_RESET 0x0200 /* PA 6 */ -#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */ -#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ -#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */ -#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */ -#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */ - -/* Ethernet settings: - * MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex - */ -#define CONFIG_SYS_ETH_MDDIS_VALUE 0 -#define CONFIG_SYS_ETH_CFG1_VALUE 1 -#define CONFIG_SYS_ETH_CFG2_VALUE 1 -#define CONFIG_SYS_ETH_CFG3_VALUE 1 - -/* PUMA configuration */ -#define CONFIG_SYS_PC_PUMA_PROG 0x0200 /* PC 6 */ -#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */ -#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Address accessed to reset the board - must not be mapped/assigned - */ -#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if 1 -/* Start port with environment in flash; switch to SPI EEPROM later */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#else -/* Final version: environment in EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_ENV_OFFSET 2048 -#define CONFIG_ENV_SIZE 2048 -#endif - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * we must activate GPL5 in the SIUMCR for CAN - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CONFIG_SYS_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CCM_80MHz */ - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#endif /* CCM_80MHz */ - -/*----------------------------------------------------------------------- - * - * Interrupt Levels - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2 and OR2 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR3 and OR3 (CAN Controller) - */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) - -/* - * BR4/OR4: PUMA Config - * - * Memory controller will be used in 2 modes: - * - * - "read" mode: - * BR4: 0x10100801 OR4: 0xffff8520 - * - "load" mode (chip select on UPM B): - * BR4: 0x101004c1 OR4: 0xffff8600 - * - * Default initialization is in "read" mode - */ -#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */ -#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */ -#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_2_CLK) -#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_2_CLK) - -#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V) -#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING) - -#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING) - -#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ -#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ - -/* - * BR5/OR5: PUMA: SMA Bus 8 Bit - * BR5: 0x10200401 OR5: 0xffe0010a - */ -#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */ -#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */ -#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) - -/* - * BR6/OR6: PUMA: SMA Bus 16 Bit - * BR6: 0x10600801 OR6: 0xffe0010a - */ -#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */ -#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */ -#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) - -/* - * BR7/OR7: PUMA: external Flash - * BR7: 0x10a00801 OR7: 0xfe00010a - */ -#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */ -#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */ -#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA) - - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h index 668cfa2eb..64512637d 100644 --- a/include/configs/CPC45.h +++ b/include/configs/CPC45.h @@ -467,6 +467,7 @@ *----------------------------------------------------------------------- */ #define CONFIG_PCI /* include pci support */ +#define CONFIG_SYS_EARLY_PCI_INIT #undef CONFIG_PCI_PNP #undef CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 8ffd4583b..95c0a9ffc 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Freescale Semiconductor, Inc. + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -74,6 +74,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ENABLE_36BIT_PHYS 1 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R 1 #define CONFIG_HWCONFIG #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ @@ -505,8 +506,8 @@ extern unsigned long get_clock_freq(void); #else #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x2000 #endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 2306e7f90..da826fc26 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -134,6 +134,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R +#define CONFIG_HWCONFIG #define CONFIG_FSL_NGPIXIS #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index d223a4d73..9184eeb56 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -399,6 +399,14 @@ #endif #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 @@ -607,14 +615,17 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=cs0_cs1\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "ubootaddr=" MK_STR(TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p4080ds/ramdisk.uboot\0" \ diff --git a/include/configs/eNET.h b/include/configs/eNET.h index da2a97d26..fc7c1c6ce 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -29,8 +29,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_RELOC_FIXUP_WORKS - /* * Stuff still to be dealt with - */ diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 49048563c..88c62d11e 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -66,13 +66,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 1dbafa052..62944a93f 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -183,7 +183,7 @@ #ifdef CONFIG_IMX31_PHYCORE_EET #define BOARD_LATE_INIT -#define CONFIG_MX31_GPIO 1 +#define CONFIG_MXC_GPIO #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index dedecd7fb..57955dfc3 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -63,13 +63,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 0414cc37a..4b4fb1a06 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -67,13 +67,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 2 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 86a4731a6..8864f3ab7 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -73,7 +73,7 @@ #define CONFIG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 2500000 -#define CONFIG_FSL_PMIC_MODE (SPI_CPOL | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) /* * MMC Configs diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h deleted file mode 100644 index 3aee206ad..000000000 --- a/include/configs/pcu_e.h +++ /dev/null @@ -1,550 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Workaround for layout bug on prototype board - */ -#define PCU_E_WITH_SWAPPED_CS 1 - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860T CPU */ -#define CONFIG_MPC860T 1 -#define CONFIG_PCU_E 1 /* ...on a PCU E board */ - -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ - -#define CONFIG_BAUDRATE 9600 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_SPI /* enable SPI driver */ -#define CONFIG_SPI_X /* 16 bit EEPROM addressing */ - -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - - -/* ---------------------------------------------------------------- - * Offset to initial SPI buffers in DPRAM (used if the environment - * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to - * use at an early stage. It is used between the two initialization - * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it - * far enough from the start of the data area (as well as from the - * stack pointer). - * ---------------------------------------------------------------- */ -#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -/* Ethernet hardware configuration done using port pins */ -#define CONFIG_SYS_PB_ETH_RESET 0x00000020 /* PB 26 */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */ -#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ -#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */ -#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */ -#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */ -#else /* XXX */ -#define CONFIG_SYS_PB_ETH_MDDIS 0x00000010 /* PB 27 */ -#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */ -#define CONFIG_SYS_PB_ETH_CFG1 0x00000200 /* PB 22 */ -#define CONFIG_SYS_PB_ETH_CFG2 0x00000400 /* PB 21 */ -#define CONFIG_SYS_PB_ETH_CFG3 0x00000800 /* PB 20 */ -#endif /* XXX */ - -/* Ethernet settings: - * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex - */ -#define CONFIG_SYS_ETH_MDDIS_VALUE 0 -#define CONFIG_SYS_ETH_CFG1_VALUE 1 -#define CONFIG_SYS_ETH_CFG2_VALUE 1 -#define CONFIG_SYS_ETH_CFG3_VALUE 1 - -/* PUMA configuration */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_PB_PUMA_PROG 0x00000010 /* PB 27 */ -#else /* XXX */ -#define CONFIG_SYS_PA_PUMA_PROG 0x4000 /* PA 1 */ -#endif /* XXX */ -#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */ -#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFE000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Address accessed to reset the board - must not be mapped/assigned - */ -#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* this is an ugly hack needed because of the silly non-constant address map */ -#define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size-flash_info[1].size) - -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 160 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#if 0 -/* Start port with environment in flash; switch to SPI EEPROM later */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */ -#define CONFIG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */ -#else -/* Final version: environment in EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_ENV_OFFSET 1024 -#define CONFIG_ENV_SIZE 1024 -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before - * running in RAM. - */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * External Arbitration max. priority (7), - * Debug pins configuration '11', - * Asynchronous external master enable. - */ -/* => 0x70600200 */ -#define CONFIG_SYS_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* 0x00004080 */ -#define CONFIG_SYS_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */ -#define CONFIG_SYS_PLPRCR \ - ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \ - ) - -#define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*50000000) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - * - * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz - */ -#define SCCR_MASK SCCR_EBDF11 -/* 0x01800000 */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000 | SCCR_DFLCD100 | \ - SCCR_DFALCD01) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - * - * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!! - * - * Don't expect the "date" command to work without a 32kHz clock input! - */ -/* 0x00C3 => 0x0003 */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0x0000 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMDS 0 - -/*----------------------------------------------------------------------- - * - * Interrupt Levels - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - second Flash bank optional - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */ -#else /* XXX */ -#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */ -#endif /* XXX */ - -/* - * used to re-map FLASH: restrict access enough but not too much to - * meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR) - -#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \ - CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ - CONFIG_SYS_OR_TIMING_FLASH) -/* 16 bit, bank valid */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_OR6_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) -#else /* XXX */ -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) -#endif /* XXX */ - -/* - * BR2/OR2: SDRAM - * - * Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */ -#else /* XXX */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */ -#endif /* XXX */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */ -#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */ - -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CONFIG_SYS_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* XXX */ -#define CONFIG_SYS_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#endif /* XXX */ - -/* - * BR3/OR3: CAN Controller - * BR3: 0x10000401 OR3: 0xffff818a - */ -#define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */ -#define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */ -#define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) -#else /* XXX */ -#define CONFIG_SYS_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) -#endif /* XXX */ - -/* - * BR4/OR4: PUMA Config - * - * Memory controller will be used in 2 modes: - * - * - "read" mode: - * BR4: 0x10100801 OR4: 0xffff8530 - * - "load" mode (chip select on UPM B): - * BR4: 0x101008c1 OR4: 0xffff8630 - * - * Default initialization is in "read" mode - */ -#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */ -#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */ -#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK) -#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK) - -#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \ - BR_PS_16 | BR_MS_UPMB | BR_V) -#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING) - -#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_BR3_PRELIM PUMA_CONF_BR_READ -#define CONFIG_SYS_OR3_PRELIM PUMA_CONF_OR_READ -#else /* XXX */ -#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ -#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ -#endif /* XXX */ - -/* - * BR5/OR5: PUMA: SMA Bus 8 Bit - * BR5: 0x10200401 OR5: 0xffe0010a - */ -#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */ -#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */ -#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) -#else /* XXX */ -#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) -#endif /* XXX */ - -/* - * BR6/OR6: PUMA: SMA Bus 16 Bit - * BR6: 0x10600801 OR6: 0xffe0010a - */ -#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */ -#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */ -#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) -#else /* XXX */ -#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) -#endif /* XXX */ - -/* - * BR7/OR7: PUMA: external Flash - * BR7: 0x10a00801 OR7: 0xfe00010a - */ -#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */ -#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */ -#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MPTPR 0x0200 - -/* - * MAMR settings for SDRAM - * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10, - * MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X - * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X - */ -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 0x30 /* = 48 */ - -#define CONFIG_SYS_MAMR ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \ - MAMR_AMA_TYPE_1 | \ - MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | \ - MAMR_WLFA_1X | \ - MAMR_TLFA_8X ) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/qong.h b/include/configs/qong.h index 7a68b7b97..cbb53dd3d 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -52,18 +52,18 @@ #define CONFIG_MXC_UART 1 #define CONFIG_SYS_MX31_UART1 1 -#define CONFIG_MX31_GPIO +#define CONFIG_MXC_GPIO #define CONFIG_MXC_SPI #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 100000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) /* FPGA */ #define CONFIG_QONG_FPGA 1 diff --git a/include/configs/vision2.h b/include/configs/vision2.h new file mode 100644 index 000000000..44a6f8be6 --- /dev/null +++ b/include/configs/vision2.h @@ -0,0 +1,214 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX51-3Stack Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> + +#define CONFIG_MX51 /* in a mx51 */ +#define CONFIG_L2_OFF + +#define CONFIG_MX51_HCLK_FREQ 24000000 +#define CONFIG_MX51_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define BOARD_LATE_INIT + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (2048 * 1024) + +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX51_UART3 +#define CONFIG_MXC_GPIO +#define CONFIG_MXC_SPI +#define CONFIG_HW_WATCHDOG + + /* + * SPI Configs + * */ +#define CONFIG_FSL_SF +#define CONFIG_CMD_SF + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + +/* + * Use gpio 4 pin 25 as chip select for SPI flash + * This corresponds to gpio 121 + */ +#define CONFIG_SPI_FLASH_CS (1 | (121 << 8)) +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 25000000 + +#define CONFIG_ENV_SPI_CS (1 | (121 << 8)) +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) +#define CONFIG_ENV_SIZE (4 * 1024) + +#define CONFIG_FSL_ENV_IN_SF +#define CONFIG_ENV_IS_IN_SPI_FLASH + +/* PMIC Controller */ +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 0 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 2500000 +#define CONFIG_FSL_PMIC_MODE SPI_MODE_0 +#define CONFIG_RTC_MC13783 + +/* + * MMC Configs + */ +#define CONFIG_FSL_ESDHC +#ifdef CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000) +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + +#define CONFIG_MMC + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_CMD_DATE + +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 3 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_SPI +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=0x90800000\0" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "Vision II U-boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x90000000 +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "Vision II U-boot > " + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024) +#define CONFIG_SYS_SDRAM_BASE 0x90000000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x1FFE8000 + +#ifndef CONFIG_SYS_ARM_WITHOUT_RELOC +#define CONFIG_SYS_INIT_RAM_END (64 * 1024) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET) +#undef CONFIG_SKIP_RELOCATE_UBOOT +#else +#define CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + 0x2000) +#endif + +#define CONFIG_BOARD_EARLY_INIT_F + +/* 166 MHz DDR RAM */ +#define CONFIG_SYS_DDR_CLKSEL 0 +#define CONFIG_SYS_CLKTL_CBCDR 0x19239100 + +#define CONFIG_SYS_NO_FLASH + +#endif /* __CONFIG_H */ diff --git a/include/mc13892.h b/include/mc13892.h index b29175741..791e3ec87 100644 --- a/include/mc13892.h +++ b/include/mc13892.h @@ -157,4 +157,7 @@ #define VSDSTBY (1 << 19) #define VSDMODE (1 << 20) +/* Reg Power Control 2*/ +#define WDIRESET (1 << 12) + #endif diff --git a/board/freescale/mx51evk/mx51evk.h b/include/mxc_gpio.h index 2854e71e8..002ba61e0 100644 --- a/board/freescale/mx51evk/mx51evk.h +++ b/include/mxc_gpio.h @@ -1,5 +1,6 @@ /* - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> * * See file CREDITS for list of people who contributed to this * project. @@ -20,31 +21,32 @@ * MA 02111-1307 USA */ -#ifndef __BOARD_FREESCALE_MX51_EVK_H__ -#define __BOARD_FREESCALE_MX51_EVK_H__ +#ifndef __MXC_GPIO_H +#define __MXC_GPIO_H -#ifndef __ASSEMBLY__ -struct io_board_ctrl { - u16 led_ctrl; /* 0x00 */ - u16 resv1[0x03]; - u16 sb_stat; /* 0x08 */ - u16 resv2[0x03]; - u16 int_stat; /* 0x10 */ - u16 resv3[0x07]; - u16 int_rest; /* 0x20 */ - u16 resv4[0x0B]; - u16 int_mask; /* 0x38 */ - u16 resv5[0x03]; - u16 id1; /* 0x40 */ - u16 resv6[0x03]; - u16 id2; /* 0x48 */ - u16 resv7[0x03]; - u16 version; /* 0x50 */ - u16 resv8[0x03]; - u16 id3; /* 0x58 */ - u16 resv9[0x03]; - u16 sw_reset; /* 0x60 */ +enum mxc_gpio_direction { + MXC_GPIO_DIRECTION_IN, + MXC_GPIO_DIRECTION_OUT, }; + +#ifdef CONFIG_MXC_GPIO +extern int mxc_gpio_direction(unsigned int gpio, + enum mxc_gpio_direction direction); +extern void mxc_gpio_set(unsigned int gpio, unsigned int value); +extern int mxc_gpio_get(unsigned int gpio); +#else +static inline int mxc_gpio_direction(unsigned int gpio, + enum mxc_gpio_direction direction) +{ + return 1; +} +static inline int mxc_gpio_get(unsigned int gpio) +{ + return 1; +} +static inline void mxc_gpio_set(unsigned int gpio, unsigned int value) +{ +} #endif #endif diff --git a/include/status_led.h b/include/status_led.h index b39ca6457..360195c96 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -190,22 +190,6 @@ void status_led_set (int led, int state); # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ -/***** PCU E and CCM ************************************************/ -#elif (defined(CONFIG_PCU_E) || defined(CONFIG_CCM)) - -# define STATUS_LED_PAR im_cpm.cp_pbpar -# define STATUS_LED_DIR im_cpm.cp_pbdir -# define STATUS_LED_ODR im_cpm.cp_pbodr -# define STATUS_LED_DAT im_cpm.cp_pbdat - -# define STATUS_LED_BIT 0x00010000 /* green LED is on PB.15 */ -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -# define STATUS_LED_STATE STATUS_LED_BLINKING - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - /***** ICU862 ********************************************************/ #elif defined(CONFIG_ICU862) @@ -270,7 +254,7 @@ void status_led_set (int led, int state); # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ /***** KUP4K, KUP4X ****************************************************/ -#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) || defined(CONFIG_CCM) +#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) # define STATUS_LED_PAR im_ioport.iop_papar # define STATUS_LED_DIR im_ioport.iop_padir diff --git a/lib/hashtable.c b/lib/hashtable.c index b747f1f79..57802cfb6 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -45,6 +45,9 @@ # include <linux/string.h> #endif +#ifndef CONFIG_ENV_MIN_ENTRIES /* minimum number of entries */ +#define CONFIG_ENV_MIN_ENTRIES 64 +#endif #ifndef CONFIG_ENV_MAX_ENTRIES /* maximum number of entries */ #define CONFIG_ENV_MAX_ENTRIES 512 #endif @@ -647,13 +650,14 @@ int himport_r(struct hsearch_data *htab, * (CONFIG_ENV_SIZE). This heuristics will result in * unreasonably large numbers (and thus memory footprint) for * big flash environments (>8,000 entries for 64 KB - * envrionment size), so we clip it to a reasonable value - * (which can be overwritten in the board config file if - * needed). + * envrionment size), so we clip it to a reasonable value. + * On the other hand we need to add some more entries for free + * space when importing very small buffers. Both boundaries can + * be overwritten in the board config file if needed. */ if (!htab->table) { - int nent = size / 8; + int nent = CONFIG_ENV_MIN_ENTRIES + size / 8; if (nent > CONFIG_ENV_MAX_ENTRIES) nent = CONFIG_ENV_MAX_ENTRIES; @@ -27,6 +27,7 @@ _depend: $(obj).depend $(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(SRCS) $(HOSTSRCS) @rm -f $@ + @touch $@ @for f in $(SRCS); do \ g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \ $(CC) -M $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \ |