diff options
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/denali_data_eye.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/denali_data_eye.c b/arch/powerpc/cpu/ppc4xx/denali_data_eye.c index 9bba0caec..19b65be61 100644 --- a/arch/powerpc/cpu/ppc4xx/denali_data_eye.c +++ b/arch/powerpc/cpu/ppc4xx/denali_data_eye.c @@ -317,7 +317,7 @@ void denali_core_search_data_eye(void) val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); mtdcr(ddrcfgd, val); - debug("DDR0_09=0x%08lx\n", val); + debug("DDR0_09=0x%08x\n", val); /* -----------------------------------------------------------+ * Set 'dqs_out_shift' = wr_dqs_shift + 32 @@ -327,7 +327,7 @@ void denali_core_search_data_eye(void) val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); mtdcr(ddrcfgd, val); - debug("DDR0_22=0x%08lx\n", val); + debug("DDR0_22=0x%08x\n", val); /* -----------------------------------------------------------+ * Set 'dll_dqs_delay_X'. @@ -337,7 +337,7 @@ void denali_core_search_data_eye(void) val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); mtdcr(ddrcfgd, val); - debug("DDR0_17=0x%08lx\n", val); + debug("DDR0_17=0x%08x\n", val); /* dll_dqs_delay_1 to dll_dqs_delay_4 */ mtdcr(ddrcfga, DDR0_18); @@ -347,7 +347,7 @@ void denali_core_search_data_eye(void) | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); mtdcr(ddrcfgd, val); - debug("DDR0_18=0x%08lx\n", val); + debug("DDR0_18=0x%08x\n", val); /* dll_dqs_delay_5 to dll_dqs_delay_8 */ mtdcr(ddrcfga, DDR0_19); @@ -357,7 +357,7 @@ void denali_core_search_data_eye(void) | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); mtdcr(ddrcfgd, val); - debug("DDR0_19=0x%08lx\n", val); + debug("DDR0_19=0x%08x\n", val); /* -----------------------------------------------------------+ * Assert 'start' parameter. |