diff options
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/fdt.c | 23 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 15 |
3 files changed, 37 insertions, 9 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index f1f80f7ae..6aca166a9 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -392,6 +392,12 @@ int cpu_init_r(void) puts("enabled\n"); } #elif defined(CONFIG_BACKSIDE_L2_CACHE) + if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || + (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) { + puts("N/A\n"); + goto skip_l2; + } + u32 l2cfg0 = mfspr(SPRN_L2CFG0); /* invalidate the L2 cache */ @@ -412,6 +418,8 @@ int cpu_init_r(void) ; printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); } + +skip_l2: #else puts("disabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 812bb3f87..c49f59b83 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -228,6 +228,12 @@ static inline void ft_fixup_l2cache(void *blob) u32 *ph; u32 l2cfg0 = mfspr(SPRN_L2CFG0); u32 size, line_size, num_ways, num_sets; + int has_l2 = 1; + + /* P2040/P2040E has no L2, so dont set any L2 props */ + if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || + (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) + has_l2 = 0; size = (l2cfg0 & 0x3fff) * 64 * 1024; num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; @@ -250,21 +256,22 @@ static inline void ft_fixup_l2cache(void *blob) goto next; } + if (has_l2) { #ifdef CONFIG_SYS_CACHE_STASHING - { u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); if (reg) fdt_setprop_cell(blob, l2_off, "cache-stash-id", (*reg * 2) + 32 + 1); - } #endif - fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); - fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size); - fdt_setprop_cell(blob, l2_off, "cache-size", size); - fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); - fdt_setprop_cell(blob, l2_off, "cache-level", 2); - fdt_setprop(blob, l2_off, "compatible", "cache", 6); + fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, l2_off, "cache-block-size", + line_size); + fdt_setprop_cell(blob, l2_off, "cache-size", size); + fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); + fdt_setprop_cell(blob, l2_off, "cache-level", 2); + fdt_setprop(blob, l2_off, "compatible", "cache", 6); + } if (l3_off < 0) { ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 56a853ee5..6678ed411 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * Kumar Gala <kumar.gala@freescale.com> * * See file CREDITS for list of people who contributed to this @@ -144,6 +144,18 @@ __secondary_start_page: #endif #ifdef CONFIG_BACKSIDE_L2_CACHE + /* skip L2 setup on P2040/P2040E as they have no L2 */ + mfspr r2,SPRN_SVR + lis r3,SVR_P2040@h + ori r3,r3,SVR_P2040@l + cmpw r2,r3 + beq 3f + + lis r3,SVR_P2040_E@h + ori r3,r3,SVR_P2040_E@l + cmpw r2,r3 + beq 3f + /* Enable/invalidate the L2 cache */ msync lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h @@ -169,6 +181,7 @@ __secondary_start_page: andis. r1,r3,L2CSR0_L2E@h beq 2b #endif +3: #define EPAPR_MAGIC (0x45504150) #define ENTRY_ADDR_UPPER 0 |