diff options
50 files changed, 2311 insertions, 332 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index ba83f71c3..d7cd09c13 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1011,6 +1011,7 @@ Nobuhiro Iwamatsu <iwamatsu@nigauri.org> SH7763RDP SH7763 RSK7203 SH7203 AP325RXA SH7723 + SHMIN SH7706 Mark Jonas <mark.jonas@de.bosch.com> @@ -1033,6 +1034,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org> BF518F-EZBRD BF518 BF526-EZBRD BF526 + BF527-AD7160-EVAL BF527 BF527-EZKIT BF527 BF527-EZKIT-V2 BF527 BF527-SDP BF527 @@ -1044,52 +1046,46 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org> BF548-EZKIT BF548 BF561-EZKIT BF561 - BF527-AD7160-EVAL BF527 +Brent Kandetzki <brentk@teleco.com> -Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> -Blackfin Team <u-boot-devel@blackfin.uclinux.org> + IP04 BF532 - CM-BF527 BF527 - CM-BF533 BF533 - CM-BF537E BF537 - CM-BF537U BF537 - CM-BF548 BF548 - CM-BF561 BF561 - TCM-BF518 BF518 - TCM-BF537 BF537 +Peter Meerwald <devel@bct-electronic.com> -Martin Strubel <strubel@section5.ch> -Blackfin Team <u-boot-devel@blackfin.uclinux.org> + bct-brettl2 BF536 - BF537-minotaur BF537 - BF537-srv1 BF537 +I-SYST Micromodule <support@i-syst.com> + + IBF-DSP561 BF561 Wojtek Skulski <skulski@pas.rochester.edu> Wojtek Skulski <info@skutek.com> -Blackfin Team <u-boot-devel@blackfin.uclinux.org> Benjamin Matthews <mben12@gmail.com> BlackStamp BF533 BlackVME BF561 -I-SYST Micromodule <support@i-syst.com> -Blackfin Team <u-boot-devel@blackfin.uclinux.org> +Martin Strubel <strubel@section5.ch> - IBF-DSP561 BF561 + BF537-minotaur BF537 + BF537-srv1 BF537 + +Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> + + CM-BF527 BF527 + CM-BF533 BF533 + CM-BF537E BF537 + CM-BF537U BF537 + CM-BF548 BF548 + CM-BF561 BF561 + TCM-BF518 BF518 + TCM-BF537 BF537 Valentin Yakovenkov <yakovenkov@niistt.ru> Anton Shurpin <shurpin.aa@niistt.ru> BF561-ACVILON BF561 -Brent Kandetzki <brentk@teleco.com> - - IP04 BF532 - -Peter Meerwald <devel@bct-electronic.com> - - bct-brettl2 BF536 - ######################################################################### # End of MAINTAINERS list # ######################################################################### @@ -865,6 +865,18 @@ The following options need to be configured: Define this to use i/o functions instead of macros (some hardware wont work with macros) + CONFIG_FTGMAC100 + Support for Faraday's FTGMAC100 Gigabit SoC Ethernet + + CONFIG_FTGMAC100_EGIGA + Define this to use GE link update with gigabit PHY. + Define this if FTGMAC100 is connected to gigabit PHY. + If your system has 10/100 PHY only, it might not occur + wrong behavior. Because PHY usually return timeout or + useless data when polling gigabit status and gigabit + control registers. This behavior won't affect the + correctnessof 10/100 link speed update. + CONFIG_SMC911X Support for SMSC's LAN911x and LAN921x chips diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c index e9d53c1af..5a1321128 100644 --- a/arch/microblaze/cpu/interrupts.c +++ b/arch/microblaze/cpu/interrupts.c @@ -41,8 +41,11 @@ void enable_interrupts (void) int disable_interrupts (void) { + unsigned int msr; + + MFS(msr, rmsr); MSRCLR(0x2); - return 0; + return (msr & 0x2) != 0; } #ifdef CONFIG_SYS_INTC_0 diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index eeef579dc..b06212efd 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -90,16 +90,18 @@ void board_init (void) { bd_t *bd; init_fnc_t **init_fnc_ptr; - gd = (gd_t *) CONFIG_SYS_GBL_DATA_OFFSET; + gd = (gd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET); + bd = (bd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \ + - GENERATED_BD_INFO_SIZE); char *s; #if defined(CONFIG_CMD_FLASH) ulong flash_size = 0; #endif asm ("nop"); /* FIXME gd is not initialize - wait */ memset ((void *)gd, 0, GENERATED_GBL_DATA_SIZE); - gd->bd = (bd_t *) (gd + 1); /* At end of global data */ + memset ((void *)bd, 0, GENERATED_BD_INFO_SIZE); + gd->bd = bd; gd->baudrate = CONFIG_BAUDRATE; - bd = gd->bd; bd->bi_baudrate = CONFIG_BAUDRATE; bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c index 206c47664..9f8f8fa18 100644 --- a/arch/powerpc/cpu/ppc4xx/miiphy.c +++ b/arch/powerpc/cpu/ppc4xx/miiphy.c @@ -100,7 +100,7 @@ int phy_setup_aneg (char *devname, unsigned char addr) u16 anar = 0x0000; if (exsr & ESTATUS_1000XF) - anar |= ADVERTISE_1000XFULL); + anar |= ADVERTISE_1000XFULL; if (exsr & ESTATUS_1000XH) anar |= ADVERTISE_1000XHALF; diff --git a/arch/sh/include/asm/cpu_sh3.h b/arch/sh/include/asm/cpu_sh3.h index 6db38a2f8..385f5dc8e 100644 --- a/arch/sh/include/asm/cpu_sh3.h +++ b/arch/sh/include/asm/cpu_sh3.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * (C) Copyright 2007-2009 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> * * This program is free software; you can redistribute it and/or @@ -31,7 +31,9 @@ #define CACHE_OC_NUM_ENTRIES 256 #define CACHE_OC_ENTRY_SHIFT 4 -#if defined(CONFIG_CPU_SH7710) +#if defined(CONFIG_CPU_SH7706) +#include <asm/cpu_sh7706.h> +#elif defined(CONFIG_CPU_SH7710) #include <asm/cpu_sh7710.h> #elif defined(CONFIG_CPU_SH7720) #include <asm/cpu_sh7720.h> diff --git a/arch/sh/include/asm/cpu_sh7706.h b/arch/sh/include/asm/cpu_sh7706.h new file mode 100644 index 000000000..d093f88d4 --- /dev/null +++ b/arch/sh/include/asm/cpu_sh7706.h @@ -0,0 +1,53 @@ +#ifndef _ASM_CPU_SH7706_H_ +#define _ASM_CPU_SH7706_H_ + +#define CACHE_OC_NUM_WAYS 4 +#define CCR_CACHE_INIT 0x0000000D + +/* MMU and Cache control */ +#define MMUCR 0xFFFFFFE0 +#define CCR 0xFFFFFFEC + +/* PFC */ +#define PACR 0xA4050100 +#define PBCR 0xA4050102 +#define PCCR 0xA4050104 +#define PETCR 0xA4050106 + +/* Port Data Registers */ +#define PADR 0xA4050120 +#define PBDR 0xA4050122 +#define PCDR 0xA4050124 + +/* BSC */ +#define FRQCR 0xffffff80 +#define BCR1 0xffffff60 +#define BCR2 0xffffff62 +#define WCR1 0xffffff64 +#define WCR2 0xffffff66 +#define MCR 0xffffff68 + +/* SDRAM controller */ +#define DCR 0xffffff6a +#define RTCSR 0xffffff6e +#define RTCNT 0xffffff70 +#define RTCOR 0xffffff72 +#define RFCR 0xffffff74 +#define SDMR 0xFFFFD000 +#define CS3_R 0xFFFFE460 + +/* SCIF */ +#define SCSMR_2 0xA4000150 +#define SCIF0_BASE SCSMR_2 + +/* Timer */ +#define TSTR0 0xFFFFFE92 +#define TSTR TSTR0 +#define TCNT0 0xFFFFFE98 +#define TCR0 0xFFFFFE9C + +/* On chip oscillator circuits */ +#define WTCNT 0xFFFFFF84 +#define WTCSR 0xFFFFFF86 + +#endif /* _ASM_CPU_SH7706_H_ */ diff --git a/arch/sh/include/asm/cpu_sh7722.h b/arch/sh/include/asm/cpu_sh7722.h index 0975b78e9..3157dcbf1 100644 --- a/arch/sh/include/asm/cpu_sh7722.h +++ b/arch/sh/include/asm/cpu_sh7722.h @@ -325,44 +325,6 @@ #define SPICR1 0xA4420030 /* SCIF */ -/* -#define SCSMR 0xFFE00000 -#define SCBRR 0xFFE00004 -#define SCSCR 0xFFE00008 -#define SCFTDR 0xFFE0000C -#define SCFSR 0xFFE00010 -#define SCFRDR 0xFFE00014 -#define SCFCR 0xFFE00018 -#define SCFDR 0xFFE0001C -#define SCLSR 0xFFE00024 -#define SCSMR1 0xFFE10000 -#define SCBRR1 0xFFE10004 -#define SCSCR1 0xFFE10008 -#define SCFTDR1 0xFFE1000C -#define SCFSR1 0xFFE10010 -#define SCFRDR1 0xFFE10014 -#define SCFCR1 0xFFE10018 -#define SCFDR1 0xFFE1001C -#define SCLSR1 0xFFE10024 -#define SCSMR2 0xFFE20000 -#define SCBRR2 0xFFE20004 -#define SCSCR2 0xFFE20008 -#define SCFTDR2 0xFFE2000C -#define SCFSR2 0xFFE20010 -#define SCFRDR2 0xFFE20014 -#define SCFCR2 0xFFE20018 -#define SCFDR2 0xFFE2001C -#define SCLSR2 0xFFE20024 -#define SCSMR3 0xFFE30000 -#define SCBRR3 0xFFE30004 -#define SCSCR3 0xFFE30008 -#define SCFTDR3 0xFFE3000C -#define SCFSR3 0xFFE30010 -#define SCFRDR3 0xFFE30014 -#define SCFCR3 0xFFE30018 -#define SCFDR3 0xFFE3001C -#define SCLSR3 0xFFE30024 -*/ #define SCIF0_BASE 0xFFE00000 /* SIM */ diff --git a/arch/sh/include/asm/cpu_sh7750.h b/arch/sh/include/asm/cpu_sh7750.h index 4e43a465e..b3e84244f 100644 --- a/arch/sh/include/asm/cpu_sh7750.h +++ b/arch/sh/include/asm/cpu_sh7750.h @@ -166,26 +166,10 @@ /* SCI */ #define SCSMR1 0xFFE00000 -#define SCBRR1 0xFFE00004 -#define SCSCR1 0xFFE00008 -#define SCTDR1 0xFFE0000C -#define SCSSR1 0xFFE00010 -#define SCRDR1 0xFFE00014 -#define SCSCMR1 0xFFE00018 -#define SCSPTR1 0xFFE0001C #define SCF0_BASE SCSMR1 /* SCIF */ #define SCSMR2 0xFFE80000 -#define SCBRR2 0xFFE80004 -#define SCSCR2 0xFFE80008 -#define SCFTDR2 0xFFE8000C -#define SCFSR2 0xFFE80010 -#define SCFRDR2 0xFFE80014 -#define SCFCR2 0xFFE80018 -#define SCFDR2 0xFFE8001C -#define SCSPTR2 0xFFE80020 -#define SCLSR2 0xFFE80024 #define SCIF1_BASE SCSMR2 /* H-UDI */ diff --git a/arch/sh/include/asm/cpu_sh7780.h b/arch/sh/include/asm/cpu_sh7780.h index d4f824e71..e9c59fe24 100644 --- a/arch/sh/include/asm/cpu_sh7780.h +++ b/arch/sh/include/asm/cpu_sh7780.h @@ -333,27 +333,8 @@ #define RYRAR 0xFFE80054 /* Serial Communication Interface with FIFO */ -#define SCIF0_BASE SCSMR0 #define SCSMR0 0xFFE00000 -#define SCBRR0 0xFFE00004 -#define SCSCR0 0xFFE00008 -#define SCFSR0 0xFFE00010 -#define SCFCR0 0xFFE00018 -#define SCTFDR0 0xFFE0001C -#define SCRFDR0 0xFFE00020 -#define SCSPTR0 0xFFE00024 -#define SCLSR0 0xFFE00028 -#define SCRER0 0xFFE0002C -#define SCSMR1 0xFFE10000 -#define SCBRR1 0xFFE10004 -#define SCSCR1 0xFFE10008 -#define SCFSR1 0xFFE10010 -#define SCFCR1 0xFFE10018 -#define SCTFDR1 0xFFE1001C -#define SCRFDR1 0xFFE10020 -#define SCSPTR1 0xFFE10024 -#define SCLSR1 0xFFE10028 -#define SCRER1 0xFFE1002C +#define SCIF0_BASE SCSMR0 /* Serial I/O with FIFO */ #define SIMDR 0xFFE20000 diff --git a/arch/sh/include/asm/zimage.h b/arch/sh/include/asm/zimage.h new file mode 100644 index 000000000..33a680b68 --- /dev/null +++ b/arch/sh/include/asm/zimage.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2010 + * Renesas Solutions Corp. + * Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ZIMAGE_H_ +#define _ASM_ZIMAGE_H_ + +#define MOUNT_ROOT_RDONLY 0x000 +#define RAMDISK_FLAGS 0x004 +#define ORIG_ROOT_DEV 0x008 +#define LOADER_TYPE 0x00c +#define INITRD_START 0x010 +#define INITRD_SIZE 0x014 +#define COMMAND_LINE 0x100 + +#define RD_PROMPT (1<<15) +#define RD_DOLOAD (1<<14) +#define CMD_ARG_RD_PROMPT "prompt_ramdisk=" +#define CMD_ARG_RD_DOLOAD "load_ramdisk=" + +#endif diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index 7f6039699..c0670cbc8 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -31,6 +31,9 @@ COBJS-y += time_sh2.o else COBJS-y += time.o endif +ifeq ($(CONFIG_CMD_SH_ZIMAGEBOOT),y) +COBJS-y += zimageboot.o +endif SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 3d201b2e5..cdac3826c 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007,2008 + * Copyright (C) 2007, 2008, 2010 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * * This program is free software; you can redistribute it and/or @@ -46,7 +46,11 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; static int sh_flash_init(void) { gd->bd->bi_flashsize = flash_init(); - printf("FLASH: %ldMB\n", gd->bd->bi_flashsize / (1024*1024)); + + if (gd->bd->bi_flashsize >= (1024 * 1024)) + printf("FLASH: %ldMB\n", gd->bd->bi_flashsize / (1024*1024)); + else + printf("FLASH: %ldKB\n", gd->bd->bi_flashsize / 1024); return 0; } diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index 19b3a9402..57273fa44 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -27,6 +27,7 @@ #include <common.h> #include <command.h> #include <asm/byteorder.h> +#include <asm/zimage.h> #ifdef CONFIG_SYS_DEBUG static void hexdump(unsigned char *buf, int len) @@ -43,19 +44,6 @@ static void hexdump(unsigned char *buf, int len) } #endif -#define MOUNT_ROOT_RDONLY 0x000 -#define RAMDISK_FLAGS 0x004 -#define ORIG_ROOT_DEV 0x008 -#define LOADER_TYPE 0x00c -#define INITRD_START 0x010 -#define INITRD_SIZE 0x014 -#define COMMAND_LINE 0x100 - -#define RD_PROMPT (1<<15) -#define RD_DOLOAD (1<<14) -#define CMD_ARG_RD_PROMPT "prompt_ramdisk=" -#define CMD_ARG_RD_DOLOAD "load_ramdisk=" - #ifdef CONFIG_SH_SDRAM_OFFSET #define GET_INITRD_START(initrd, linux) (initrd - linux + CONFIG_SH_SDRAM_OFFSET) #else @@ -94,13 +82,12 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1; - /* Setup parameters */ - memset(param, 0, size); /* Clear zero page */ + /* Clear zero page */ + memset(param, 0, size); /* Set commandline */ strcpy(cmdline, bootargs); - sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10); /* Initrd */ if (images->rd_start || images->rd_end) { unsigned long ramdisk_flags = 0; @@ -128,7 +115,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima /* Boot kernel */ kernel(); - /* does not return */ + /* does not return */ return 1; } diff --git a/arch/sh/lib/zimageboot.c b/arch/sh/lib/zimageboot.c new file mode 100644 index 000000000..dd413c0f7 --- /dev/null +++ b/arch/sh/lib/zimageboot.c @@ -0,0 +1,80 @@ +/* + * (C) Copyright 2010 + * Renesas Solutions Corp. + * Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Linux SuperH zImage loading and boot + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/zimage.h> + +int do_sh_zimageboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ulong (*zboot_entry)(int, char * const []) = NULL; + char *s0, *s1; + unsigned char *param = NULL; + char *cmdline; + char *bootargs; + + disable_interrupts(); + + if (argc >= 3) { + /* argv[1] holds the address of the zImage */ + s0 = argv[1]; + /* argv[2] holds the address of zero page */ + s1 = argv[2]; + } else { + goto exit; + } + + if (s0) + zboot_entry = (ulong (*)(int, char * const []))simple_strtoul(s0, NULL, 16); + + /* empty_zero_page */ + if (s1) + param = (unsigned char*)simple_strtoul(s1, NULL, 16); + + /* Linux kernel command line */ + cmdline = (char *)param + COMMAND_LINE; + bootargs = getenv("bootargs"); + + /* Clear zero page */ + memset(param, 0, 0x1000); + + /* Set commandline */ + strcpy(cmdline, bootargs); + + /* Boot */ + zboot_entry(0, NULL); + +exit: + return -1; +} + +U_BOOT_CMD( + zimageboot, 3, 0, do_sh_zimageboot, + "Boot zImage for Renesas SH", + "" +); diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S index 680feaa6a..8b7bfce63 100644 --- a/board/amcc/canyonlands/init.S +++ b/board/amcc/canyonlands/init.S @@ -80,7 +80,7 @@ tlbtab: #if !defined(CONFIG_ARCHES) /* TLB-entry for NAND */ - tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG) + tlbentry(CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG) /* TLB-entry for CPLD */ tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG) diff --git a/board/shmin/Makefile b/board/shmin/Makefile new file mode 100644 index 000000000..06888cdd6 --- /dev/null +++ b/board/shmin/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2010 Nobuhiro Iwamatsu +# Copyright (C) 2008 Renesas Solutions Corp. +# +# u-boot/board/shmin/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).o + +OBJS := shmin.o +SOBJS := lowlevel_init.o + +LIB := $(addprefix $(obj),$(LIB)) +OBJS := $(addprefix $(obj),$(OBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/shmin/config.mk b/board/shmin/config.mk new file mode 100644 index 000000000..0c7605e7f --- /dev/null +++ b/board/shmin/config.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2010 Nobuhiro Iwamatsu +# +# u-boot/board/shmin/config.mk +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# + +CONFIG_SYS_TEXT_BASE = 0x8DFB0000 diff --git a/board/shmin/lowlevel_init.S b/board/shmin/lowlevel_init.S new file mode 100644 index 000000000..b29da35a9 --- /dev/null +++ b/board/shmin/lowlevel_init.S @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008, 2010 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +#include <asm/processor.h> +#include <asm/macro.h> + + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + /* Use setting of original bootloader */ + rts + nop + .align 2 diff --git a/board/shmin/shmin.c b/board/shmin/shmin.c new file mode 100644 index 000000000..8742f1021 --- /dev/null +++ b/board/shmin/shmin.c @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2007 - 2010 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * + * board/shmin/shmin.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Copy board_flash_get_legacy() from board/freescale/m54455evb/m54455evb.c + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/processor.h> + +int checkboard(void) +{ + puts("BOARD: T-SH7706LAN "); + if(readb(0xb0008006) == 0xab) + puts("v2\n"); + else + puts("v1\n"); + return 0; +} + +int board_init(void) +{ + writew(0x2980, BCR2); + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state(unsigned short value) +{ + +} + +#if defined(CONFIG_FLASH_CFI_LEGACY) +#include <flash.h> +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + int sect[] = CONFIG_SYS_ATMEL_SECT; + int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ; + int i, j, k; + + if (base != CONFIG_SYS_ATMEL_BASE) + return 0; + + info->flash_id = 0x01000000; + info->portwidth = 1; + info->chipwidth = 1; + info->buffer_size = 1; + info->erase_blk_tout = 16384; + info->write_tout = 2; + info->buffer_write_tout = 5; + info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */ + info->cmd_reset = 0x00F0; + info->interface = FLASH_CFI_X8; + info->legacy_unlock = 0; + info->manufacturer_id = (u16) ATM_MANUFACT; + info->device_id = ATM_ID_LV040; + info->device_id2 = 0; + info->ext_addr = 0; + info->cfi_version = 0x3133; + info->cfi_offset = 0x0000; + info->addr_unlock1 = 0x00000555; + info->addr_unlock2 = 0x000002AA; + info->name = "CFI conformant"; + info->size = 0; + info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT; + info->start[0] = base; + + for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) { + info->size += sect[i] * sectsz[i]; + for (j = 0; j < sect[i]; j++, k++) { + info->start[k + 1] = info->start[k] + sectsz[i]; + info->protect[k] = 0; + } + } + + return 1; +} +#endif /* CONFIG_FLASH_CFI_LEGACY */ diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile index 717ffc9c9..501fd467e 100644 --- a/board/xilinx/ppc405-generic/Makefile +++ b/board/xilinx/ppc405-generic/Makefile @@ -27,12 +27,9 @@ include $(TOPDIR)/config.mk ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../../xilinx/ppc405-generic) endif -INCS := -CFLAGS += $(INCS) -HOSTCFLAGS += $(INCS) - LIB = $(obj)lib$(BOARD).o COBJS += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o @@ -41,10 +38,8 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -all: $(LIB) $(SOBJS) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile index 1760e4e3b..ed2cf9f43 100644 --- a/board/xilinx/ppc440-generic/Makefile +++ b/board/xilinx/ppc440-generic/Makefile @@ -27,26 +27,20 @@ include $(TOPDIR)/config.mk ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../../xilinx/ppc440-generic) endif -INCS := -CFLAGS += $(INCS) -HOSTCFLAGS += $(INCS) - LIB = $(obj)lib$(BOARD).o COBJS += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o - -SOBJS += ../../xilinx/ppc440-generic/init.o +SOBJS += ../../xilinx/ppc440-generic/init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -all: $(LIB) $(SOBJS) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) clean: rm -f $(SOBJS) $(OBJS) diff --git a/boards.cfg b/boards.cfg index 94b8745a9..0574bb204 100644 --- a/boards.cfg +++ b/boards.cfg @@ -745,6 +745,7 @@ xilinx-ppc440-generic_flash powerpc ppc4xx ppc440-generic xilinx rsk7203 sh sh2 rsk7203 renesas - mpr2 sh sh3 mpr2 - - ms7720se sh sh3 ms7720se - - +shmin sh sh3 shmin - - espt sh sh4 espt - - ms7722se sh sh4 ms7722se - - ms7750se sh sh4 ms7750se - - diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c index d373480f7..cdb050c25 100644 --- a/common/cmd_fdc.c +++ b/common/cmd_fdc.c @@ -721,6 +721,7 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) image_header_t *hdr; /* used for fdc boot */ unsigned char boot_drive; int i,nrofblk; + char *ep; int rcode = 0; #if defined(CONFIG_FIT) const void *fit_hdr = NULL; @@ -823,7 +824,7 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) load_addr = addr; /* Check if we should attempt an auto-start */ - if (getenv_yesno("autostart")) { + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { char *local_args[2]; local_args[0] = argv[0]; diff --git a/common/cmd_fdos.c b/common/cmd_fdos.c index 238abdde4..2af4ca0ef 100644 --- a/common/cmd_fdos.c +++ b/common/cmd_fdos.c @@ -99,7 +99,7 @@ int do_fdosboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) size, load_addr); /* Check if we should attempt an auto-start */ - if (getenv_yesno("autostart")) { + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { char *local_args[2]; local_args[0] = argv[0]; local_args[1] = NULL; diff --git a/common/cmd_ide.c b/common/cmd_ide.c index f6278812a..df7bdf56e 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -496,7 +496,7 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) load_addr = addr; /* Check if we should attempt an auto-start */ - if (getenv_yesno("autostart")) { + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { char *local_args[2]; local_args[0] = argv[0]; diff --git a/common/cmd_nand.c b/common/cmd_nand.c index c547a683f..7bd37de78 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -574,7 +574,15 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) (u_char *)addr); else ret = nand_write_skip_bad(nand, off, &rwsize, - (u_char *)addr); + (u_char *)addr, 0); +#ifdef CONFIG_CMD_NAND_YAFFS + } else if (!strcmp(s, ".yaffs")) { + if (read) { + printf("Unknown nand command suffix '%s'.\n", s); + return 1; + } + ret = nand_write_skip_bad(nand, off, &rwsize, (u_char *)addr, 1); +#endif } else if (!strcmp(s, ".oob")) { /* out-of-band data */ mtd_oob_ops_t ops = { @@ -680,6 +688,11 @@ U_BOOT_CMD( "nand write - addr off|partition size\n" " read/write 'size' bytes starting at offset 'off'\n" " to/from memory address 'addr', skipping bad blocks.\n" +#ifdef CONFIG_CMD_NAND_YAFFS + "nand write.yaffs - addr off|partition size\n" + " write 'size' bytes starting at offset 'off' with yaffs format\n" + " from memory address 'addr', skipping bad blocks.\n" +#endif "nand erase[.spread] [clean] [off [size]] - erase 'size' bytes " "from offset 'off'\n" " With '.spread', erase enough for given file size, otherwise,\n" @@ -711,7 +724,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, ulong offset, ulong addr, char *cmd) { int r; - char *s; + char *ep, *s; size_t cnt; image_header_t *hdr; #if defined(CONFIG_FIT) @@ -787,7 +800,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, load_addr = addr; /* Check if we should attempt an auto-start */ - if (getenv_yesno("autostart")) { + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) { char *local_args[2]; local_args[0] = cmd; diff --git a/common/cmd_net.c b/common/cmd_net.c index 00e0ea8dd..8c6f5c8c3 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -211,7 +211,7 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char * const argv[]) flush_cache(load_addr, size); /* Loading ok, check if we should attempt an auto-start */ - if (getenv_yesno("autostart")) { + if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) { char *local_args[2]; local_args[0] = argv[0]; local_args[1] = NULL; diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index 63a46ded8..be4fe741c 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -327,7 +327,7 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) flush_cache (addr, (cnt+1)*info.blksz); /* Check if we should attempt an auto-start */ - if (getenv_yesno("autostart")) { + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { char *local_args[2]; local_args[0] = argv[0]; local_args[1] = NULL; diff --git a/common/cmd_usb.c b/common/cmd_usb.c index 843919822..b04a8df76 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -488,7 +488,7 @@ int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) flush_cache(addr, (cnt+1)*info.blksz); /* Check if we should attempt an auto-start */ - if (getenv_yesno("autostart")) { + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) { char *local_args[2]; local_args[0] = argv[0]; local_args[1] = NULL; diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c index 223fb7114..da8c9b15b 100644 --- a/drivers/mtd/jedec_flash.c +++ b/drivers/mtd/jedec_flash.c @@ -41,6 +41,7 @@ #define AM29DL800BB 0x22CB #define AM29DL800BT 0x224A +#define AM29F400BB 0x22AB #define AM29F800BB 0x2258 #define AM29F800BT 0x22D6 #define AM29LV400BB 0x22BA @@ -296,6 +297,23 @@ static const struct amd_flash_info jedec_table[] = { #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16 { .mfr_id = (u16)AMD_MANUFACT, + .dev_id = AM29F400BB, + .name = "AMD AM29F400BB", + .uaddr = { + [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = CFI_CMDSET_AMD_LEGACY, + .NumEraseRegions= 4, + .regions = { + ERASEINFO(0x04000, 1), + ERASEINFO(0x02000, 2), + ERASEINFO(0x08000, 1), + ERASEINFO(0x10000, 7), + } + }, + { + .mfr_id = (u16)AMD_MANUFACT, .dev_id = AM29LV400BB, .name = "AMD AM29LV400BB", .uaddr = { diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index d5eb54ad8..ab8bbb3ae 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -296,7 +296,7 @@ int board_nand_init(struct nand_chip *nand) mtd->priv = nand; /* Detect NAND chips */ - if (nand_scan_ident(mtd, 1)) { + if (nand_scan_ident(mtd, 1, NULL)) { printk(KERN_WARNING "NAND Flash not found !\n"); return -ENXIO; } diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index c0e068ab7..d987f4c85 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -43,7 +43,7 @@ static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand, ulong base_addr) { int maxchips = CONFIG_SYS_NAND_MAX_CHIPS; - int __attribute__((unused)) i = 0; + static int __attribute__((unused)) i = 0; if (maxchips < 1) maxchips = 1; diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 5239c1fcf..3b96b0e2a 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2414,10 +2414,10 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) */ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, struct nand_chip *chip, - int busw, int *maf_id) + int busw, int *maf_id, + const struct nand_flash_dev *type) { - const struct nand_flash_dev *type = NULL; - int i, dev_id, maf_idx; + int dev_id, maf_idx; int tmp_id, tmp_manf; /* Select the device */ @@ -2456,15 +2456,14 @@ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, return ERR_PTR(-ENODEV); } - /* Lookup the flash id */ - for (i = 0; nand_flash_ids[i].name != NULL; i++) { - if (dev_id == nand_flash_ids[i].id) { - type = &nand_flash_ids[i]; - break; - } - } + if (!type) + type = nand_flash_ids; + + for (; type->name != NULL; type++) + if (dev_id == type->id) + break; - if (!type) { + if (!type->name) { /* supress warning if there is no nand */ if (*maf_id != 0x00 && *maf_id != 0xff && dev_id != 0x00 && dev_id != 0xff) @@ -2580,13 +2579,15 @@ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, * nand_scan_ident - [NAND Interface] Scan for the NAND device * @mtd: MTD device structure * @maxchips: Number of chips to scan for + * @table: Alternative NAND ID table * * This is the first phase of the normal nand_scan() function. It * reads the flash ID and sets up MTD fields accordingly. * * The mtd->owner field must be set to the module of the caller. */ -int nand_scan_ident(struct mtd_info *mtd, int maxchips) +int nand_scan_ident(struct mtd_info *mtd, int maxchips, + const struct nand_flash_dev *table) { int i, busw, nand_maf_id; struct nand_chip *chip = mtd->priv; @@ -2598,7 +2599,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips) nand_set_defaults(chip, busw); /* Read the flash type */ - type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id); + type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id, table); if (IS_ERR(type)) { #ifndef CONFIG_SYS_NAND_QUIET_TEST @@ -2869,7 +2870,7 @@ int nand_scan(struct mtd_info *mtd, int maxchips) { int ret; - ret = nand_scan_ident(mtd, maxchips); + ret = nand_scan_ident(mtd, maxchips, NULL); if (!ret) ret = nand_scan_tail(mtd); return ret; diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 22c741169..8b4f73881 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -447,17 +447,34 @@ static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length) * @param nand NAND device * @param offset offset in flash * @param length buffer length - * @param buf buffer to read from + * @param buffer buffer to read from + * @param withoob whether write with yaffs format * @return 0 in case of success */ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, - u_char *buffer) + u_char *buffer, int withoob) { - int rval; + int rval = 0, blocksize; size_t left_to_write = *length; u_char *p_buffer = buffer; int need_skip; +#ifdef CONFIG_CMD_NAND_YAFFS + if (withoob) { + int pages; + pages = nand->erasesize / nand->writesize; + blocksize = (pages * nand->oobsize) + nand->erasesize; + if (*length % (nand->writesize + nand->oobsize)) { + printf ("Attempt to write incomplete page" + " in yaffs mode\n"); + return -EINVAL; + } + } else +#endif + { + blocksize = nand->erasesize; + } + /* * nand_write() handles unaligned, partial page writes. * @@ -506,12 +523,44 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, continue; } - if (left_to_write < (nand->erasesize - block_offset)) + if (left_to_write < (blocksize - block_offset)) write_size = left_to_write; else - write_size = nand->erasesize - block_offset; + write_size = blocksize - block_offset; + +#ifdef CONFIG_CMD_NAND_YAFFS + if (withoob) { + int page, pages; + size_t pagesize = nand->writesize; + size_t pagesize_oob = pagesize + nand->oobsize; + struct mtd_oob_ops ops; + + ops.len = pagesize; + ops.ooblen = nand->oobsize; + ops.mode = MTD_OOB_AUTO; + ops.ooboffs = 0; + + pages = write_size / pagesize_oob; + for (page = 0; page < pages; page++) { + ops.datbuf = p_buffer; + ops.oobbuf = ops.datbuf + pagesize; + + rval = nand->write_oob(nand, offset, &ops); + if (!rval) + break; + + offset += pagesize; + p_buffer += pagesize_oob; + } + } + else +#endif + { + rval = nand_write (nand, offset, &write_size, p_buffer); + offset += write_size; + p_buffer += write_size; + } - rval = nand_write (nand, offset, &write_size, p_buffer); if (rval != 0) { printf ("NAND write to offset %llx failed %d\n", offset, rval); @@ -520,8 +569,6 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, } left_to_write -= write_size; - offset += write_size; - p_buffer += write_size; } return 0; diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b605eea7d..fd9d0b4be 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -47,6 +47,7 @@ COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o COBJS-$(CONFIG_ETHOC) += ethoc.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o +COBJS-$(CONFIG_FTGMAC100) += ftgmac100.o COBJS-$(CONFIG_FTMAC100) += ftmac100.o COBJS-$(CONFIG_GRETH) += greth.o COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c new file mode 100644 index 000000000..dc7a80e5c --- /dev/null +++ b/drivers/net/ftgmac100.c @@ -0,0 +1,570 @@ +/* + * Faraday FTGMAC100 Ethernet + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert@faraday-tech.com> + * + * (C) Copyright 2010 Andes Technology + * Macpaul Lin <macpaul@andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <net.h> +#include <asm/io.h> +#include <linux/mii.h> + +#include "ftgmac100.h" + +#define ETH_ZLEN 60 + +#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) + +/* RBSR - hw default init value is also 0x640 */ +#define RBSR_DEFAULT_VALUE 0x640 + +/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */ +#define PKTBUFSTX 4 /* must be power of 2 */ + +struct ftgmac100_data { + struct ftgmac100_txdes txdes[PKTBUFSTX]; + struct ftgmac100_rxdes rxdes[PKTBUFSRX]; + int tx_index; + int rx_index; + int phy_addr; +}; + +/* + * struct mii_bus functions + */ +static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr, + int regnum) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + int phycr; + int i; + + phycr = readl(&ftgmac100->phycr); + + /* preserve MDC cycle threshold */ + phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; + + phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) + | FTGMAC100_PHYCR_REGAD(regnum) + | FTGMAC100_PHYCR_MIIRD; + + writel(phycr, &ftgmac100->phycr); + + for (i = 0; i < 10; i++) { + phycr = readl(&ftgmac100->phycr); + + if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { + int data; + + data = readl(&ftgmac100->phydata); + return FTGMAC100_PHYDATA_MIIRDATA(data); + } + + mdelay(10); + } + + debug("mdio read timed out\n"); + return -1; +} + +static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr, + int regnum, u16 value) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + int phycr; + int data; + int i; + + phycr = readl(&ftgmac100->phycr); + + /* preserve MDC cycle threshold */ + phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; + + phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) + | FTGMAC100_PHYCR_REGAD(regnum) + | FTGMAC100_PHYCR_MIIWR; + + data = FTGMAC100_PHYDATA_MIIWDATA(value); + + writel(data, &ftgmac100->phydata); + writel(phycr, &ftgmac100->phycr); + + for (i = 0; i < 10; i++) { + phycr = readl(&ftgmac100->phycr); + + if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) { + debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \ + "phy_addr: %x\n", phy_addr); + return 0; + } + + mdelay(1); + } + + debug("mdio write timed out\n"); + return -1; +} + +int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value) +{ + *value = ftgmac100_mdiobus_read(dev , addr, reg); + + if (*value == -1) + return -1; + + return 0; +} + +int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value) +{ + if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1) + return -1; + + return 0; +} + +static int ftgmac100_phy_reset(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + int i; + u16 status, adv; + + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + + ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv); + + printf("%s: Starting autonegotiation...\n", dev->name); + + ftgmac100_phy_write(dev, priv->phy_addr, + MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); + + for (i = 0; i < 100000 / 100; i++) { + ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status); + + if (status & BMSR_ANEGCOMPLETE) + break; + mdelay(1); + } + + if (status & BMSR_ANEGCOMPLETE) { + printf("%s: Autonegotiation complete\n", dev->name); + } else { + printf("%s: Autonegotiation timed out (status=0x%04x)\n", + dev->name, status); + return 0; + } + + return 1; +} + +static int ftgmac100_phy_init(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + + int phy_addr; + u16 phy_id, status, adv, lpa, stat_ge; + int media, speed, duplex; + int i; + + /* Check if the PHY is up to snuff... */ + for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) { + + ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id); + + /* + * When it is unable to found PHY, + * the interface usually return 0xffff or 0x0000 + */ + if (phy_id != 0xffff && phy_id != 0x0) { + printf("%s: found PHY at 0x%02x\n", + dev->name, phy_addr); + priv->phy_addr = phy_addr; + break; + } + } + + if (phy_id == 0xffff || phy_id == 0x0) { + printf("%s: no PHY present\n", dev->name); + return 0; + } + + ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status); + + if (!(status & BMSR_LSTATUS)) { + /* Try to re-negotiate if we don't have link already. */ + ftgmac100_phy_reset(dev); + + for (i = 0; i < 100000 / 100; i++) { + ftgmac100_phy_read(dev, priv->phy_addr, + MII_BMSR, &status); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } + + if (!(status & BMSR_LSTATUS)) { + printf("%s: link down\n", dev->name); + return 0; + } + +#ifdef CONFIG_FTGMAC100_EGIGA + /* 1000 Base-T Status Register */ + ftgmac100_phy_read(dev, priv->phy_addr, + MII_STAT1000, &stat_ge); + + speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF) + ? 1 : 0); + + duplex = ((stat_ge & LPA_1000FULL) + ? 1 : 0); + + if (speed) { /* Speed is 1000 */ + printf("%s: link up, 1000bps %s-duplex\n", + dev->name, duplex ? "full" : "half"); + return 0; + } +#endif + + ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv); + ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa); + + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + + printf("%s: link up, %sMbps %s-duplex\n", + dev->name, speed ? "100" : "10", duplex ? "full" : "half"); + + return 1; +} + +static int ftgmac100_update_link_speed(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + + unsigned short stat_fe; + unsigned short stat_ge; + unsigned int maccr; + +#ifdef CONFIG_FTGMAC100_EGIGA + /* 1000 Base-T Status Register */ + ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge); +#endif + + ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe); + + if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */ + return 0; + + /* read MAC control register and clear related bits */ + maccr = readl(&ftgmac100->maccr) & + ~(FTGMAC100_MACCR_GIGA_MODE | + FTGMAC100_MACCR_FAST_MODE | + FTGMAC100_MACCR_FULLDUP); + +#ifdef CONFIG_FTGMAC100_EGIGA + if (stat_ge & LPA_1000FULL) { + /* set gmac for 1000BaseTX and Full Duplex */ + maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP; + } + + if (stat_ge & LPA_1000HALF) { + /* set gmac for 1000BaseTX and Half Duplex */ + maccr |= FTGMAC100_MACCR_GIGA_MODE; + } +#endif + + if (stat_fe & BMSR_100FULL) { + /* set MII for 100BaseTX and Full Duplex */ + maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP; + } + + if (stat_fe & BMSR_10FULL) { + /* set MII for 10BaseT and Full Duplex */ + maccr |= FTGMAC100_MACCR_FULLDUP; + } + + if (stat_fe & BMSR_100HALF) { + /* set MII for 100BaseTX and Half Duplex */ + maccr |= FTGMAC100_MACCR_FAST_MODE; + } + + if (stat_fe & BMSR_10HALF) { + /* set MII for 10BaseT and Half Duplex */ + /* we have already clear these bits, do nothing */ + ; + } + + /* update MII config into maccr */ + writel(maccr, &ftgmac100->maccr); + + return 1; +} + +/* + * Reset MAC + */ +static void ftgmac100_reset(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + + debug("%s()\n", __func__); + + writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr); + + while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST) + ; +} + +/* + * Set MAC address + */ +static void ftgmac100_set_mac(struct eth_device *dev, + const unsigned char *mac) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + unsigned int maddr = mac[0] << 8 | mac[1]; + unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; + + debug("%s(%x %x)\n", __func__, maddr, laddr); + + writel(maddr, &ftgmac100->mac_madr); + writel(laddr, &ftgmac100->mac_ladr); +} + +static void ftgmac100_set_mac_from_env(struct eth_device *dev) +{ + eth_getenv_enetaddr("ethaddr", dev->enetaddr); + + ftgmac100_set_mac(dev, dev->enetaddr); +} + +/* + * disable transmitter, receiver + */ +static void ftgmac100_halt(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + + debug("%s()\n", __func__); + + writel(0, &ftgmac100->maccr); +} + +static int ftgmac100_init(struct eth_device *dev, bd_t *bd) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_txdes *txdes = priv->txdes; + struct ftgmac100_rxdes *rxdes = priv->rxdes; + unsigned int maccr; + int i; + + debug("%s()\n", __func__); + + ftgmac100_reset(dev); + + /* set the ethernet address */ + ftgmac100_set_mac_from_env(dev); + + /* disable all interrupts */ + writel(0, &ftgmac100->ier); + + /* initialize descriptors */ + priv->tx_index = 0; + priv->rx_index = 0; + + txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR; + rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR; + + for (i = 0; i < PKTBUFSTX; i++) { + /* TXBUF_BADR */ + txdes[i].txdes3 = 0; + txdes[i].txdes1 = 0; + } + + for (i = 0; i < PKTBUFSRX; i++) { + /* RXBUF_BADR */ + rxdes[i].rxdes3 = (unsigned int)NetRxPackets[i]; + rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + } + + /* transmit ring */ + writel((unsigned int)txdes, &ftgmac100->txr_badr); + + /* receive ring */ + writel((unsigned int)rxdes, &ftgmac100->rxr_badr); + + /* poll receive descriptor automatically */ + writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); + + /* config receive buffer size register */ + writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr); + + /* enable transmitter, receiver */ + maccr = FTGMAC100_MACCR_TXMAC_EN | + FTGMAC100_MACCR_RXMAC_EN | + FTGMAC100_MACCR_TXDMA_EN | + FTGMAC100_MACCR_RXDMA_EN | + FTGMAC100_MACCR_CRC_APD | + FTGMAC100_MACCR_FULLDUP | + FTGMAC100_MACCR_RX_RUNT | + FTGMAC100_MACCR_RX_BROADPKT; + + writel(maccr, &ftgmac100->maccr); + + if (!ftgmac100_phy_init(dev)) { + if (!ftgmac100_update_link_speed(dev)) + return -1; + } + + return 0; +} + +/* + * Get a data block via Ethernet + */ +static int ftgmac100_recv(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_rxdes *curr_des; + unsigned short rxlen; + + curr_des = &priv->rxdes[priv->rx_index]; + + if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY)) + return -1; + + if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR | + FTGMAC100_RXDES0_CRC_ERR | + FTGMAC100_RXDES0_FTL | + FTGMAC100_RXDES0_RUNT | + FTGMAC100_RXDES0_RX_ODD_NB)) { + return -1; + } + + rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0); + + debug("%s(): RX buffer %d, %x received\n", + __func__, priv->rx_index, rxlen); + + /* pass the packet up to the protocol layers. */ + NetReceive((void *)curr_des->rxdes3, rxlen); + + /* release buffer to DMA */ + curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; + + return 0; +} + +/* + * Send a data block via Ethernet + */ +static int +ftgmac100_send(struct eth_device *dev, void *packet, int length) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; + int start; + + if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { + debug("%s(): no TX descriptor available\n", __func__); + return -1; + } + + debug("%s(%x, %x)\n", __func__, (int)packet, length); + + length = (length < ETH_ZLEN) ? ETH_ZLEN : length; + + /* initiate a transmit sequence */ + curr_des->txdes3 = (unsigned int)packet; /* TXBUF_BADR */ + + /* only one descriptor on TXBUF */ + curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR; + curr_des->txdes0 |= FTGMAC100_TXDES0_FTS | + FTGMAC100_TXDES0_LTS | + FTGMAC100_TXDES0_TXBUF_SIZE(length) | + FTGMAC100_TXDES0_TXDMA_OWN ; + + /* start transmit */ + writel(1, &ftgmac100->txpd); + + /* wait for transfer to succeed */ + start = get_timer(0); + while (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { + if (get_timer(0) >= 5) { + debug("%s(): timed out\n", __func__); + return -1; + } + } + + debug("%s(): packet sent\n", __func__); + + priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX; + + return 0; +} + +int ftgmac100_initialize(bd_t *bd) +{ + struct eth_device *dev; + struct ftgmac100_data *priv; + + dev = malloc(sizeof *dev); + if (!dev) { + printf("%s(): failed to allocate dev\n", __func__); + goto out; + } + + /* Transmit and receive descriptors should align to 16 bytes */ + priv = memalign(16, sizeof(struct ftgmac100_data)); + if (!priv) { + printf("%s(): failed to allocate priv\n", __func__); + goto free_dev; + } + + memset(dev, 0, sizeof(*dev)); + memset(priv, 0, sizeof(*priv)); + + sprintf(dev->name, "FTGMAC100"); + dev->iobase = CONFIG_FTGMAC100_BASE; + dev->init = ftgmac100_init; + dev->halt = ftgmac100_halt; + dev->send = ftgmac100_send; + dev->recv = ftgmac100_recv; + dev->priv = priv; + + eth_register(dev); + + return 1; + +free_dev: + free(dev); +out: + return 0; +} diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h new file mode 100644 index 000000000..46b7369c8 --- /dev/null +++ b/drivers/net/ftgmac100.h @@ -0,0 +1,255 @@ +/* + * Faraday FTGMAC100 Ethernet + * + * (C) Copyright 2010 Faraday Technology + * Po-Yu Chuang <ratbert@faraday-tech.com> + * + * (C) Copyright 2010 Andes Technology + * Macpaul Lin <macpaul@andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __FTGMAC100_H +#define __FTGMAC100_H + +/* The registers offset table of ftgmac100 */ +struct ftgmac100 { + unsigned int isr; /* 0x00 */ + unsigned int ier; /* 0x04 */ + unsigned int mac_madr; /* 0x08 */ + unsigned int mac_ladr; /* 0x0c */ + unsigned int maht0; /* 0x10 */ + unsigned int maht1; /* 0x14 */ + unsigned int txpd; /* 0x18 */ + unsigned int rxpd; /* 0x1c */ + unsigned int txr_badr; /* 0x20 */ + unsigned int rxr_badr; /* 0x24 */ + unsigned int hptxpd; /* 0x28 */ + unsigned int hptxpd_badr; /* 0x2c */ + unsigned int itc; /* 0x30 */ + unsigned int aptc; /* 0x34 */ + unsigned int dblac; /* 0x38 */ + unsigned int dmafifos; /* 0x3c */ + unsigned int revr; /* 0x40 */ + unsigned int fear; /* 0x44 */ + unsigned int tpafcr; /* 0x48 */ + unsigned int rbsr; /* 0x4c */ + unsigned int maccr; /* 0x50 */ + unsigned int macsr; /* 0x54 */ + unsigned int tm; /* 0x58 */ + unsigned int resv1; /* 0x5c */ /* not defined in spec */ + unsigned int phycr; /* 0x60 */ + unsigned int phydata; /* 0x64 */ + unsigned int fcr; /* 0x68 */ + unsigned int bpr; /* 0x6c */ + unsigned int wolcr; /* 0x70 */ + unsigned int wolsr; /* 0x74 */ + unsigned int wfcrc; /* 0x78 */ + unsigned int resv2; /* 0x7c */ /* not defined in spec */ + unsigned int wfbm1; /* 0x80 */ + unsigned int wfbm2; /* 0x84 */ + unsigned int wfbm3; /* 0x88 */ + unsigned int wfbm4; /* 0x8c */ + unsigned int nptxr_ptr; /* 0x90 */ + unsigned int hptxr_ptr; /* 0x94 */ + unsigned int rxr_ptr; /* 0x98 */ + unsigned int resv3; /* 0x9c */ /* not defined in spec */ + unsigned int tx; /* 0xa0 */ + unsigned int tx_mcol_scol; /* 0xa4 */ + unsigned int tx_ecol_fail; /* 0xa8 */ + unsigned int tx_lcol_und; /* 0xac */ + unsigned int rx; /* 0xb0 */ + unsigned int rx_bc; /* 0xb4 */ + unsigned int rx_mc; /* 0xb8 */ + unsigned int rx_pf_aep; /* 0xbc */ + unsigned int rx_runt; /* 0xc0 */ + unsigned int rx_crcer_ftl; /* 0xc4 */ + unsigned int rx_col_lost; /* 0xc8 */ +}; + +/* + * Interrupt status register & interrupt enable register + */ +#define FTGMAC100_INT_RPKT_BUF (1 << 0) +#define FTGMAC100_INT_RPKT_FIFO (1 << 1) +#define FTGMAC100_INT_NO_RXBUF (1 << 2) +#define FTGMAC100_INT_RPKT_LOST (1 << 3) +#define FTGMAC100_INT_XPKT_ETH (1 << 4) +#define FTGMAC100_INT_XPKT_FIFO (1 << 5) +#define FTGMAC100_INT_NO_NPTXBUF (1 << 6) +#define FTGMAC100_INT_XPKT_LOST (1 << 7) +#define FTGMAC100_INT_AHB_ERR (1 << 8) +#define FTGMAC100_INT_PHYSTS_CHG (1 << 9) +#define FTGMAC100_INT_NO_HPTXBUF (1 << 10) + +/* + * Interrupt timer control register + */ +#define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) +#define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) +#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7) +#define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) +#define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) +#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15) + +/* + * Automatic polling timer control register + */ +#define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) +#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) +#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) +#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) + +/* + * DMA burst length and arbitration control register + */ +#define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0) +#define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3) +#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6) +#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8) +#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) +#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) +#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) +#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) +#define FTGMAC100_DBLAC_IFG_INC (1 << 23) + +/* + * DMA FIFO status register + */ +#define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf) +#define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf) +#define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7) +#define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf) +#define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3) +#define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf) +#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26) +#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27) +#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28) +#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29) +#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30) +#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31) + +/* + * Receive buffer size register + */ +#define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff) + +/* + * MAC control register + */ +#define FTGMAC100_MACCR_TXDMA_EN (1 << 0) +#define FTGMAC100_MACCR_RXDMA_EN (1 << 1) +#define FTGMAC100_MACCR_TXMAC_EN (1 << 2) +#define FTGMAC100_MACCR_RXMAC_EN (1 << 3) +#define FTGMAC100_MACCR_RM_VLAN (1 << 4) +#define FTGMAC100_MACCR_HPTXR_EN (1 << 5) +#define FTGMAC100_MACCR_LOOP_EN (1 << 6) +#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7) +#define FTGMAC100_MACCR_FULLDUP (1 << 8) +#define FTGMAC100_MACCR_GIGA_MODE (1 << 9) +#define FTGMAC100_MACCR_CRC_APD (1 << 10) +#define FTGMAC100_MACCR_RX_RUNT (1 << 12) +#define FTGMAC100_MACCR_JUMBO_LF (1 << 13) +#define FTGMAC100_MACCR_RX_ALL (1 << 14) +#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15) +#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16) +#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17) +#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18) +#define FTGMAC100_MACCR_FAST_MODE (1 << 19) +#define FTGMAC100_MACCR_SW_RST (1 << 31) + +/* + * PHY control register + */ +#define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f +#define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f) +#define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) +#define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) +#define FTGMAC100_PHYCR_MIIRD (1 << 26) +#define FTGMAC100_PHYCR_MIIWR (1 << 27) + +/* + * PHY data register + */ +#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff) +#define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff) + +/* + * Transmit descriptor, aligned to 16 bytes + */ +struct ftgmac100_txdes { + unsigned int txdes0; + unsigned int txdes1; + unsigned int txdes2; /* not used by HW */ + unsigned int txdes3; /* TXBUF_BADR */ +} __attribute__ ((aligned(16))); + +#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) +#define FTGMAC100_TXDES0_EDOTR (1 << 15) +#define FTGMAC100_TXDES0_CRC_ERR (1 << 19) +#define FTGMAC100_TXDES0_LTS (1 << 28) +#define FTGMAC100_TXDES0_FTS (1 << 29) +#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) + +#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) +#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16) +#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17) +#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18) +#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19) +#define FTGMAC100_TXDES1_LLC (1 << 22) +#define FTGMAC100_TXDES1_TX2FIC (1 << 30) +#define FTGMAC100_TXDES1_TXIC (1 << 31) + +/* + * Receive descriptor, aligned to 16 bytes + */ +struct ftgmac100_rxdes { + unsigned int rxdes0; + unsigned int rxdes1; + unsigned int rxdes2; /* not used by HW */ + unsigned int rxdes3; /* RXBUF_BADR */ +} __attribute__ ((aligned(16))); + +#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) +#define FTGMAC100_RXDES0_EDORR (1 << 15) +#define FTGMAC100_RXDES0_MULTICAST (1 << 16) +#define FTGMAC100_RXDES0_BROADCAST (1 << 17) +#define FTGMAC100_RXDES0_RX_ERR (1 << 18) +#define FTGMAC100_RXDES0_CRC_ERR (1 << 19) +#define FTGMAC100_RXDES0_FTL (1 << 20) +#define FTGMAC100_RXDES0_RUNT (1 << 21) +#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22) +#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23) +#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24) +#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) +#define FTGMAC100_RXDES0_LRS (1 << 28) +#define FTGMAC100_RXDES0_FRS (1 << 29) +#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) + +#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff +#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) +#define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20) +#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) +#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) +#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) +#define FTGMAC100_RXDES1_LLC (1 << 22) +#define FTGMAC100_RXDES1_DF (1 << 23) +#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24) +#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25) +#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) +#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) + +#endif /* __FTGMAC100_H */ diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c index 810079f03..bd6966ed7 100644 --- a/drivers/net/lan91c96.c +++ b/drivers/net/lan91c96.c @@ -767,8 +767,8 @@ static struct id_type supported_chips[] = { {8, "LAN91C100FD"}, {7, "LAN91C100"}, {5, "LAN91C95"}, - {4, "LAN91C94/LAN91C96"}, - {3, "LAN91C90/LAN91C92"}, + {4, "LAN91C94/96"}, + {3, "LAN91C90/92"}, }; /* lan91c96_detect_chip * See: diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 0103a2918..fcf69abd2 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -1,6 +1,7 @@ /* * SuperH SCIF device driver. - * Copyright (c) 2007,2008 Nobuhiro Iwamatsu + * Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu + * Copyright (C) 2002 - 2008 Paul Mundt * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,8 +21,7 @@ #include <common.h> #include <asm/io.h> #include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; +#include "serial_sh.h" #if defined(CONFIG_CONS_SCIF0) # define SCIF_BASE SCIF0_BASE @@ -39,139 +39,88 @@ DECLARE_GLOBAL_DATA_PTR; # error "Default SCIF doesn't set....." #endif -/* Base register */ -#define SCSMR (vu_short *)(SCIF_BASE + 0x0) -#define SCBRR (vu_char *)(SCIF_BASE + 0x4) -#define SCSCR (vu_short *)(SCIF_BASE + 0x8) -#define SCFCR (vu_short *)(SCIF_BASE + 0x18) -#define SCFDR (vu_short *)(SCIF_BASE + 0x1C) -#if defined(CONFIG_CPU_SH7720) || \ - (defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A)) -# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ -# define SCFTDR (vu_char *)(SCIF_BASE + 0x20) -# define SCFRDR (vu_char *)(SCIF_BASE + 0x24) +#if defined(CONFIG_SCIF_A) + #define SCIF_BASE_PORT PORT_SCIFA #else -# define SCFTDR (vu_char *)(SCIF_BASE + 0xC) -# define SCFSR (vu_short *)(SCIF_BASE + 0x10) -# define SCFRDR (vu_char *)(SCIF_BASE + 0x14) + #define SCIF_BASE_PORT PORT_SCIF #endif -#if defined(CONFIG_CPU_SH7780) || \ - defined(CONFIG_CPU_SH7785) -# define SCRFDR (vu_short *)(SCIF_BASE + 0x20) -# define SCSPTR (vu_short *)(SCIF_BASE + 0x24) -# define SCLSR (vu_short *)(SCIF_BASE + 0x28) -# define SCRER (vu_short *)(SCIF_BASE + 0x2C) -# define LSR_ORER 1 -# define FIFOLEVEL_MASK 0xFF -#elif defined(CONFIG_CPU_SH7763) -# if defined(CONFIG_CONS_SCIF2) -# define SCSPTR (vu_short *)(SCIF_BASE + 0x20) -# define SCLSR (vu_short *)(SCIF_BASE + 0x24) -# define LSR_ORER 1 -# define FIFOLEVEL_MASK 0x1F -# else -# define SCRFDR (vu_short *)(SCIF_BASE + 0x20) -# define SCSPTR (vu_short *)(SCIF_BASE + 0x24) -# define SCLSR (vu_short *)(SCIF_BASE + 0x28) -# define SCRER (vu_short *)(SCIF_BASE + 0x2C) -# define LSR_ORER 1 -# define FIFOLEVEL_MASK 0xFF -# endif -#elif defined(CONFIG_CPU_SH7723) -# if defined(CONFIG_SCIF_A) -# define SCLSR SCFSR -# define LSR_ORER 0x0200 -# define FIFOLEVEL_MASK 0x3F -#else -# define SCLSR (vu_short *)(SCIF_BASE + 0x24) -# define LSR_ORER 1 -# define FIFOLEVEL_MASK 0x1F -#endif -#elif defined(CONFIG_CPU_SH7750) || \ - defined(CONFIG_CPU_SH7751) || \ - defined(CONFIG_CPU_SH7722) || \ - defined(CONFIG_CPU_SH7203) -# define SCSPTR (vu_short *)(SCIF_BASE + 0x20) -# define SCLSR (vu_short *)(SCIF_BASE + 0x24) -# define LSR_ORER 1 -# define FIFOLEVEL_MASK 0x1F -#elif defined(CONFIG_CPU_SH7720) -# define SCLSR SCFSR -# define LSR_ORER 0x0200 -# define FIFOLEVEL_MASK 0x1F -#elif defined(CONFIG_CPU_SH7710) || \ - defined(CONFIG_CPU_SH7712) -# define SCLSR SCFSR /* SCSSR */ -# define LSR_ORER 1 -# define FIFOLEVEL_MASK 0x1F -#endif - -/* SCBRR register value setting */ -#if defined(CONFIG_CPU_SH7720) -# define SCBRR_VALUE(bps, clk) (((clk * 2) + 16 * bps) / (32 * bps) - 1) -#elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A) -/* SH7723 SCIFA use bus clock. So clock *2 */ -# define SCBRR_VALUE(bps, clk) (((clk * 2 * 2) + 16 * bps) / (32 * bps) - 1) -#else /* Generic SuperH */ -# define SCBRR_VALUE(bps, clk) ((clk + 16 * bps) / (32 * bps) - 1) -#endif - -#define SCR_RE (1 << 4) -#define SCR_TE (1 << 5) -#define FCR_RFRST (1 << 1) /* RFCL */ -#define FCR_TFRST (1 << 2) /* TFCL */ -#define FSR_DR (1 << 0) -#define FSR_RDF (1 << 1) -#define FSR_FER (1 << 3) -#define FSR_BRK (1 << 4) -#define FSR_FER (1 << 3) -#define FSR_TEND (1 << 6) -#define FSR_ER (1 << 7) - -/*----------------------------------------------------------------------*/ +static struct uart_port sh_sci = { + .membase = (unsigned char*)SCIF_BASE, + .mapbase = SCIF_BASE, + .type = SCIF_BASE_PORT, +}; void serial_setbrg(void) { - writeb(SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ), SCBRR); + DECLARE_GLOBAL_DATA_PTR; + sci_out(&sh_sci, SCBRR, SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ)); } int serial_init(void) { - writew((SCR_RE | SCR_TE), SCSCR); - writew(0, SCSMR); - writew(0, SCSMR); - writew((FCR_RFRST | FCR_TFRST), SCFCR); - readw(SCFCR); - writew(0, SCFCR); + sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci)); + sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci)); + sci_out(&sh_sci, SCSMR, 0); + sci_out(&sh_sci, SCSMR, 0); + sci_out(&sh_sci, SCFCR, SCFCR_RFRST|SCFCR_TFRST); + sci_in(&sh_sci, SCFCR); + sci_out(&sh_sci, SCFCR, 0); serial_setbrg(); return 0; } -static int serial_rx_fifo_level(void) +#if defined(CONFIG_CPU_SH7760) || \ + defined(CONFIG_CPU_SH7780) || \ + defined(CONFIG_CPU_SH7785) || \ + defined(CONFIG_CPU_SH7786) +static int scif_rxfill(struct uart_port *port) +{ + return sci_in(port, SCRFDR) & 0xff; +} +#elif defined(CONFIG_CPU_SH7763) +static int scif_rxfill(struct uart_port *port) { -#if defined(SCRFDR) - return (readw(SCRFDR) >> 0) & FIFOLEVEL_MASK; + if ((port->mapbase == 0xffe00000) || + (port->mapbase == 0xffe08000)) { + /* SCIF0/1*/ + return sci_in(port, SCRFDR) & 0xff; + } else { + /* SCIF2 */ + return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; + } +} +#elif defined(CONFIG_ARCH_SH7372) +static int scif_rxfill(struct uart_port *port) +{ + if (port->type == PORT_SCIFA) + return sci_in(port, SCFDR) & SCIF_RFDC_MASK; + else + return sci_in(port, SCRFDR); +} #else - return (readw(SCFDR) >> 0) & FIFOLEVEL_MASK; +static int scif_rxfill(struct uart_port *port) +{ + return sci_in(port, SCFDR) & SCIF_RFDC_MASK; +} #endif + +static int serial_rx_fifo_level(void) +{ + return scif_rxfill(&sh_sci); } void serial_raw_putc(const char c) { - unsigned int fsr_bits_to_clear; - while (1) { - if (readw(SCFSR) & FSR_TEND) { /* Tx fifo is empty */ - fsr_bits_to_clear = FSR_TEND; + /* Tx fifo is empty */ + if (sci_in(&sh_sci, SCxSR) & SCxSR_TEND(&sh_sci)) break; - } } - writeb(c, SCFTDR); - if (fsr_bits_to_clear != 0) - writew(readw(SCFSR) & ~fsr_bits_to_clear, SCFSR); + sci_out(&sh_sci, SCxTDR, c); + sci_out(&sh_sci, SCxSR, sci_in(&sh_sci, SCxSR) & ~SCxSR_TEND(&sh_sci)); } void serial_putc(const char c) @@ -193,27 +142,25 @@ int serial_tstc(void) return serial_rx_fifo_level() ? 1 : 0; } -#define FSR_ERR_CLEAR 0x0063 -#define RDRF_CLEAR 0x00fc void handle_error(void) { - readw(SCFSR); - writew(FSR_ERR_CLEAR, SCFSR); - readw(SCLSR); - writew(0x00, SCLSR); + sci_in(&sh_sci, SCxSR); + sci_out(&sh_sci, SCxSR, SCxSR_ERROR_CLEAR(&sh_sci)); + sci_in(&sh_sci, SCLSR); + sci_out(&sh_sci, SCLSR, 0x00); } int serial_getc_check(void) { unsigned short status; - status = readw(SCFSR); + status = sci_in(&sh_sci, SCxSR); - if (status & (FSR_FER | FSR_ER | FSR_BRK)) + if (status & SCIF_ERRORS) handle_error(); - if (readw(SCLSR) & LSR_ORER) + if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci)) handle_error(); - return status & (FSR_DR | FSR_RDF); + return status & (SCIF_DR | SCxSR_RDxF(&sh_sci)); } int serial_getc(void) @@ -224,16 +171,15 @@ int serial_getc(void) while (!serial_getc_check()) ; - ch = readb(SCFRDR); - status = readw(SCFSR); + ch = sci_in(&sh_sci, SCxRDR); + status = sci_in(&sh_sci, SCxSR); - writew(RDRF_CLEAR, SCFSR); + sci_out(&sh_sci, SCxSR, SCxSR_RDxF_CLEAR(&sh_sci)); - if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) - handle_error(); + if (status & SCIF_ERRORS) + handle_error(); - if (readw(SCLSR) & LSR_ORER) + if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci)) handle_error(); - return ch; } diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h new file mode 100644 index 000000000..e19593c66 --- /dev/null +++ b/drivers/serial/serial_sh.h @@ -0,0 +1,690 @@ +/* + * Copy and modify from linux/drivers/serial/sh-sci.h + */ + +struct uart_port { + unsigned long iobase; /* in/out[bwl] */ + unsigned char *membase; /* read/write[bwl] */ + unsigned long mapbase; /* for ioremap */ + unsigned int type; /* port type */ +}; + +#define PORT_SCI 52 +#define PORT_SCIF 53 +#define PORT_SCIFA 83 +#define PORT_SCIFB 93 + +#if defined(CONFIG_H83007) || defined(CONFIG_H83068) +#include <asm/regs306x.h> +#endif +#if defined(CONFIG_H8S2678) +#include <asm/regs267x.h> +#endif + +#if defined(CONFIG_CPU_SH7706) || \ + defined(CONFIG_CPU_SH7707) || \ + defined(CONFIG_CPU_SH7708) || \ + defined(CONFIG_CPU_SH7709) +# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ +# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ +# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ +#elif defined(CONFIG_CPU_SH7705) +# define SCIF0 0xA4400000 +# define SCIF2 0xA4410000 +# define SCSMR_Ir 0xA44A0000 +# define IRDA_SCIF SCIF0 +# define SCPCR 0xA4000116 +# define SCPDR 0xA4000136 + +/* Set the clock source, + * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input + * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output + */ +# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 +#elif defined(CONFIG_CPU_SH7720) || \ + defined(CONFIG_CPU_SH7721) || \ + defined(CONFIG_ARCH_SH7367) || \ + defined(CONFIG_ARCH_SH7377) || \ + defined(CONFIG_ARCH_SH7372) +# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ +# define PORT_PTCR 0xA405011EUL +# define PORT_PVCR 0xA4050122UL +# define SCIF_ORER 0x0200 /* overrun error bit */ +#elif defined(CONFIG_SH_RTS7751R2D) +# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ +# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ +# define SCIF_ORER 0x0001 /* overrun error bit */ +# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +#elif defined(CONFIG_CPU_SH7750) || \ + defined(CONFIG_CPU_SH7750R) || \ + defined(CONFIG_CPU_SH7750S) || \ + defined(CONFIG_CPU_SH7091) || \ + defined(CONFIG_CPU_SH7751) || \ + defined(CONFIG_CPU_SH7751R) +# define SCSPTR1 0xffe0001c /* 8 bit SCI */ +# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ +# define SCIF_ORER 0x0001 /* overrun error bit */ +# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ + 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ + 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) +#elif defined(CONFIG_CPU_SH7760) +# define SCSPTR0 0xfe600024 /* 16 bit SCIF */ +# define SCSPTR1 0xfe610024 /* 16 bit SCIF */ +# define SCSPTR2 0xfe620024 /* 16 bit SCIF */ +# define SCIF_ORER 0x0001 /* overrun error bit */ +# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) +# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ +# define SCIF_ORER 0x0001 /* overrun error bit */ +# define PACR 0xa4050100 +# define PBCR 0xa4050102 +# define SCSCR_INIT(port) 0x3B +#elif defined(CONFIG_CPU_SH7343) +# define SCSPTR0 0xffe00010 /* 16 bit SCIF */ +# define SCSPTR1 0xffe10010 /* 16 bit SCIF */ +# define SCSPTR2 0xffe20010 /* 16 bit SCIF */ +# define SCSPTR3 0xffe30010 /* 16 bit SCIF */ +# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ +#elif defined(CONFIG_CPU_SH7722) +# define PADR 0xA4050120 +# undef PSDR +# define PSDR 0xA405013e +# define PWDR 0xA4050166 +# define PSCR 0xA405011E +# define SCIF_ORER 0x0001 /* overrun error bit */ +# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +#elif defined(CONFIG_CPU_SH7366) +# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ +# define SCSPTR0 SCPDR0 +# define SCIF_ORER 0x0001 /* overrun error bit */ +# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +#elif defined(CONFIG_CPU_SH7723) +# define SCSPTR0 0xa4050160 +# define SCSPTR1 0xa405013e +# define SCSPTR2 0xa4050160 +# define SCSPTR3 0xa405013e +# define SCSPTR4 0xa4050128 +# define SCSPTR5 0xa4050128 +# define SCIF_ORER 0x0001 /* overrun error bit */ +# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +#elif defined(CONFIG_CPU_SH7724) +# define SCIF_ORER 0x0001 /* overrun error bit */ +# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ + 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ + 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) +#elif defined(CONFIG_CPU_SH4_202) +# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ +# define SCIF_ORER 0x0001 /* overrun error bit */ +# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +#elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103) +# define SCIF_BASE_ADDR 0x01030000 +# define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR) +# define SCIF_PTR2_OFFS 0x0000020 +# define SCIF_LSR2_OFFS 0x0000024 +# define SCSPTR\ + ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ +# define SCLSR2\ + ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ +# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ +#elif defined(CONFIG_H83007) || defined(CONFIG_H83068) +# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ +# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) +#elif defined(CONFIG_H8S2678) +# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ +# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) +#elif defined(CONFIG_CPU_SH7757) +# define SCSPTR0 0xfe4b0020 +# define SCSPTR1 0xfe4b0020 +# define SCSPTR2 0xfe4b0020 +# define SCIF_ORER 0x0001 +# define SCSCR_INIT(port) 0x38 +# define SCIF_ONLY +#elif defined(CONFIG_CPU_SH7763) +# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ +# define SCSPTR1 0xffe08024 /* 16 bit SCIF */ +# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ +# define SCIF_ORER 0x0001 /* overrun error bit */ +# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +#elif defined(CONFIG_CPU_SH7770) +# define SCSPTR0 0xff923020 /* 16 bit SCIF */ +# define SCSPTR1 0xff924020 /* 16 bit SCIF */ +# define SCSPTR2 0xff925020 /* 16 bit SCIF */ +# define SCIF_ORER 0x0001 /* overrun error bit */ +# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ +#elif defined(CONFIG_CPU_SH7780) +# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ +# define SCSPTR1 0xffe10024 /* 16 bit SCIF */ +# define SCIF_ORER 0x0001 /* Overrun error bit */ + +#if defined(CONFIG_SH_SH2007) +/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */ +# define SCSCR_INIT(port) 0x38 +#else +/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */ +# define SCSCR_INIT(port) 0x3a +#endif + +#elif defined(CONFIG_CPU_SH7785) || \ + defined(CONFIG_CPU_SH7786) +# define SCSPTR0 0xffea0024 /* 16 bit SCIF */ +# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ +# define SCSPTR2 0xffec0024 /* 16 bit SCIF */ +# define SCSPTR3 0xffed0024 /* 16 bit SCIF */ +# define SCSPTR4 0xffee0024 /* 16 bit SCIF */ +# define SCSPTR5 0xffef0024 /* 16 bit SCIF */ +# define SCIF_ORER 0x0001 /* Overrun error bit */ +# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +#elif defined(CONFIG_CPU_SH7201) || \ + defined(CONFIG_CPU_SH7203) || \ + defined(CONFIG_CPU_SH7206) || \ + defined(CONFIG_CPU_SH7263) +# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ +# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ +# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ +# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ +# if defined(CONFIG_CPU_SH7201) +# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ +# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ +# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ +# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ +# endif +# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +#elif defined(CONFIG_CPU_SH7619) +# define SCSPTR0 0xf8400020 /* 16 bit SCIF */ +# define SCSPTR1 0xf8410020 /* 16 bit SCIF */ +# define SCSPTR2 0xf8420020 /* 16 bit SCIF */ +# define SCIF_ORER 0x0001 /* overrun error bit */ +# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +#elif defined(CONFIG_CPU_SHX3) +# define SCSPTR0 0xffc30020 /* 16 bit SCIF */ +# define SCSPTR1 0xffc40020 /* 16 bit SCIF */ +# define SCSPTR2 0xffc50020 /* 16 bit SCIF */ +# define SCSPTR3 0xffc60020 /* 16 bit SCIF */ +# define SCIF_ORER 0x0001 /* Overrun error bit */ +# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +#else +# error CPU subtype not defined +#endif + +/* SCSCR */ +#define SCI_CTRL_FLAGS_TIE 0x80 /* all */ +#define SCI_CTRL_FLAGS_RIE 0x40 /* all */ +#define SCI_CTRL_FLAGS_TE 0x20 /* all */ +#define SCI_CTRL_FLAGS_RE 0x10 /* all */ +#if defined(CONFIG_CPU_SH7750) || \ + defined(CONFIG_CPU_SH7091) || \ + defined(CONFIG_CPU_SH7750R) || \ + defined(CONFIG_CPU_SH7722) || \ + defined(CONFIG_CPU_SH7750S) || \ + defined(CONFIG_CPU_SH7751) || \ + defined(CONFIG_CPU_SH7751R) || \ + defined(CONFIG_CPU_SH7763) || \ + defined(CONFIG_CPU_SH7780) || \ + defined(CONFIG_CPU_SH7785) || \ + defined(CONFIG_CPU_SH7786) || \ + defined(CONFIG_CPU_SHX3) +#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ +#elif defined(CONFIG_CPU_SH7724) +#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8) +#else +#define SCI_CTRL_FLAGS_REIE 0 +#endif +/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ +/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ +/* SCI_CTRL_FLAGS_CKE1 0x02 * all */ +/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ + +/* SCxSR SCI */ +#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ +#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ +#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ +#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ +#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ +#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ +/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ +/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ + +#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) + +/* SCxSR SCIF */ +#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ +#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ +#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ +#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ +#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ +#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ +#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ +#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ + +#if defined(CONFIG_CPU_SH7705) || \ + defined(CONFIG_CPU_SH7720) || \ + defined(CONFIG_CPU_SH7721) || \ + defined(CONFIG_ARCH_SH7367) || \ + defined(CONFIG_ARCH_SH7377) || \ + defined(CONFIG_ARCH_SH7372) +# define SCIF_ORER 0x0200 +# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) +# define SCIF_RFDC_MASK 0x007f +# define SCIF_TXROOM_MAX 64 +#elif defined(CONFIG_CPU_SH7763) +# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) +# define SCIF_RFDC_MASK 0x007f +# define SCIF_TXROOM_MAX 64 +/* SH7763 SCIF2 support */ +# define SCIF2_RFDC_MASK 0x001f +# define SCIF2_TXROOM_MAX 16 +#else +# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) +# define SCIF_RFDC_MASK 0x001f +# define SCIF_TXROOM_MAX 16 +#endif + +#ifndef SCIF_ORER +#define SCIF_ORER 0x0000 +#endif + +#define SCxSR_TEND(port)\ + (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) +#define SCxSR_ERRORS(port)\ + (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) +#define SCxSR_RDxF(port)\ + (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) +#define SCxSR_TDxE(port)\ + (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) +#define SCxSR_FER(port)\ + (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) +#define SCxSR_PER(port)\ + (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) +#define SCxSR_BRK(port)\ + ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) +#define SCxSR_ORER(port)\ + (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) + +#if defined(CONFIG_CPU_SH7705) || \ + defined(CONFIG_CPU_SH7720) || \ + defined(CONFIG_CPU_SH7721) || \ + defined(CONFIG_ARCH_SH7367) || \ + defined(CONFIG_ARCH_SH7377) || \ + defined(CONFIG_ARCH_SH7372) +# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) +# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) +# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) +# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) +#else +# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) +# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) +# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) +# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) +#endif + +/* SCFCR */ +#define SCFCR_RFRST 0x0002 +#define SCFCR_TFRST 0x0004 +#define SCFCR_TCRST 0x4000 +#define SCFCR_MCE 0x0008 + +#define SCI_MAJOR 204 +#define SCI_MINOR_START 8 + +/* Generic serial flags */ +#define SCI_RX_THROTTLE 0x0000001 + +#define SCI_MAGIC 0xbabeface + +/* + * Events are used to schedule things to happen at timer-interrupt + * time, instead of at rs interrupt time. + */ +#define SCI_EVENT_WRITE_WAKEUP 0 + +#define SCI_IN(size, offset)\ + if ((size) == 8) {\ + return readb(port->membase + (offset));\ + } else {\ + return readw(port->membase + (offset));\ + } +#define SCI_OUT(size, offset, value)\ + if ((size) == 8) {\ + writeb(value, port->membase + (offset));\ + } else if ((size) == 16) {\ + writew(value, port->membase + (offset));\ + } + +#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ + static inline unsigned int sci_##name##_in(struct uart_port *port) {\ + if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ + SCI_IN(scif_size, scif_offset)\ + } else { /* PORT_SCI or PORT_SCIFA */\ + SCI_IN(sci_size, sci_offset);\ + }\ + }\ +static inline void sci_##name##_out(struct uart_port *port,\ + unsigned int value) {\ + if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ + SCI_OUT(scif_size, scif_offset, value)\ + } else { /* PORT_SCI or PORT_SCIFA */\ + SCI_OUT(sci_size, sci_offset, value);\ + }\ +} + +#ifdef CONFIG_H8300 +/* h8300 don't have SCIF */ +#define CPU_SCIF_FNS(name) \ + static inline unsigned int sci_##name##_in(struct uart_port *port) {\ + return 0;\ + }\ + static inline void sci_##name##_out(struct uart_port *port,\ + unsigned int value) {\ + } +#else +#define CPU_SCIF_FNS(name, scif_offset, scif_size) \ + static inline unsigned int sci_##name##_in(struct uart_port *port) {\ + SCI_IN(scif_size, scif_offset);\ + }\ + static inline void sci_##name##_out(struct uart_port *port,\ + unsigned int value) {\ + SCI_OUT(scif_size, scif_offset, value);\ + } +#endif + +#define CPU_SCI_FNS(name, sci_offset, sci_size)\ + static inline unsigned int sci_##name##_in(struct uart_port *port) {\ + SCI_IN(sci_size, sci_offset);\ + }\ + static inline void sci_##name##_out(struct uart_port *port,\ + unsigned int value) {\ + SCI_OUT(sci_size, sci_offset, value);\ + } + +#if defined(CONFIG_SH3) || \ + defined(CONFIG_ARCH_SH7367) || \ + defined(CONFIG_ARCH_SH7377) || \ + defined(CONFIG_ARCH_SH7372) +#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) +#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ + sh4_sci_offset, sh4_sci_size, \ + sh3_scif_offset, sh3_scif_size, \ + sh4_scif_offset, sh4_scif_size, \ + h8_sci_offset, h8_sci_size) \ + CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ + sh4_scif_offset, sh4_scif_size) +#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ + sh4_scif_offset, sh4_scif_size) \ + CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) +#elif defined(CONFIG_CPU_SH7705) || \ + defined(CONFIG_CPU_SH7720) || \ + defined(CONFIG_CPU_SH7721) || \ + defined(CONFIG_ARCH_SH7367) || \ + defined(CONFIG_ARCH_SH7377) +#define SCIF_FNS(name, scif_offset, scif_size) \ + CPU_SCIF_FNS(name, scif_offset, scif_size) +#elif defined(CONFIG_ARCH_SH7372) +#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ + sh4_scifb_offset, sh4_scifb_size) \ + CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ + sh4_scifb_offset, sh4_scifb_size) +#define SCIF_FNS(name, scif_offset, scif_size) \ + CPU_SCIF_FNS(name, scif_offset, scif_size) +#else +#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ + sh4_sci_offset, sh4_sci_size, \ + sh3_scif_offset, sh3_scif_size,\ + sh4_scif_offset, sh4_scif_size, \ + h8_sci_offset, h8_sci_size) \ + CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ + sh3_scif_offset, sh3_scif_size) +#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ + sh4_scif_offset, sh4_scif_size) \ + CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) +#endif +#elif defined(__H8300H__) || defined(__H8300S__) +#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ + sh4_sci_offset, sh4_sci_size, \ + sh3_scif_offset, sh3_scif_size,\ + sh4_scif_offset, sh4_scif_size, \ + h8_sci_offset, h8_sci_size) \ + CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) +#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ + sh4_scif_offset, sh4_scif_size) \ + CPU_SCIF_FNS(name) +#elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724) + #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ + sh4_scif_offset, sh4_scif_size) \ + CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ + sh4_scif_offset, sh4_scif_size) + #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ + CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) +#else +#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ + sh4_sci_offset, sh4_sci_size, \ + sh3_scif_offset, sh3_scif_size,\ + sh4_scif_offset, sh4_scif_size, \ + h8_sci_offset, h8_sci_size) \ + CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ + sh4_scif_offset, sh4_scif_size) +#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \ + sh4_scif_offset, sh4_scif_size) \ + CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) +#endif + +#if defined(CONFIG_CPU_SH7705) || \ + defined(CONFIG_CPU_SH7720) || \ + defined(CONFIG_CPU_SH7721) || \ + defined(CONFIG_ARCH_SH7367) || \ + defined(CONFIG_ARCH_SH7377) + +SCIF_FNS(SCSMR, 0x00, 16) +SCIF_FNS(SCBRR, 0x04, 8) +SCIF_FNS(SCSCR, 0x08, 16) +SCIF_FNS(SCTDSR, 0x0c, 8) +SCIF_FNS(SCFER, 0x10, 16) +SCIF_FNS(SCxSR, 0x14, 16) +SCIF_FNS(SCFCR, 0x18, 16) +SCIF_FNS(SCFDR, 0x1c, 16) +SCIF_FNS(SCxTDR, 0x20, 8) +SCIF_FNS(SCxRDR, 0x24, 8) +SCIF_FNS(SCLSR, 0x00, 0) +#elif defined(CONFIG_ARCH_SH7372) +SCIF_FNS(SCSMR, 0x00, 16) +SCIF_FNS(SCBRR, 0x04, 8) +SCIF_FNS(SCSCR, 0x08, 16) +SCIF_FNS(SCTDSR, 0x0c, 16) +SCIF_FNS(SCFER, 0x10, 16) +SCIF_FNS(SCxSR, 0x14, 16) +SCIF_FNS(SCFCR, 0x18, 16) +SCIF_FNS(SCFDR, 0x1c, 16) +SCIF_FNS(SCTFDR, 0x38, 16) +SCIF_FNS(SCRFDR, 0x3c, 16) +SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8) +SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) +SCIF_FNS(SCLSR, 0x00, 0) +#elif defined(CONFIG_CPU_SH7723) ||\ + defined(CONFIG_CPU_SH7724) +SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) +SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) +SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) +SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) +SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) +SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) +SCIx_FNS(SCSPTR, 0, 0, 0, 0) +SCIF_FNS(SCTDSR, 0x0c, 8) +SCIF_FNS(SCFER, 0x10, 16) +SCIF_FNS(SCFCR, 0x18, 16) +SCIF_FNS(SCFDR, 0x1c, 16) +SCIF_FNS(SCLSR, 0x24, 16) +#else +/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ +/* name off sz off sz off sz off sz off sz*/ +SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) +SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) +SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) +SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) +SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) +SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) +SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) +#if defined(CONFIG_CPU_SH7760) || \ + defined(CONFIG_CPU_SH7780) || \ + defined(CONFIG_CPU_SH7785) || \ + defined(CONFIG_CPU_SH7786) +SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) +SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) +SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) +SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) +SCIF_FNS(SCLSR, 0, 0, 0x28, 16) +#elif defined(CONFIG_CPU_SH7763) +SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) +SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) +SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) +SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) +SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) +SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) +SCIF_FNS(SCLSR, 0, 0, 0x28, 16) +#else +SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) +#if defined(CONFIG_CPU_SH7722) +SCIF_FNS(SCSPTR, 0, 0, 0, 0) +#else +SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) +#endif +SCIF_FNS(SCLSR, 0, 0, 0x24, 16) +#endif +#endif +#define sci_in(port, reg) sci_##reg##_in(port) +#define sci_out(port, reg, value) sci_##reg##_out(port, value) + +/* H8/300 series SCI pins assignment */ +#if defined(__H8300H__) || defined(__H8300S__) +static const struct __attribute__((packed)) { + int port; /* GPIO port no */ + unsigned short rx, tx; /* GPIO bit no */ +} h8300_sci_pins[] = { +#if defined(CONFIG_H83007) || defined(CONFIG_H83068) + { /* SCI0 */ + .port = H8300_GPIO_P9, + .rx = H8300_GPIO_B2, + .tx = H8300_GPIO_B0, + }, + { /* SCI1 */ + .port = H8300_GPIO_P9, + .rx = H8300_GPIO_B3, + .tx = H8300_GPIO_B1, + }, + { /* SCI2 */ + .port = H8300_GPIO_PB, + .rx = H8300_GPIO_B7, + .tx = H8300_GPIO_B6, + } +#elif defined(CONFIG_H8S2678) + { /* SCI0 */ + .port = H8300_GPIO_P3, + .rx = H8300_GPIO_B2, + .tx = H8300_GPIO_B0, + }, + { /* SCI1 */ + .port = H8300_GPIO_P3, + .rx = H8300_GPIO_B3, + .tx = H8300_GPIO_B1, + }, + { /* SCI2 */ + .port = H8300_GPIO_P5, + .rx = H8300_GPIO_B1, + .tx = H8300_GPIO_B0, + } +#endif +}; +#endif + +#if defined(CONFIG_CPU_SH7706) || \ + defined(CONFIG_CPU_SH7707) || \ + defined(CONFIG_CPU_SH7708) || \ + defined(CONFIG_CPU_SH7709) +static inline int sci_rxd_in(struct uart_port *port) +{ + if (port->mapbase == 0xfffffe80) + return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ + return 1; +} +#elif defined(CONFIG_CPU_SH7750) || \ + defined(CONFIG_CPU_SH7751) || \ + defined(CONFIG_CPU_SH7751R) || \ + defined(CONFIG_CPU_SH7750R) || \ + defined(CONFIG_CPU_SH7750S) || \ + defined(CONFIG_CPU_SH7091) +static inline int sci_rxd_in(struct uart_port *port) +{ + if (port->mapbase == 0xffe00000) + return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ + return 1; +} +#elif defined(__H8300H__) || defined(__H8300S__) +static inline int sci_rxd_in(struct uart_port *port) +{ + int ch = (port->mapbase - SMR0) >> 3; + return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; +} +#else /* default case for non-SCI processors */ +static inline int sci_rxd_in(struct uart_port *port) +{ + return 1; +} +#endif + +/* + * Values for the BitRate Register (SCBRR) + * + * The values are actually divisors for a frequency which can + * be internal to the SH3 (14.7456MHz) or derived from an external + * clock source. This driver assumes the internal clock is used; + * to support using an external clock source, config options or + * possibly command-line options would need to be added. + * + * Also, to support speeds below 2400 (why?) the lower 2 bits of + * the SCSMR register would also need to be set to non-zero values. + * + * -- Greg Banks 27Feb2000 + * + * Answer: The SCBRR register is only eight bits, and the value in + * it gets larger with lower baud rates. At around 2400 (depending on + * the peripherial module clock) you run out of bits. However the + * lower two bits of SCSMR allow the module clock to be divided down, + * scaling the value which is needed in SCBRR. + * + * -- Stuart Menefy - 23 May 2000 + * + * I meant, why would anyone bother with bitrates below 2400. + * + * -- Greg Banks - 7Jul2000 + * + * You "speedist"! How will I use my 110bps ASR-33 teletype with paper + * tape reader as a console! + * + * -- Mitch Davis - 15 Jul 2000 + */ + +#if (defined(CONFIG_CPU_SH7780) || \ + defined(CONFIG_CPU_SH7785) || \ + defined(CONFIG_CPU_SH7786)) && \ + !defined(CONFIG_SH_SH2007) +#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) +#elif defined(CONFIG_CPU_SH7705) || \ + defined(CONFIG_CPU_SH7720) || \ + defined(CONFIG_CPU_SH7721) || \ + defined(CONFIG_ARCH_SH7367) || \ + defined(CONFIG_ARCH_SH7377) || \ + defined(CONFIG_ARCH_SH7372) +#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) +#elif defined(CONFIG_CPU_SH7723) ||\ + defined(CONFIG_CPU_SH7724) +static inline int scbrr_calc(struct uart_port port, int bps, int clk) +{ + if (port.type == PORT_SCIF) + return (clk+16*bps)/(32*bps)-1; + else + return ((clk*2)+16*bps)/(16*bps)-1; +} +#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk) +#elif defined(__H8300H__) || defined(__H8300S__) +#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) +#else /* Generic SH */ +#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) +#endif diff --git a/fs/ubifs/misc.h b/fs/ubifs/misc.h index b745d8678..609232e93 100644 --- a/fs/ubifs/misc.h +++ b/fs/ubifs/misc.h @@ -260,7 +260,8 @@ struct ubifs_branch *ubifs_idx_branch(const struct ubifs_info *c, static inline void *ubifs_idx_key(const struct ubifs_info *c, const struct ubifs_idx_node *idx) { - return (void *)((struct ubifs_branch *)idx->branches)->key; + const __u8 *branch = idx->branches; + return (void *)((struct ubifs_branch *)branch)->key; } /** diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index aedf49510..a1ead70ee 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -440,7 +440,6 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_NET #define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM @@ -488,22 +487,6 @@ #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -/* - * PCI stuff - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/ - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT -#define CONFIG_SYS_PCI_MASTER_INIT - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ - #ifndef DEBUG #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ #endif diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 75e4e0761..090ab3bc2 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -137,14 +137,14 @@ /* global pointer */ /* start of global data */ #define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) + (CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE) /* monitor code */ #define SIZE 0x40000 -#define CONFIG_SYS_MONITOR_LEN (SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_MONITOR_LEN SIZE #define CONFIG_SYS_MONITOR_BASE \ - (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN) + (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \ + - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE) #define CONFIG_SYS_MONITOR_END \ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_SYS_MALLOC_LEN SIZE diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index ade6f7c70..8689513fb 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -24,6 +24,7 @@ #define CONFIG_CMD_IDE #define CONFIG_CMD_EXT2 #define CONFIG_DOS_PARTITION +#define CONFIG_CMD_SH_ZIMAGEBOOT /* SCIF */ #define CONFIG_SCIF_CONSOLE 1 diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h index 591fb5cd1..a95a75962 100644 --- a/include/configs/sh7785lcr.h +++ b/include/configs/sh7785lcr.h @@ -41,6 +41,7 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_RUN #define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_SH_ZIMAGEBOOT #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE diff --git a/include/configs/shmin.h b/include/configs/shmin.h new file mode 100644 index 000000000..54a1587ae --- /dev/null +++ b/include/configs/shmin.h @@ -0,0 +1,128 @@ +/* + * Configuation settings for shmin (T-SH7706LAN, T-SH7706LSR) + * + * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SHMIN_H +#define __SHMIN_H + +#define CONFIG_SH 1 +#define CONFIG_SH3 1 +#define CONFIG_CPU_SH7706 1 +/* T-SH7706LAN */ +#define CONFIG_SHMIN 1 +/* T-SH7706LSR*/ +/* #define CONFIG_T_SH7706LSR 1 */ + +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_NFS +#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS "console=ttySC0,115200" + +/* + * This board has original boot loader. If you write u-boot to 0x0, + * you should set undef. + */ +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +/* system */ +#define SHMIN_SDRAM_BASE (0x8C000000) +#define SHMIN_FLASH_BASE_1 (0xA0000000) + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ +#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ +#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ +/* Buffer size for Boot Arguments passed to kernel */ +#define CONFIG_SYS_BARGSIZE 512 +/* List of legal baudrate settings for this board */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600,14400,19200,38400,57600,115200 } + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE 1 +#define CONFIG_CONS_SCIF0 1 + +/* memory */ +#define CONFIG_SYS_SDRAM_BASE SHMIN_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024) +#define CONFIG_SYS_MEMTEST_START SHMIN_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - (256 * 1024)) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1 * 1024 * 1024) +#define CONFIG_SYS_MONITOR_BASE (SHMIN_FLASH_BASE_1 + CONFIG_ENV_SECT_SIZE) +#define CONFIG_SYS_MONITOR_LEN (128 * 1024) +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE 256 +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + +/* FLASH */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#undef CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_BASE SHMIN_FLASH_BASE_1 +#define CONFIG_SYS_MAX_FLASH_SECT 11 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ATMEL_TOTALSECT CONFIG_SYS_MAX_FLASH_SECT +#define CONFIG_SYS_ATMEL_REGION 4 +#define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} +#define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#ifdef CONFIG_T_SH7706LSR +#define CONFIG_ENV_ADDR (SHMIN_FLASH_BASE_1 + 70000) +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#endif + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 + +/* Board Clock */ +#ifdef CONFIG_T_SH7706LSR +#define CONFIG_SYS_CLK_FREQ 40000000 +#else +#define CONFIG_SYS_CLK_FREQ 33333333 +#endif /* CONFIG_T_SH7706LSR */ +#define CONFIG_SYS_TMU_CLK_DIV 4 +#define CONFIG_SYS_HZ 1000 + +/* Network device */ +#define CONFIG_DRIVER_NE2000 +#define CONFIG_DRIVER_NE2000_BASE (0xb0000300) + +#endif /* __SHMIN_H */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 1128f5ae1..d299929ab 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -33,11 +33,13 @@ struct mtd_info; +struct nand_flash_dev; /* Scan and identify a NAND device */ extern int nand_scan (struct mtd_info *mtd, int max_chips); /* Separate phases of nand_scan(), allowing board driver to intervene * and override command or ECC setup according to flash type */ -extern int nand_scan_ident(struct mtd_info *mtd, int max_chips); +extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, + const struct nand_flash_dev *table); extern int nand_scan_tail(struct mtd_info *mtd); /* Free resources held by the NAND device */ diff --git a/include/nand.h b/include/nand.h index a4524113d..7459bd033 100644 --- a/include/nand.h +++ b/include/nand.h @@ -115,7 +115,7 @@ typedef struct nand_erase_options nand_erase_options_t; int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, u_char *buffer); int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, - u_char *buffer); + u_char *buffer, int withoob); int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); #define NAND_LOCK_STATUS_TIGHT 0x01 diff --git a/include/netdev.h b/include/netdev.h index 7f6641935..1a542e8e9 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -61,6 +61,7 @@ int ethoc_initialize(u8 dev_num, int base_addr); int eth_3com_initialize (bd_t * bis); int fec_initialize (bd_t *bis); int fecmxc_initialize (bd_t *bis); +int ftgmac100_initialize(bd_t *bits); int ftmac100_initialize(bd_t *bits); int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); |