diff options
| -rw-r--r-- | board/freescale/mpc837xemds/mpc837xemds.c | 2 | ||||
| -rw-r--r-- | board/freescale/mpc837xerdb/mpc837xerdb.c | 2 | ||||
| -rw-r--r-- | cpu/mpc83xx/spd_sdram.c | 4 | ||||
| -rw-r--r-- | include/configs/MPC837XEMDS.h | 2 | ||||
| -rw-r--r-- | include/configs/MPC837XERDB.h | 2 | 
5 files changed, 6 insertions, 6 deletions
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index f7cd5fe17..40a505b1d 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -36,7 +36,7 @@ int board_early_init_f(void)  	u32 spridr = in_be32(&immr->sysconf.spridr);  	/* we check only part num, and don't look for CPU revisions */ -	switch (spridr) { +	switch (PARTID_NO_E(spridr)) {  	case SPR_8377:  		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,  				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index e054f4e44..f73fd5aa5 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -16,10 +16,10 @@  #include <i2c.h>  #include <asm/io.h>  #include <asm/fsl_serdes.h> +#include <fdt_support.h>  #include <spd_sdram.h>  #include <vsc7385.h> -  #if defined(CFG_DRAM_TEST)  int  testdram(void) diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 97ac7bb3d..70cd41029 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -601,7 +601,7 @@ long int spd_sdram()  	debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);  	/* Check DIMM data bus width */ -	if (spd.dataw_lsb == 0x20) { +	if (spd.dataw_lsb < 64) {  		if (spd.mem_type == SPD_MEMTYPE_DDR)  			burstlen = 0x03; /* 32 bit data bus, burst len is 8 */  		else @@ -763,7 +763,7 @@ long int spd_sdram()  		sdram_cfg |= SDRAM_CFG_RD_EN;  	/* The DIMM is 32bit width */ -	if (spd.dataw_lsb == 0x20) { +	if (spd.dataw_lsb < 64) {  		if (spd.mem_type == SPD_MEMTYPE_DDR)  			sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;  		if (spd.mem_type == SPD_MEMTYPE_DDR2) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 7c4e76e27..7fc0f7ef8 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -96,7 +96,7 @@   */  #define CFG_SCCR_TSEC1CM	1	/* CSB:eTSEC1 = 1:1 */  #define CFG_SCCR_TSEC2CM	1	/* CSB:eTSEC2 = 1:1 */ -#define CFG_SCCR_SATACM		SCCR_SATACM_1	/* CSB:SATA[0:3] = 1:1 */ +#define CFG_SCCR_SATACM		SCCR_SATACM_2	/* CSB:SATA[0:3] = 2:1 */  /*   * System IO Config diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index eaac525a3..c698ff84c 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -108,7 +108,7 @@  /* System Clock Configuration Register */  #define CFG_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */  #define CFG_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */ -#define CFG_SCCR_SATACM		SCCR_SATACM_1	/* SATA1-4 clock mode (0-3) */ +#define CFG_SCCR_SATACM		SCCR_SATACM_2	/* SATA1-4 clock mode (0-3) */  /*   * System IO Config  |