diff options
51 files changed, 2699 insertions, 578 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index cbe5c47f5..777d14186 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -239,6 +239,10 @@ The LEOX team <team@leox.org> ELPT860 MPC860T +Guennadi Liakhovetski <g.liakhovetski@gmx.de> + + linkstation MPC8241 + Dave Liu <daveliu@freescale.com> MPC8315ERDB MPC8315 @@ -412,13 +416,13 @@ Stephen Williams <steve@icarus.com> JSE PPC405GPr -John Zhan <zhanz@sinovee.com> +Roy Zang <tie-fei.zang@freescale.com> - svm_sc8xx MPC8xx + mpc7448hpc2 MPC7448 -Guennadi Liakhovetski <g.liakhovetski@gmx.de> +John Zhan <zhanz@sinovee.com> - linkstation MPC8241 + svm_sc8xx MPC8xx ------------------------------------------------------------------------- @@ -523,6 +527,10 @@ Rolf Offermanns <rof@sysgo.de> shannon SA1100 +Kyungmin Park <kyungmin.park@samsung.com> + + apollon ARM1136EJS + Peter Pearse <peter.pearse@arm.com> integratorcp All current ARM supplied & supported core modules -see http://www.arm.com/products/DevTools/Hardware_Platforms.html @@ -552,6 +560,13 @@ Robert Schwebel <r.schwebel@pengutronix.de> csb226 xscale innokom xscale +Michael Schwingen <michael@schwingen.org> + + actux1 xscale + actux2 xscale + actux3 xscale + actux4 xscale + Andrea Scian <andrea.scian@dave-tech.it> B2 ARM7TDMI (S3C44B0X) @@ -566,22 +581,11 @@ Richard Woodruff <r-woodruff2@ti.com> omap2420h4 ARM1136EJS -Kyungmin Park <kyungmin.park@samsung.com> - - apollon ARM1136EJS - Alex Züpke <azu@sysgo.de> lart SA1100 dnp1110 SA1110 -Michael Schwingen <michael@schwingen.org> - - actux1 xscale - actux2 xscale - actux3 xscale - actux4 xscale - ------------------------------------------------------------------------- Unknown / orphaned boards: @@ -679,6 +683,10 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com> TASREG MCF5249 +Hayden Fraser <Hayden.Fraser@freescale.com> + + M5253EVBE mcf52x2 + TsiChung Liew <Tsi-Chung.Liew@freescale.com> M52277EVB mcf5227x @@ -689,10 +697,6 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com> M5475EVB mcf547x_8x M5485EVB mcf547x_8x -Hayden Fraser <Hayden.Fraser@freescale.com> - - M5253EVBE mcf52x2 - ######################################################################### # AVR32 Systems: # # # @@ -716,6 +720,10 @@ Haavard Skinnemoen <hskinnemoen@atmel.com> # Board CPU # ######################################################################### +Yusuke Goda <goda.yusuke@renesas.com> + + MIGO-R SH7722 + Nobuhiro Iwamatsu <iwamatsu@nigauri.org> MS7750SE SH7750 @@ -732,10 +740,6 @@ Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> MS7720SE SH7720 -Yusuke Goda <goda.yusuke@renesas.com> - - MIGO-R SH7722 - ######################################################################### # Blackfin Systems: # # # @@ -98,7 +98,7 @@ Where we come from: - create ARMBoot project (http://sourceforge.net/projects/armboot) - add other CPU families (starting with ARM) - create U-Boot project (http://sourceforge.net/projects/u-boot) -- current project page: see http://www.denx.de/wiki/UBoot +- current project page: see http://www.denx.de/wiki/U-Boot Names and Spelling: @@ -3903,7 +3903,7 @@ may be rejected, even when they contain important and valuable stuff. Patches shall be sent to the u-boot-users mailing list. -Please see http://www.denx.de/wiki/UBoot/Patches for details. +Please see http://www.denx.de/wiki/U-Boot/Patches for details. When you send a patch, please include the following information with it: diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile index 5b956823f..52d0d3c58 100644 --- a/board/ads5121/Makefile +++ b/board/ads5121/Makefile @@ -27,7 +27,7 @@ $(shell mkdir -p $(OBJTREE)/board/freescale/common) LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o iopin.o +COBJS-y := $(BOARD).o COBJS-${CONFIG_FSL_DIU_FB} += ads5121_diu.o COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_diu_fb.o COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_logo_bmp.o diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 8452054e6..ba3d7d2a0 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -23,14 +23,12 @@ #include <common.h> #include <mpc512x.h> -#include "iopin.h" #include <asm/bitops.h> #include <command.h> #include <fdt_support.h> #ifdef CONFIG_MISC_INIT_R #include <i2c.h> #endif -#include "iopin.h" /* for iopin_initialize() prototype */ /* Clocks in use */ #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ @@ -124,7 +122,7 @@ long int fixed_sdram (void) u32 i; /* Initialize IO Control */ - im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR; + im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR; /* Initialize DDR Local Window */ im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000; @@ -237,6 +235,56 @@ int misc_init_r(void) return 0; } +static iopin_t ioregs_init[] = { + /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */ + { + IOCTL_SPDIF_TXCLK, 3, 0, + IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* Set highest Slew on 9 PATA pins */ + { + IOCTL_PATA_CE1, 9, 1, + IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC1=FEC_COL Sets Next 15 to FEC pads */ + { + IOCTL_PSC0_0, 15, 0, + IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC1=SPDIF_TXCLK */ + { + IOCTL_LPC_CS1, 1, 0, + IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) + }, + /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */ + { + IOCTL_I2C1_SCL, 2, 0, + IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) + }, + /* FUNC2=DIU CLK */ + { + IOCTL_PSC6_0, 1, 0, + IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) + }, + /* FUNC2=DIU_HSYNC */ + { + IOCTL_PSC6_1, 1, 0, + IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */ + { + IOCTL_PSC6_4, 26, 0, + IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } +}; int checkboard (void) { @@ -246,7 +294,9 @@ int checkboard (void) printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", brd_rev, cpld_rev); /* initialize function mux & slew rate IO inter alia on IO Pins */ - iopin_initialize(); + + + iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0])); return 0; } diff --git a/board/ads5121/iopin.c b/board/ads5121/iopin.c deleted file mode 100644 index a6792a0e2..000000000 --- a/board/ads5121/iopin.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2008 - * Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com - * mpc512x I/O pin/pad initialization for the ADS5121 board - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <linux/types.h> -#include "iopin.h" - -/* IO pin fields */ -#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ -#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ -#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */ -#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */ -#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */ -#define IO_PIN_DS(v) ((v)) /* slew rate */ - -static struct iopin_t { - int p_offset; /* offset from IOCTL_MEM_OFFSET */ - int nr_pins; /* number of pins to set this way */ - int bit_or; /* or in the value instead of overwrite */ - u_long val; /* value to write or or */ -} ioregs_init[] = { - /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */ - { - IOCTL_SPDIF_TXCLK, 3, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* Set highest Slew on 9 PATA pins */ - { - IOCTL_PATA_CE1, 9, 1, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=FEC_COL Sets Next 15 to FEC pads */ - { - IOCTL_PSC0_0, 15, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=SPDIF_TXCLK */ - { - IOCTL_LPC_CS1, 1, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, - /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */ - { - IOCTL_I2C1_SCL, 2, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, - /* FUNC2=DIU CLK */ - { - IOCTL_PSC6_0, 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, - /* FUNC2=DIU_HSYNC */ - { - IOCTL_PSC6_1, 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */ - { - IOCTL_PSC6_4, 26, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - } -}; - -void iopin_initialize(void) -{ - short i, j, n, p; - u_long *reg; - immap_t *im = (immap_t *)CFG_IMMR; - - reg = (u_long *)&(im->io_ctrl.regs[0]); - - if (sizeof(ioregs_init) == 0) - return; - - n = sizeof(ioregs_init) / sizeof(ioregs_init[0]); - - for (i = 0; i < n; i++) { - for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); - p < ioregs_init[i].nr_pins; p++, j++) { - if (ioregs_init[i].bit_or) - reg[j] |= ioregs_init[i].val; - else - reg[j] = ioregs_init[i].val; - } - } - return; -} diff --git a/board/ads5121/iopin.h b/board/ads5121/iopin.h deleted file mode 100644 index 7ef8472f1..000000000 --- a/board/ads5121/iopin.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * (C) Copyright 2008 - * Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com - * mpc512x I/O pin/pad initialization for the ADS5121 board - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define IOCTL_MEM 0x000 -#define IOCTL_GP 0x004 -#define IOCTL_LPC_CLK 0x008 -#define IOCTL_LPC_OE 0x00C -#define IOCTL_LPC_RWB 0x010 -#define IOCTL_LPC_ACK 0x014 -#define IOCTL_LPC_CS0 0x018 -#define IOCTL_NFC_CE0 0x01C -#define IOCTL_LPC_CS1 0x020 -#define IOCTL_LPC_CS2 0x024 -#define IOCTL_LPC_AX03 0x028 -#define IOCTL_EMB_AX02 0x02C -#define IOCTL_EMB_AX01 0x030 -#define IOCTL_EMB_AX00 0x034 -#define IOCTL_EMB_AD31 0x038 -#define IOCTL_EMB_AD30 0x03C -#define IOCTL_EMB_AD29 0x040 -#define IOCTL_EMB_AD28 0x044 -#define IOCTL_EMB_AD27 0x048 -#define IOCTL_EMB_AD26 0x04C -#define IOCTL_EMB_AD25 0x050 -#define IOCTL_EMB_AD24 0x054 -#define IOCTL_EMB_AD23 0x058 -#define IOCTL_EMB_AD22 0x05C -#define IOCTL_EMB_AD21 0x060 -#define IOCTL_EMB_AD20 0x064 -#define IOCTL_EMB_AD19 0x068 -#define IOCTL_EMB_AD18 0x06C -#define IOCTL_EMB_AD17 0x070 -#define IOCTL_EMB_AD16 0x074 -#define IOCTL_EMB_AD15 0x078 -#define IOCTL_EMB_AD14 0x07C -#define IOCTL_EMB_AD13 0x080 -#define IOCTL_EMB_AD12 0x084 -#define IOCTL_EMB_AD11 0x088 -#define IOCTL_EMB_AD10 0x08C -#define IOCTL_EMB_AD09 0x090 -#define IOCTL_EMB_AD08 0x094 -#define IOCTL_EMB_AD07 0x098 -#define IOCTL_EMB_AD06 0x09C -#define IOCTL_EMB_AD05 0x0A0 -#define IOCTL_EMB_AD04 0x0A4 -#define IOCTL_EMB_AD03 0x0A8 -#define IOCTL_EMB_AD02 0x0AC -#define IOCTL_EMB_AD01 0x0B0 -#define IOCTL_EMB_AD00 0x0B4 -#define IOCTL_PATA_CE1 0x0B8 -#define IOCTL_PATA_CE2 0x0BC -#define IOCTL_PATA_ISOLATE 0x0C0 -#define IOCTL_PATA_IOR 0x0C4 -#define IOCTL_PATA_IOW 0x0C8 -#define IOCTL_PATA_IOCHRDY 0x0CC -#define IOCTL_PATA_INTRQ 0x0D0 -#define IOCTL_PATA_DRQ 0x0D4 -#define IOCTL_PATA_DACK 0x0D8 -#define IOCTL_NFC_WP 0x0DC -#define IOCTL_NFC_RB 0x0E0 -#define IOCTL_NFC_ALE 0x0E4 -#define IOCTL_NFC_CLE 0x0E8 -#define IOCTL_NFC_WE 0x0EC -#define IOCTL_NFC_RE 0x0F0 -#define IOCTL_PCI_AD31 0x0F4 -#define IOCTL_PCI_AD30 0x0F8 -#define IOCTL_PCI_AD29 0x0FC -#define IOCTL_PCI_AD28 0x100 -#define IOCTL_PCI_AD27 0x104 -#define IOCTL_PCI_AD26 0x108 -#define IOCTL_PCI_AD25 0x10C -#define IOCTL_PCI_AD24 0x110 -#define IOCTL_PCI_AD23 0x114 -#define IOCTL_PCI_AD22 0x118 -#define IOCTL_PCI_AD21 0x11C -#define IOCTL_PCI_AD20 0x120 -#define IOCTL_PCI_AD19 0x124 -#define IOCTL_PCI_AD18 0x128 -#define IOCTL_PCI_AD17 0x12C -#define IOCTL_PCI_AD16 0x130 -#define IOCTL_PCI_AD15 0x134 -#define IOCTL_PCI_AD14 0x138 -#define IOCTL_PCI_AD13 0x13C -#define IOCTL_PCI_AD12 0x140 -#define IOCTL_PCI_AD11 0x144 -#define IOCTL_PCI_AD10 0x148 -#define IOCTL_PCI_AD09 0x14C -#define IOCTL_PCI_AD08 0x150 -#define IOCTL_PCI_AD07 0x154 -#define IOCTL_PCI_AD06 0x158 -#define IOCTL_PCI_AD05 0x15C -#define IOCTL_PCI_AD04 0x160 -#define IOCTL_PCI_AD03 0x164 -#define IOCTL_PCI_AD02 0x168 -#define IOCTL_PCI_AD01 0x16C -#define IOCTL_PCI_AD00 0x170 -#define IOCTL_PCI_CBE0 0x174 -#define IOCTL_PCI_CBE1 0x178 -#define IOCTL_PCI_CBE2 0x17C -#define IOCTL_PCI_CBE3 0x180 -#define IOCTL_PCI_GNT2 0x184 -#define IOCTL_PCI_REQ2 0x188 -#define IOCTL_PCI_GNT1 0x18C -#define IOCTL_PCI_REQ1 0x190 -#define IOCTL_PCI_GNT0 0x194 -#define IOCTL_PCI_REQ0 0x198 -#define IOCTL_PCI_INTA 0x19C -#define IOCTL_PCI_CLK 0x1A0 -#define IOCTL_PCI_RST_OUT 0x1A4 -#define IOCTL_PCI_FRAME 0x1A8 -#define IOCTL_PCI_IDSEL 0x1AC -#define IOCTL_PCI_DEVSEL 0x1B0 -#define IOCTL_PCI_IRDY 0x1B4 -#define IOCTL_PCI_TRDY 0x1B8 -#define IOCTL_PCI_STOP 0x1BC -#define IOCTL_PCI_PAR 0x1C0 -#define IOCTL_PCI_PERR 0x1C4 -#define IOCTL_PCI_SERR 0x1C8 -#define IOCTL_SPDIF_TXCLK 0x1CC -#define IOCTL_SPDIF_TX 0x1D0 -#define IOCTL_SPDIF_RX 0x1D4 -#define IOCTL_I2C0_SCL 0x1D8 -#define IOCTL_I2C0_SDA 0x1DC -#define IOCTL_I2C1_SCL 0x1E0 -#define IOCTL_I2C1_SDA 0x1E4 -#define IOCTL_I2C2_SCL 0x1E8 -#define IOCTL_I2C2_SDA 0x1EC -#define IOCTL_IRQ0 0x1F0 -#define IOCTL_IRQ1 0x1F4 -#define IOCTL_CAN1_TX 0x1F8 -#define IOCTL_CAN2_TX 0x1FC -#define IOCTL_J1850_TX 0x200 -#define IOCTL_J1850_RX 0x204 -#define IOCTL_PSC_MCLK_IN 0x208 -#define IOCTL_PSC0_0 0x20C -#define IOCTL_PSC0_1 0x210 -#define IOCTL_PSC0_2 0x214 -#define IOCTL_PSC0_3 0x218 -#define IOCTL_PSC0_4 0x21C -#define IOCTL_PSC1_0 0x220 -#define IOCTL_PSC1_1 0x224 -#define IOCTL_PSC1_2 0x228 -#define IOCTL_PSC1_3 0x22C -#define IOCTL_PSC1_4 0x230 -#define IOCTL_PSC2_0 0x234 -#define IOCTL_PSC2_1 0x238 -#define IOCTL_PSC2_2 0x23C -#define IOCTL_PSC2_3 0x240 -#define IOCTL_PSC2_4 0x244 -#define IOCTL_PSC3_0 0x248 -#define IOCTL_PSC3_1 0x24C -#define IOCTL_PSC3_2 0x250 -#define IOCTL_PSC3_3 0x254 -#define IOCTL_PSC3_4 0x258 -#define IOCTL_PSC4_0 0x25C -#define IOCTL_PSC4_1 0x260 -#define IOCTL_PSC4_2 0x264 -#define IOCTL_PSC4_3 0x268 -#define IOCTL_PSC4_4 0x26C -#define IOCTL_PSC5_0 0x270 -#define IOCTL_PSC5_1 0x274 -#define IOCTL_PSC5_2 0x278 -#define IOCTL_PSC5_3 0x27C -#define IOCTL_PSC5_4 0x280 -#define IOCTL_PSC6_0 0x284 -#define IOCTL_PSC6_1 0x288 -#define IOCTL_PSC6_2 0x28C -#define IOCTL_PSC6_3 0x290 -#define IOCTL_PSC6_4 0x294 -#define IOCTL_PSC7_0 0x298 -#define IOCTL_PSC7_1 0x29C -#define IOCTL_PSC7_2 0x2A0 -#define IOCTL_PSC7_3 0x2A4 -#define IOCTL_PSC7_4 0x2A8 -#define IOCTL_PSC8_0 0x2AC -#define IOCTL_PSC8_1 0x2B0 -#define IOCTL_PSC8_2 0x2B4 -#define IOCTL_PSC8_3 0x2B8 -#define IOCTL_PSC8_4 0x2BC -#define IOCTL_PSC9_0 0x2C0 -#define IOCTL_PSC9_1 0x2C4 -#define IOCTL_PSC9_2 0x2C8 -#define IOCTL_PSC9_3 0x2CC -#define IOCTL_PSC9_4 0x2D0 -#define IOCTL_PSC10_0 0x2D4 -#define IOCTL_PSC10_1 0x2D8 -#define IOCTL_PSC10_2 0x2DC -#define IOCTL_PSC10_3 0x2E0 -#define IOCTL_PSC10_4 0x2E4 -#define IOCTL_PSC11_0 0x2E8 -#define IOCTL_PSC11_1 0x2EC -#define IOCTL_PSC11_2 0x2F0 -#define IOCTL_PSC11_3 0x2F4 -#define IOCTL_PSC11_4 0x2F8 -#define IOCTL_HRESET 0x2FC -#define IOCTL_SRESET 0x300 -#define IOCTL_CKSTP_OUT 0x304 -#define IOCTL_USB2_VBUS_PWR_FAULT 0x308 -#define IOCTL_USB2_VBUS_PWR_SELECT 0x30C -#define IOCTL_USB2_PHY_DRVV_BUS 0x310 - -extern void iopin_initialize(void); diff --git a/board/freescale/mpc8540ads/u-boot.lds b/board/freescale/mpc8540ads/u-boot.lds index 0e4f5a245..515d32085 100644 --- a/board/freescale/mpc8540ads/u-boot.lds +++ b/board/freescale/mpc8540ads/u-boot.lds @@ -26,6 +26,12 @@ OUTPUT_ARCH(powerpc) /* Do we need any of these for elf? __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + SECTIONS { /* Read-only sections, merged into text segment: */ @@ -57,7 +63,7 @@ SECTIONS *(.text) *(.fixup) *(.got1) - } + } :text _etext = .; PROVIDE (etext = .); .rodata : @@ -66,7 +72,7 @@ SECTIONS *(.rodata1) *(.rodata.str1.4) *(.eh_frame) - } + } :text .fini : { *(.fini) } =0 .ctors : { *(.ctors) } .dtors : { *(.dtors) } @@ -118,12 +124,12 @@ SECTIONS .bootpg ADDR(.text) + 0x7f000 : { cpu/mpc85xx/start.o (.bootpg) - } = 0xffff + } :text = 0xffff .resetvec ADDR(.text) + 0x7fffc : { *(.resetvec) - } = 0xffff + } :text = 0xffff . = ADDR(.text) + 0x80000; @@ -134,7 +140,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) - } + } :bss . = ALIGN(4); _end = . ; diff --git a/board/freescale/mpc8541cds/u-boot.lds b/board/freescale/mpc8541cds/u-boot.lds index 1c583de83..d728d8b73 100644 --- a/board/freescale/mpc8541cds/u-boot.lds +++ b/board/freescale/mpc8541cds/u-boot.lds @@ -23,6 +23,12 @@ OUTPUT_ARCH(powerpc) /* Do we need any of these for elf? __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + SECTIONS { /* Read-only sections, merged into text segment: */ @@ -54,7 +60,7 @@ SECTIONS *(.text) *(.fixup) *(.got1) - } + } :text _etext = .; PROVIDE (etext = .); .rodata : @@ -63,7 +69,7 @@ SECTIONS *(.rodata1) *(.rodata.str1.4) *(.eh_frame) - } + } :text .fini : { *(.fini) } =0 .ctors : { *(.ctors) } .dtors : { *(.dtors) } @@ -115,12 +121,12 @@ SECTIONS .bootpg ADDR(.text) + 0x7f000 : { cpu/mpc85xx/start.o (.bootpg) - } = 0xffff + } :text = 0xffff .resetvec ADDR(.text) + 0x7fffc : { *(.resetvec) - } = 0xffff + } :text = 0xffff . = ADDR(.text) + 0x80000; @@ -131,7 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) - } + } :bss . = ALIGN(4); _end = . ; diff --git a/board/freescale/mpc8544ds/u-boot.lds b/board/freescale/mpc8544ds/u-boot.lds index 500e6475a..a05ece5cf 100644 --- a/board/freescale/mpc8544ds/u-boot.lds +++ b/board/freescale/mpc8544ds/u-boot.lds @@ -23,6 +23,12 @@ OUTPUT_ARCH(powerpc) /* Do we need any of these for elf? __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + SECTIONS { /* Read-only sections, merged into text segment: */ @@ -54,7 +60,7 @@ SECTIONS *(.text) *(.fixup) *(.got1) - } + } :text _etext = .; PROVIDE (etext = .); .rodata : @@ -63,7 +69,7 @@ SECTIONS *(.rodata1) *(.rodata.str1.4) *(.eh_frame) - } + } :text .fini : { *(.fini) } =0 .ctors : { *(.ctors) } .dtors : { *(.dtors) } @@ -115,12 +121,12 @@ SECTIONS .bootpg ADDR(.text) + 0x7f000 : { cpu/mpc85xx/start.o (.bootpg) - } = 0xffff + } :text = 0xffff .resetvec ADDR(.text) + 0x7fffc : { *(.resetvec) - } = 0xffff + } :text = 0xffff . = ADDR(.text) + 0x80000; @@ -131,7 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) - } + } :bss . = ALIGN(4); _end = . ; diff --git a/board/freescale/mpc8548cds/u-boot.lds b/board/freescale/mpc8548cds/u-boot.lds index 6b9339511..d4a2f72a5 100644 --- a/board/freescale/mpc8548cds/u-boot.lds +++ b/board/freescale/mpc8548cds/u-boot.lds @@ -23,6 +23,12 @@ OUTPUT_ARCH(powerpc) /* Do we need any of these for elf? __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + SECTIONS { /* Read-only sections, merged into text segment: */ @@ -54,7 +60,7 @@ SECTIONS *(.text) *(.fixup) *(.got1) - } + } :text _etext = .; PROVIDE (etext = .); .rodata : @@ -63,7 +69,7 @@ SECTIONS *(.rodata1) *(.rodata.str1.4) *(.eh_frame) - } + } :text .fini : { *(.fini) } =0 .ctors : { *(.ctors) } .dtors : { *(.dtors) } @@ -115,12 +121,12 @@ SECTIONS .bootpg ADDR(.text) + 0x7f000 : { cpu/mpc85xx/start.o (.bootpg) - } = 0xffff + } :text = 0xffff .resetvec ADDR(.text) + 0x7fffc : { *(.resetvec) - } = 0xffff + } :text = 0xffff . = ADDR(.text) + 0x80000; @@ -131,7 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) - } + } :bss . = ALIGN(4); _end = . ; diff --git a/board/freescale/mpc8555cds/u-boot.lds b/board/freescale/mpc8555cds/u-boot.lds index a18b3a7b5..11885e820 100644 --- a/board/freescale/mpc8555cds/u-boot.lds +++ b/board/freescale/mpc8555cds/u-boot.lds @@ -23,6 +23,12 @@ OUTPUT_ARCH(powerpc) /* Do we need any of these for elf? __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + SECTIONS { /* Read-only sections, merged into text segment: */ @@ -54,7 +60,7 @@ SECTIONS *(.text) *(.fixup) *(.got1) - } + } :text _etext = .; PROVIDE (etext = .); .rodata : @@ -63,7 +69,7 @@ SECTIONS *(.rodata1) *(.rodata.str1.4) *(.eh_frame) - } + } :text .fini : { *(.fini) } =0 .ctors : { *(.ctors) } .dtors : { *(.dtors) } @@ -115,12 +121,12 @@ SECTIONS .bootpg ADDR(.text) + 0x7f000 : { cpu/mpc85xx/start.o (.bootpg) - } = 0xffff + } :text = 0xffff .resetvec ADDR(.text) + 0x7fffc : { *(.resetvec) - } = 0xffff + } :text = 0xffff . = ADDR(.text) + 0x80000; @@ -131,7 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) - } + } :bss . = ALIGN(4); _end = . ; diff --git a/board/freescale/mpc8560ads/u-boot.lds b/board/freescale/mpc8560ads/u-boot.lds index 0e4f5a245..515d32085 100644 --- a/board/freescale/mpc8560ads/u-boot.lds +++ b/board/freescale/mpc8560ads/u-boot.lds @@ -26,6 +26,12 @@ OUTPUT_ARCH(powerpc) /* Do we need any of these for elf? __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + SECTIONS { /* Read-only sections, merged into text segment: */ @@ -57,7 +63,7 @@ SECTIONS *(.text) *(.fixup) *(.got1) - } + } :text _etext = .; PROVIDE (etext = .); .rodata : @@ -66,7 +72,7 @@ SECTIONS *(.rodata1) *(.rodata.str1.4) *(.eh_frame) - } + } :text .fini : { *(.fini) } =0 .ctors : { *(.ctors) } .dtors : { *(.dtors) } @@ -118,12 +124,12 @@ SECTIONS .bootpg ADDR(.text) + 0x7f000 : { cpu/mpc85xx/start.o (.bootpg) - } = 0xffff + } :text = 0xffff .resetvec ADDR(.text) + 0x7fffc : { *(.resetvec) - } = 0xffff + } :text = 0xffff . = ADDR(.text) + 0x80000; @@ -134,7 +140,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) - } + } :bss . = ALIGN(4); _end = . ; diff --git a/board/freescale/mpc8568mds/u-boot.lds b/board/freescale/mpc8568mds/u-boot.lds index 9d245e4ec..ad96410b2 100644 --- a/board/freescale/mpc8568mds/u-boot.lds +++ b/board/freescale/mpc8568mds/u-boot.lds @@ -23,6 +23,12 @@ OUTPUT_ARCH(powerpc) /* Do we need any of these for elf? __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + SECTIONS { /* Read-only sections, merged into text segment: */ @@ -54,7 +60,7 @@ SECTIONS *(.text) *(.fixup) *(.got1) - } + } :text _etext = .; PROVIDE (etext = .); .rodata : @@ -63,7 +69,7 @@ SECTIONS *(.rodata1) *(.rodata.str1.4) *(.eh_frame) - } + } :text .fini : { *(.fini) } =0 .ctors : { *(.ctors) } .dtors : { *(.dtors) } @@ -115,12 +121,12 @@ SECTIONS .bootpg ADDR(.text) + 0x7f000 : { cpu/mpc85xx/start.o (.bootpg) - } = 0xffff + } :text = 0xffff .resetvec ADDR(.text) + 0x7fffc : { *(.resetvec) - } = 0xffff + } :text = 0xffff . = ADDR(.text) + 0x80000; @@ -131,7 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) - } + } :bss . = ALIGN(4); _end = . ; diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 18d71008d..2dffdfac8 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -138,7 +138,6 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) memset ((void *)&images, 0, sizeof (images)); images.verify = getenv_yesno ("verify"); - images.autostart = getenv_yesno ("autostart"); images.lmb = &lmb; lmb_init(&lmb); diff --git a/common/cmd_load.c b/common/cmd_load.c index 1b75a7b5e..ab167f5ab 100644 --- a/common/cmd_load.c +++ b/common/cmd_load.c @@ -424,7 +424,6 @@ write_record (char *buf) #define untochar(x) ((int) (((x) - SPACE) & 0xff)) extern int os_data_count; -extern int os_data_header[8]; static void set_kerm_bin_mode(unsigned long *); static int k_recv(void); @@ -631,11 +630,6 @@ void send_nack (int n) } -/* os_data_* takes an OS Open image and puts it into memory, and - puts the boot header in an array named os_data_header - - if image is binary, no header is stored in os_data_header. -*/ void (*os_data_init) (void); void (*os_data_char) (char new_char); static int os_data_state, os_data_state_saved; @@ -643,25 +637,28 @@ int os_data_count; static int os_data_count_saved; static char *os_data_addr, *os_data_addr_saved; static char *bin_start_address; -int os_data_header[8]; + static void bin_data_init (void) { os_data_state = 0; os_data_count = 0; os_data_addr = bin_start_address; } + static void os_data_save (void) { os_data_state_saved = os_data_state; os_data_count_saved = os_data_count; os_data_addr_saved = os_data_addr; } + static void os_data_restore (void) { os_data_state = os_data_state_saved; os_data_count = os_data_count_saved; os_data_addr = os_data_addr_saved; } + static void bin_data_char (char new_char) { switch (os_data_state) { @@ -671,6 +668,7 @@ static void bin_data_char (char new_char) break; } } + static void set_kerm_bin_mode (unsigned long *addr) { bin_start_address = (char *) addr; @@ -686,16 +684,19 @@ void k_data_init (void) k_data_escape = 0; os_data_init (); } + void k_data_save (void) { k_data_escape_saved = k_data_escape; os_data_save (); } + void k_data_restore (void) { k_data_escape = k_data_escape_saved; os_data_restore (); } + void k_data_char (char new_char) { if (k_data_escape) { diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c index ce99a38ca..d6d337628 100644 --- a/common/cmd_onenand.c +++ b/common/cmd_onenand.c @@ -58,8 +58,6 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } else { start = simple_strtoul(argv[2], NULL, 10); end = simple_strtoul(argv[3], NULL, 10); - start -= (unsigned long)onenand_chip.base; - end -= (unsigned long)onenand_chip.base; start >>= onenand_chip.erase_shift; end >>= onenand_chip.erase_shift; @@ -92,8 +90,6 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) size_t retlen = 0; int oob = strncmp(argv[1], "read.oob", 8) ? 0 : 1; - ofs -= (unsigned long)onenand_chip.base; - if (oob) onenand_read_oob(&onenand_mtd, ofs, len, &retlen, (u_char *) addr); @@ -111,8 +107,6 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) size_t len = simple_strtoul(argv[4], NULL, 16); size_t retlen = 0; - ofs -= (unsigned long)onenand_chip.base; - onenand_write(&onenand_mtd, ofs, len, &retlen, (u_char *) addr); printf("Done\n"); diff --git a/common/env_onenand.c b/common/env_onenand.c index ad5b1d7aa..dbd0883fa 100644 --- a/common/env_onenand.c +++ b/common/env_onenand.c @@ -66,7 +66,6 @@ void env_relocate_spec(void) size_t retlen; env_addr = CFG_ENV_ADDR; - env_addr -= (unsigned long) onenand_chip.base; /* Check OneNAND exist */ if (onenand_mtd.oobblock) @@ -101,7 +100,6 @@ int saveenv(void) instr.len = CFG_ENV_SIZE; instr.addr = env_addr; - instr.addr -= (unsigned long)onenand_chip.base; if (onenand_erase(&onenand_mtd, &instr)) { printf("OneNAND: erase failed at 0x%08lx\n", env_addr); return 1; @@ -111,7 +109,6 @@ int saveenv(void) env_ptr->crc = crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)); - env_addr -= (unsigned long)onenand_chip.base; if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.oobblock, &retlen, (u_char *) env_ptr)) { printf("OneNAND: write failed at 0x%08x\n", instr.addr); diff --git a/common/image.c b/common/image.c index 535c302d4..180734838 100644 --- a/common/image.c +++ b/common/image.c @@ -189,6 +189,22 @@ int image_check_dcrc (image_header_t *hdr) return (dcrc == image_get_dcrc (hdr)); } +void memmove_wd (void *to, void *from, size_t len, ulong chunksz) +{ +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + while (len > 0) { + size_t tail = (len > chunksz) ? chunksz : len; + WATCHDOG_RESET (); + memmove (to, from, tail); + to += tail; + from += tail; + len -= tail; + } +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + memmove (to, from, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ +} +#endif /* USE_HOSTCC */ /** * image_multi_count - get component (sub-image) count @@ -833,7 +849,7 @@ int boot_get_ramdisk (int argc, char *argv[], bootm_headers_t *images, rd_noffset = fit_conf_get_ramdisk_node (fit_hdr, cfg_noffset); if (rd_noffset < 0) { debug ("* ramdisk: no ramdisk in config\n"); - return 1; + return 0; } } #endif diff --git a/common/lcd.c b/common/lcd.c index e3347ec93..8d770f3e7 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -793,7 +793,7 @@ static void *lcd_logo (void) sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__); lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, (uchar *)info, strlen(info)); - sprintf (info, "(C) 2004 DENX Software Engineering"); + sprintf (info, "(C) 2008 DENX Software Engineering GmbH"); lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT, (uchar *)info, strlen(info)); diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile index 2be35b2bc..8ba8ae875 100644 --- a/cpu/mpc512x/Makefile +++ b/cpu/mpc512x/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o +COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o iopin.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c index b59f36d5f..81bae41b9 100644 --- a/cpu/mpc512x/cpu.c +++ b/cpu/mpc512x/cpu.c @@ -131,22 +131,69 @@ void watchdog_reset (void) #endif #ifdef CONFIG_OF_LIBFDT -void ft_cpu_setup(void *blob, bd_t *bd) + +#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES +/* + * fdt setup for old device trees + * fix up + * cpu clocks + * soc clocks + * ethernet addresses + */ +static void old_ft_cpu_setup(void *blob, bd_t *bd) +{ + /* + * avoid fixing up by path because that + * produces scary error messages + */ + + /* + * old device trees have ethernet nodes with + * device_type = "network" + */ + do_fixup_by_prop(blob, "device_type", "network", 8, + "local-mac-address", bd->bi_enetaddr, 6, 0); + do_fixup_by_prop(blob, "device_type", "network", 8, + "address", bd->bi_enetaddr, 6, 0); + /* + * old device trees have soc nodes with + * device_type = "soc" + */ + do_fixup_by_prop_u32(blob, "device_type", "soc", 4, + "bus-frequency", bd->bi_ipsfreq, 0); +} +#endif + +static void ft_clock_setup(void *blob, bd_t *bd) { + int node; char *cpu_path = "/cpus/" OF_CPU; - char *eth_path = "/" OF_SOC "/ethernet@2800"; - char *eth_path_old = "/" OF_SOC_OLD "/ethernet@2800"; + const char *path = NULL; - do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); - do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); - do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipsfreq, 1); - do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0); + /* + * fixup cpu clocks using path + */ + do_fixup_by_path_u32(blob, cpu_path, + "timebase-frequency", OF_TBCLK, 1); + do_fixup_by_path_u32(blob, cpu_path, + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_path_u32(blob, cpu_path, + "clock-frequency", bd->bi_intfreq, 1); + /* + * fixup soc clocks using compatible + */ + do_fixup_by_compat_u32(blob, OF_SOC_COMPAT, + "bus-frequency", bd->bi_ipsfreq, 1); +} - /* this is so old kernels with old device trees will boot */ - do_fixup_by_path_u32(blob, "/" OF_SOC_OLD, "bus-frequency", bd->bi_ipsfreq, 0); - do_fixup_by_path(blob, eth_path_old, "local-mac-address", - bd->bi_enetaddr, 6, 0); - do_fixup_by_path(blob, eth_path_old, "address", bd->bi_enetaddr, 6, 0); +void ft_cpu_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES + old_ft_cpu_setup(blob, bd); +#endif + ft_clock_setup(blob, bd); +#ifdef CONFIG_HAS_ETH0 + fdt_fixup_ethernet(blob, bd); +#endif } #endif diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c new file mode 100644 index 000000000..01ab34aa3 --- /dev/null +++ b/cpu/mpc512x/iopin.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2008 + * Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com + * mpc512x I/O pin/pad initialization for the ADS5121 board + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/types.h> +#include <mpc512x.h> + +void iopin_initialize(iopin_t *ioregs_init, int len) +{ + short i, j, n, p; + u_long *reg; + immap_t *im = (immap_t *)CFG_IMMR; + + reg = (u_long *)&(im->io_ctrl.regs[0]); + + if (sizeof(ioregs_init) == 0) + return; + + for (i = 0; i < len; i++) { + for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); + p < ioregs_init[i].nr_pins; p++, j++) { + if (ioregs_init[i].bit_or) + reg[j] |= ioregs_init[i].val; + else + reg[j] = ioregs_init[i].val; + } + } + return; +} diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 12647ef98..479075ccb 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -158,13 +158,13 @@ static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; /* use CFG_MAX_FLASH_BANKS_DETECT if defined */ #ifdef CFG_MAX_FLASH_BANKS_DETECT -static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST; -flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */ +# define CFI_MAX_FLASH_BANKS CFG_MAX_FLASH_BANKS_DETECT #else -static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */ +# define CFI_MAX_FLASH_BANKS CFG_MAX_FLASH_BANKS #endif +flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ + /* * Check if chip width is defined. If not, start detecting with 8bit. */ @@ -1912,12 +1912,14 @@ unsigned long flash_init (void) char *s = getenv("unlock"); #endif +#define BANK_BASE(i) (((unsigned long [CFI_MAX_FLASH_BANKS])CFG_FLASH_BANKS_LIST)[i]) + /* Init: no FLASHes known */ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; - if (!flash_detect_legacy (bank_base[i], i)) - flash_get_size (bank_base[i], i); + if (!flash_detect_legacy (BANK_BASE(i), i)) + flash_get_size (BANK_BASE(i), i); size += flash_info[i].size; if (flash_info[i].flash_id == FLASH_UNKNOWN) { #ifndef CFG_FLASH_QUIET_TEST diff --git a/drivers/mtd/dataflash.c b/drivers/mtd/dataflash.c index 0ad48cdae..049da69fe 100644 --- a/drivers/mtd/dataflash.c +++ b/drivers/mtd/dataflash.c @@ -56,7 +56,7 @@ int AT91F_DataflashInit (void) switch (dfcode) { case AT45DB021: dataflash_info[i].Device.pages_number = 1024; - dataflash_info[i].Device.pages_size = 263; + dataflash_info[i].Device.pages_size = 264; dataflash_info[i].Device.page_offset = 9; dataflash_info[i].Device.byte_mask = 0x300; dataflash_info[i].Device.cs = cs[i].cs; @@ -65,6 +65,19 @@ int AT91F_DataflashInit (void) dataflash_info[i].id = dfcode; found[i] += dfcode;; break; + + case AT45DB081: + dataflash_info[i].Device.pages_number = 4096; + dataflash_info[i].Device.pages_size = 264; + dataflash_info[i].Device.page_offset = 9; + dataflash_info[i].Device.byte_mask = 0x300; + dataflash_info[i].Device.cs = cs[i].cs; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i].addr; + dataflash_info[i].id = dfcode; + found[i] += dfcode;; + break; + case AT45DB161: dataflash_info[i].Device.pages_number = 4096; dataflash_info[i].Device.pages_size = 528; diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index d2c430b8a..ba89247e4 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -29,6 +29,7 @@ #include "uccf.h" #include "uec.h" #include "uec_phy.h" +#include "miiphy.h" #if defined(CONFIG_QE) @@ -125,6 +126,13 @@ static uec_info_t eth4_uec_info = { }; #endif +#define MAXCONTROLLERS (4) + +static struct eth_device *devlist[MAXCONTROLLERS]; + +u16 phy_read (struct uec_mii_info *mii_info, u16 regnum); +void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val); + static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode) { uec_t *uec_regs; @@ -629,6 +637,39 @@ static void phy_change(struct eth_device *dev) adjust_link(dev); } +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ + && !defined(BITBANGMII) + +/* + * Read a MII PHY register. + * + * Returns: + * 0 on success + */ +static int uec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + *value = uec_read_phy_reg(devlist[0], addr, reg); + + return 0; +} + +/* + * Write a MII PHY register. + * + * Returns: + * 0 on success + */ +static int uec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + uec_write_phy_reg(devlist[0], addr, reg, value); + + return 0; +} + +#endif + static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr) { uec_t *uec_regs; @@ -1334,6 +1375,8 @@ int uec_initialize(int index) return -EINVAL; } + devlist[index] = dev; + uec->uec_info = uec_info; sprintf(dev->name, "FSL UEC%d", index); @@ -1356,6 +1399,13 @@ int uec_initialize(int index) return err; } +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ + && !defined(BITBANGMII) + miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write); +#endif + return 1; } + + #endif /* CONFIG_QE */ diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile index 252b00e65..2bdbb59cd 100644 --- a/drivers/usb/Makefile +++ b/drivers/usb/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libusb.a COBJS-y += isp116x-hcd.o COBJS-y += sl811_usb.o COBJS-y += usb_ohci.o +COBJS-y += r8a66597-hcd.o COBJS-y += usbdcore.o COBJS-y += usbdcore_ep0.o COBJS-y += usbdcore_mpc8xx.o diff --git a/drivers/usb/r8a66597-hcd.c b/drivers/usb/r8a66597-hcd.c new file mode 100644 index 000000000..3eb4cb03f --- /dev/null +++ b/drivers/usb/r8a66597-hcd.c @@ -0,0 +1,924 @@ +/* + * R8A66597 HCD (Host Controller Driver) for u-boot + * + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include <common.h> +#include <usb.h> +#include <asm/io.h> + +#include "r8a66597.h" + +#if defined(CONFIG_USB_R8A66597_HCD) + +#ifdef R8A66597_DEBUG +#define R8A66597_DPRINT printf +#else +#define R8A66597_DPRINT(...) +#endif + +static const char hcd_name[] = "r8a66597_hcd"; +static unsigned short clock = CONFIG_R8A66597_XTAL; +static unsigned short vif = CONFIG_R8A66597_LDRV; +static unsigned short endian = CONFIG_R8A66597_ENDIAN; +static struct r8a66597 gr8a66597; + +static void set_devadd_reg(struct r8a66597 *r8a66597, u8 r8a66597_address, + u16 usbspd, u8 upphub, u8 hubport, int port) +{ + u16 val; + unsigned long devadd_reg = get_devadd_addr(r8a66597_address); + + val = (upphub << 11) | (hubport << 8) | (usbspd << 6) | (port & 0x0001); + r8a66597_write(r8a66597, val, devadd_reg); +} + +static int r8a66597_clock_enable(struct r8a66597 *r8a66597) +{ + u16 tmp; + int i = 0; + +#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) + do { + r8a66597_write(r8a66597, SCKE, SYSCFG0); + tmp = r8a66597_read(r8a66597, SYSCFG0); + if (i++ > 1000) { + printf("register access fail.\n"); + return -1; + } + } while ((tmp & SCKE) != SCKE); + r8a66597_write(r8a66597, 0x04, 0x02); +#else + do { + r8a66597_write(r8a66597, USBE, SYSCFG0); + tmp = r8a66597_read(r8a66597, SYSCFG0); + if (i++ > 1000) { + printf("register access fail.\n"); + return -1; + } + } while ((tmp & USBE) != USBE); + r8a66597_bclr(r8a66597, USBE, SYSCFG0); + r8a66597_mdfy(r8a66597, clock, XTAL, SYSCFG0); + + i = 0; + r8a66597_bset(r8a66597, XCKE, SYSCFG0); + do { + udelay(1000); + tmp = r8a66597_read(r8a66597, SYSCFG0); + if (i++ > 500) { + printf("register access fail.\n"); + return -1; + } + } while ((tmp & SCKE) != SCKE); +#endif /* #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) */ + + return 0; +} + +static void r8a66597_clock_disable(struct r8a66597 *r8a66597) +{ + r8a66597_bclr(r8a66597, SCKE, SYSCFG0); + udelay(1); +#if !defined(CONFIG_SUPERH_ON_CHIP_R8A66597) + r8a66597_bclr(r8a66597, PLLC, SYSCFG0); + r8a66597_bclr(r8a66597, XCKE, SYSCFG0); + r8a66597_bclr(r8a66597, USBE, SYSCFG0); +#endif +} + +static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port) +{ + u16 val; + + val = port ? DRPD : DCFM | DRPD; + r8a66597_bset(r8a66597, val, get_syscfg_reg(port)); + r8a66597_bset(r8a66597, HSE, get_syscfg_reg(port)); + + r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR, get_dmacfg_reg(port)); +} + +static void r8a66597_disable_port(struct r8a66597 *r8a66597, int port) +{ + u16 val, tmp; + + r8a66597_write(r8a66597, 0, get_intenb_reg(port)); + r8a66597_write(r8a66597, 0, get_intsts_reg(port)); + + r8a66597_port_power(r8a66597, port, 0); + + do { + tmp = r8a66597_read(r8a66597, SOFCFG) & EDGESTS; + udelay(640); + } while (tmp == EDGESTS); + + val = port ? DRPD : DCFM | DRPD; + r8a66597_bclr(r8a66597, val, get_syscfg_reg(port)); + r8a66597_bclr(r8a66597, HSE, get_syscfg_reg(port)); +} + +static int enable_controller(struct r8a66597 *r8a66597) +{ + int ret, port; + + ret = r8a66597_clock_enable(r8a66597); + if (ret < 0) + return ret; + + r8a66597_bset(r8a66597, vif & LDRV, PINCFG); + r8a66597_bset(r8a66597, USBE, SYSCFG0); + + r8a66597_bset(r8a66597, INTL, SOFCFG); + r8a66597_write(r8a66597, 0, INTENB0); + r8a66597_write(r8a66597, 0, INTENB1); + r8a66597_write(r8a66597, 0, INTENB2); + + r8a66597_bset(r8a66597, endian & BIGEND, CFIFOSEL); + r8a66597_bset(r8a66597, endian & BIGEND, D0FIFOSEL); + r8a66597_bset(r8a66597, endian & BIGEND, D1FIFOSEL); + r8a66597_bset(r8a66597, TRNENSEL, SOFCFG); + + for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) + r8a66597_enable_port(r8a66597, port); + + return 0; +} + +static void disable_controller(struct r8a66597 *r8a66597) +{ + int i; + + if (!(r8a66597_read(r8a66597, SYSCFG0) & USBE)) + return; + + r8a66597_write(r8a66597, 0, INTENB0); + r8a66597_write(r8a66597, 0, INTSTS0); + + r8a66597_write(r8a66597, 0, D0FIFOSEL); + r8a66597_write(r8a66597, 0, D1FIFOSEL); + r8a66597_write(r8a66597, 0, DCPCFG); + r8a66597_write(r8a66597, 0x40, DCPMAXP); + r8a66597_write(r8a66597, 0, DCPCTR); + + for (i = 0; i <= 10; i++) + r8a66597_write(r8a66597, 0, get_devadd_addr(i)); + for (i = 1; i <= 5; i++) { + r8a66597_write(r8a66597, 0, get_pipetre_addr(i)); + r8a66597_write(r8a66597, 0, get_pipetrn_addr(i)); + } + for (i = 1; i < R8A66597_MAX_NUM_PIPE; i++) { + r8a66597_write(r8a66597, 0, get_pipectr_addr(i)); + r8a66597_write(r8a66597, i, PIPESEL); + r8a66597_write(r8a66597, 0, PIPECFG); + r8a66597_write(r8a66597, 0, PIPEBUF); + r8a66597_write(r8a66597, 0, PIPEMAXP); + r8a66597_write(r8a66597, 0, PIPEPERI); + } + + for (i = 0; i < R8A66597_MAX_ROOT_HUB; i++) + r8a66597_disable_port(r8a66597, i); + + r8a66597_clock_disable(r8a66597); +} + +static void r8a66597_reg_wait(struct r8a66597 *r8a66597, unsigned long reg, + u16 mask, u16 loop) +{ + u16 tmp; + int i = 0; + + do { + tmp = r8a66597_read(r8a66597, reg); + if (i++ > 1000000) { + printf("register%lx, loop %x is timeout\n", reg, loop); + break; + } + } while ((tmp & mask) != loop); +} + +static void pipe_buffer_setting(struct r8a66597 *r8a66597, + struct usb_device *dev, unsigned long pipe) +{ + u16 val = 0; + u16 pipenum, bufnum, maxpacket; + + if (usb_pipein(pipe)) { + pipenum = BULK_IN_PIPENUM; + bufnum = BULK_IN_BUFNUM; + maxpacket = dev->epmaxpacketin[usb_pipeendpoint(pipe)]; + } else { + pipenum = BULK_OUT_PIPENUM; + bufnum = BULK_OUT_BUFNUM; + maxpacket = dev->epmaxpacketout[usb_pipeendpoint(pipe)]; + } + + if (r8a66597->pipe_config & (1 << pipenum)) + return; + r8a66597->pipe_config |= (1 << pipenum); + + r8a66597_bset(r8a66597, ACLRM, get_pipectr_addr(pipenum)); + r8a66597_bclr(r8a66597, ACLRM, get_pipectr_addr(pipenum)); + r8a66597_write(r8a66597, pipenum, PIPESEL); + + /* FIXME: This driver support bulk transfer only. */ + if (!usb_pipein(pipe)) + val |= R8A66597_DIR; + else + val |= R8A66597_SHTNAK; + val |= R8A66597_BULK | R8A66597_DBLB | usb_pipeendpoint(pipe); + r8a66597_write(r8a66597, val, PIPECFG); + + r8a66597_write(r8a66597, (8 << 10) | bufnum, PIPEBUF); + r8a66597_write(r8a66597, make_devsel(usb_pipedevice(pipe)) | + maxpacket, PIPEMAXP); + r8a66597_write(r8a66597, 0, PIPEPERI); + r8a66597_write(r8a66597, SQCLR, get_pipectr_addr(pipenum)); +} + +static int send_setup_packet(struct r8a66597 *r8a66597, struct usb_device *dev, + struct devrequest *setup) +{ + int i; + unsigned short *p = (unsigned short *)setup; + unsigned long setup_addr = USBREQ; + u16 intsts1; + int timeout = 3000; + u16 devsel = setup->request == USB_REQ_SET_ADDRESS ? 0 : dev->devnum; + + r8a66597_write(r8a66597, make_devsel(devsel) | + (8 << dev->maxpacketsize), DCPMAXP); + r8a66597_write(r8a66597, ~(SIGN | SACK), INTSTS1); + + for (i = 0; i < 4; i++) { + r8a66597_write(r8a66597, le16_to_cpu(p[i]), setup_addr); + setup_addr += 2; + } + r8a66597_write(r8a66597, ~0x0001, BRDYSTS); + r8a66597_write(r8a66597, SUREQ, DCPCTR); + + while (1) { + intsts1 = r8a66597_read(r8a66597, INTSTS1); + if (intsts1 & SACK) + break; + if (intsts1 & SIGN) { + printf("setup packet send error\n"); + return -1; + } + if (timeout-- < 0) { + printf("setup packet timeout\n"); + return -1; + } + udelay(500); + } + + return 0; +} + +static int send_bulk_packet(struct r8a66597 *r8a66597, struct usb_device *dev, + unsigned long pipe, void *buffer, int transfer_len) +{ + u16 tmp, bufsize; + u16 *buf; + size_t size; + + R8A66597_DPRINT("%s\n", __func__); + + r8a66597_mdfy(r8a66597, MBW | BULK_OUT_PIPENUM, + MBW | CURPIPE, CFIFOSEL); + r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, BULK_OUT_PIPENUM); + tmp = r8a66597_read(r8a66597, CFIFOCTR); + if ((tmp & FRDY) == 0) { + printf("%s FRDY is not set (%x)\n", __func__, tmp); + return -1; + } + + /* prepare parameters */ + bufsize = dev->epmaxpacketout[usb_pipeendpoint(pipe)]; + buf = (u16 *)(buffer + dev->act_len); + size = min((int)bufsize, transfer_len - dev->act_len); + + /* write fifo */ + r8a66597_write(r8a66597, ~(1 << BULK_OUT_PIPENUM), BEMPSTS); + if (buffer) { + r8a66597_write_fifo(r8a66597, CFIFO, buf, size); + r8a66597_write(r8a66597, BVAL, CFIFOCTR); + } + + /* update parameters */ + dev->act_len += size; + + r8a66597_mdfy(r8a66597, PID_BUF, PID, + get_pipectr_addr(BULK_OUT_PIPENUM)); + + while (!(r8a66597_read(r8a66597, BEMPSTS) & (1 << BULK_OUT_PIPENUM))) + if (ctrlc()) + return -1; + r8a66597_write(r8a66597, ~(1 << BULK_OUT_PIPENUM), BEMPSTS); + + if (dev->act_len >= transfer_len) + r8a66597_mdfy(r8a66597, PID_NAK, PID, + get_pipectr_addr(BULK_OUT_PIPENUM)); + + return 0; +} + +static int receive_bulk_packet(struct r8a66597 *r8a66597, + struct usb_device *dev, + unsigned long pipe, + void *buffer, int transfer_len) +{ + u16 tmp; + u16 *buf; + const u16 pipenum = BULK_IN_PIPENUM; + int rcv_len; + int maxpacket = dev->epmaxpacketin[usb_pipeendpoint(pipe)]; + + R8A66597_DPRINT("%s\n", __func__); + + /* prepare */ + if (dev->act_len == 0) { + r8a66597_mdfy(r8a66597, PID_NAK, PID, + get_pipectr_addr(pipenum)); + r8a66597_write(r8a66597, ~(1 << pipenum), BRDYSTS); + + r8a66597_write(r8a66597, TRCLR, get_pipetre_addr(pipenum)); + r8a66597_write(r8a66597, + (transfer_len + maxpacket - 1) / maxpacket, + get_pipetrn_addr(pipenum)); + r8a66597_bset(r8a66597, TRENB, get_pipetre_addr(pipenum)); + + r8a66597_mdfy(r8a66597, PID_BUF, PID, + get_pipectr_addr(pipenum)); + } + + r8a66597_mdfy(r8a66597, MBW | pipenum, MBW | CURPIPE, CFIFOSEL); + r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, pipenum); + + while (!(r8a66597_read(r8a66597, BRDYSTS) & (1 << pipenum))) + if (ctrlc()) + return -1; + r8a66597_write(r8a66597, ~(1 << pipenum), BRDYSTS); + + tmp = r8a66597_read(r8a66597, CFIFOCTR); + if ((tmp & FRDY) == 0) { + printf("%s FRDY is not set. (%x)\n", __func__, tmp); + return -1; + } + + buf = (u16 *)(buffer + dev->act_len); + rcv_len = tmp & DTLN; + dev->act_len += rcv_len; + + if (buffer) { + if (rcv_len == 0) + r8a66597_write(r8a66597, BCLR, CFIFOCTR); + else + r8a66597_read_fifo(r8a66597, CFIFO, buf, rcv_len); + } + + return 0; +} + +static int receive_control_packet(struct r8a66597 *r8a66597, + struct usb_device *dev, + void *buffer, int transfer_len) +{ + u16 tmp; + int rcv_len; + + /* FIXME: limit transfer size : 64byte or less */ + + r8a66597_bclr(r8a66597, R8A66597_DIR, DCPCFG); + r8a66597_mdfy(r8a66597, 0, ISEL | CURPIPE, CFIFOSEL); + r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0); + r8a66597_bset(r8a66597, SQSET, DCPCTR); + r8a66597_write(r8a66597, BCLR, CFIFOCTR); + r8a66597_mdfy(r8a66597, PID_BUF, PID, DCPCTR); + + while (!(r8a66597_read(r8a66597, BRDYSTS) & 0x0001)) + if (ctrlc()) + return -1; + r8a66597_write(r8a66597, ~0x0001, BRDYSTS); + + r8a66597_mdfy(r8a66597, MBW, MBW | CURPIPE, CFIFOSEL); + r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0); + + tmp = r8a66597_read(r8a66597, CFIFOCTR); + if ((tmp & FRDY) == 0) { + printf("%s FRDY is not set. (%x)\n", __func__, tmp); + return -1; + } + + rcv_len = tmp & DTLN; + dev->act_len += rcv_len; + + r8a66597_mdfy(r8a66597, PID_NAK, PID, DCPCTR); + + if (buffer) { + if (rcv_len == 0) + r8a66597_write(r8a66597, BCLR, DCPCTR); + else + r8a66597_read_fifo(r8a66597, CFIFO, buffer, rcv_len); + } + + return 0; +} + +static int send_status_packet(struct r8a66597 *r8a66597, + unsigned long pipe) +{ + r8a66597_bset(r8a66597, SQSET, DCPCTR); + r8a66597_mdfy(r8a66597, PID_NAK, PID, DCPCTR); + + if (usb_pipein(pipe)) { + r8a66597_bset(r8a66597, R8A66597_DIR, DCPCFG); + r8a66597_mdfy(r8a66597, ISEL, ISEL | CURPIPE, CFIFOSEL); + r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0); + r8a66597_write(r8a66597, ~BEMP0, BEMPSTS); + r8a66597_write(r8a66597, BCLR | BVAL, CFIFOCTR); + } else { + r8a66597_bclr(r8a66597, R8A66597_DIR, DCPCFG); + r8a66597_mdfy(r8a66597, 0, ISEL | CURPIPE, CFIFOSEL); + r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0); + r8a66597_write(r8a66597, BCLR, CFIFOCTR); + } + r8a66597_mdfy(r8a66597, PID_BUF, PID, DCPCTR); + + while (!(r8a66597_read(r8a66597, BEMPSTS) & 0x0001)) + if (ctrlc()) + return -1; + + return 0; +} + +static void r8a66597_check_syssts(struct r8a66597 *r8a66597, int port) +{ + int count = R8A66597_MAX_SAMPLING; + unsigned short syssts, old_syssts; + + R8A66597_DPRINT("%s\n", __func__); + + old_syssts = r8a66597_read(r8a66597, get_syssts_reg(port) & LNST); + while (count > 0) { + wait_ms(R8A66597_RH_POLL_TIME); + + syssts = r8a66597_read(r8a66597, get_syssts_reg(port) & LNST); + if (syssts == old_syssts) { + count--; + } else { + count = R8A66597_MAX_SAMPLING; + old_syssts = syssts; + } + } +} + +static void r8a66597_bus_reset(struct r8a66597 *r8a66597, int port) +{ + wait_ms(10); + r8a66597_mdfy(r8a66597, USBRST, USBRST | UACT, get_dvstctr_reg(port)); + wait_ms(50); + r8a66597_mdfy(r8a66597, UACT, USBRST | UACT, get_dvstctr_reg(port)); + wait_ms(50); +} + +static int check_usb_device_connecting(struct r8a66597 *r8a66597) +{ + int timeout = 10000; /* 100usec * 10000 = 1sec */ + int i; + + for (i = 0; i < 5; i++) { + /* check a usb cable connect */ + while (!(r8a66597_read(r8a66597, INTSTS1) & ATTCH)) { + if (timeout-- < 0) { + printf("%s timeout.\n", __func__); + return -1; + } + udelay(100); + } + + /* check a data line */ + r8a66597_check_syssts(r8a66597, 0); + + r8a66597_bus_reset(r8a66597, 0); + r8a66597->speed = get_rh_usb_speed(r8a66597, 0); + + if (!(r8a66597_read(r8a66597, INTSTS1) & DTCH)) { + r8a66597->port_change = USB_PORT_STAT_C_CONNECTION; + r8a66597->port_status = USB_PORT_STAT_CONNECTION | + USB_PORT_STAT_ENABLE; + return 0; /* success */ + } + + R8A66597_DPRINT("USB device has detached. retry = %d\n", i); + r8a66597_write(r8a66597, ~DTCH, INTSTS1); + } + + return -1; /* fail */ +} + +/* based on usb_ohci.c */ +#define min_t(type, x, y) \ + ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) +/*-------------------------------------------------------------------------* + * Virtual Root Hub + *-------------------------------------------------------------------------*/ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = +{ + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; */ + + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = +{ + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = +{ + 34, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '8', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'A', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '6', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '6', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '5', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '9', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '7', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +static int r8a66597_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, struct devrequest *cmd) +{ + struct r8a66597 *r8a66597 = &gr8a66597; + int leni = transfer_len; + int len = 0; + int stat = 0; + __u16 bmRType_bReq; + __u16 wValue; + __u16 wIndex; + __u16 wLength; + unsigned char data[32]; + + R8A66597_DPRINT("%s\n", __func__); + + if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { + printf("Root-Hub submit IRQ: NOT implemented"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = cpu_to_le16 (cmd->value); + wIndex = cpu_to_le16 (cmd->index); + wLength = cpu_to_le16 (cmd->length); + + switch (bmRType_bReq) { + case RH_GET_STATUS: + *(__u16 *)buffer = cpu_to_le16(1); + len = 2; + break; + case RH_GET_STATUS | RH_INTERFACE: + *(__u16 *)buffer = cpu_to_le16(0); + len = 2; + break; + case RH_GET_STATUS | RH_ENDPOINT: + *(__u16 *)buffer = cpu_to_le16(0); + len = 2; + break; + case RH_GET_STATUS | RH_CLASS: + *(__u32 *)buffer = cpu_to_le32(0); + len = 4; + break; + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + *(__u32 *)buffer = cpu_to_le32(r8a66597->port_status | + (r8a66597->port_change << 16)); + len = 4; + break; + case RH_CLEAR_FEATURE | RH_ENDPOINT: + case RH_CLEAR_FEATURE | RH_CLASS: + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case RH_C_PORT_CONNECTION: + r8a66597->port_change &= ~USB_PORT_STAT_C_CONNECTION; + break; + } + break; + + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_SUSPEND): + break; + case (RH_PORT_RESET): + r8a66597_bus_reset(r8a66597, 0); + break; + case (RH_PORT_POWER): + break; + case (RH_PORT_ENABLE): + break; + } + break; + case RH_SET_ADDRESS: + gr8a66597.rh_devnum = wValue; + break; + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case (0x01): /* device descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof(root_hub_dev_des), + wLength)); + memcpy(buffer, root_hub_dev_des, len); + break; + case (0x02): /* configuration descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof(root_hub_config_des), + wLength)); + memcpy(buffer, root_hub_config_des, len); + break; + case (0x03): /* string descriptors */ + if (wValue == 0x0300) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof(root_hub_str_index0), + wLength)); + memcpy(buffer, root_hub_str_index0, len); + } + if (wValue == 0x0301) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof(root_hub_str_index1), + wLength)); + memcpy(buffer, root_hub_str_index1, len); + } + break; + default: + stat = USB_ST_STALLED; + } + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + { + __u32 temp = 0x00000001; + + data[0] = 9; /* min length; */ + data[1] = 0x29; + data[2] = temp & RH_A_NDP; + data[3] = 0; + if (temp & RH_A_PSM) + data[3] |= 0x1; + if (temp & RH_A_NOCP) + data[3] |= 0x10; + else if (temp & RH_A_OCPM) + data[3] |= 0x8; + + /* corresponds to data[4-7] */ + data[5] = (temp & RH_A_POTPGT) >> 24; + data[7] = temp & RH_B_DR; + if (data[2] < 7) { + data[8] = 0xff; + } else { + data[0] += 2; + data[8] = (temp & RH_B_DR) >> 8; + data[10] = data[9] = 0xff; + } + + len = min_t(unsigned int, leni, + min_t(unsigned int, data[0], wLength)); + memcpy(buffer, data, len); + break; + } + + case RH_GET_CONFIGURATION: + *(__u8 *) buffer = 0x01; + len = 1; + break; + case RH_SET_CONFIGURATION: + break; + default: + dbg("unsupported root hub command"); + stat = USB_ST_STALLED; + } + + wait_ms(1); + + len = min_t(int, len, leni); + + dev->act_len = len; + dev->status = stat; + + return stat; +} + +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len) +{ + struct r8a66597 *r8a66597 = &gr8a66597; + int ret = 0; + + R8A66597_DPRINT("%s\n", __func__); + R8A66597_DPRINT("pipe = %08x, buffer = %p, len = %d, devnum = %d\n", + pipe, buffer, transfer_len, dev->devnum); + + set_devadd_reg(r8a66597, dev->devnum, r8a66597->speed, 0, 0, 0); + + pipe_buffer_setting(r8a66597, dev, pipe); + + dev->act_len = 0; + while (dev->act_len < transfer_len && ret == 0) { + if (ctrlc()) + return -1; + + if (usb_pipein(pipe)) + ret = receive_bulk_packet(r8a66597, dev, pipe, buffer, + transfer_len); + else + ret = send_bulk_packet(r8a66597, dev, pipe, buffer, + transfer_len); + } + + if (ret == 0) + dev->status = 0; + + return ret; +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, struct devrequest *setup) +{ + struct r8a66597 *r8a66597 = &gr8a66597; + u16 r8a66597_address = setup->request == USB_REQ_SET_ADDRESS ? + 0 : dev->devnum; + + R8A66597_DPRINT("%s\n", __func__); + if (usb_pipedevice(pipe) == r8a66597->rh_devnum) + return r8a66597_submit_rh_msg(dev, pipe, buffer, transfer_len, + setup); + + R8A66597_DPRINT("%s: setup\n", __func__); + set_devadd_reg(r8a66597, r8a66597_address, r8a66597->speed, 0, 0, 0); + + if (send_setup_packet(r8a66597, dev, setup) < 0) { + printf("setup packet send error\n"); + return -1; + } + + if (usb_pipein(pipe)) + if (receive_control_packet(r8a66597, dev, buffer, + transfer_len) < 0) + return -1; + + if (send_status_packet(r8a66597, pipe) < 0) + return -1; + + dev->status = 0; + + return 0; +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval) +{ + /* no implement */ + R8A66597_DPRINT("%s\n", __func__); + return 0; +} + +void usb_event_poll(void) +{ + /* no implement */ + R8A66597_DPRINT("%s\n", __func__); +} + +int usb_lowlevel_init(void) +{ + struct r8a66597 *r8a66597 = &gr8a66597; + + R8A66597_DPRINT("%s\n", __func__); + + memset(r8a66597, 0, sizeof(r8a66597)); + r8a66597->reg = CONFIG_R8A66597_BASE_ADDR; + + disable_controller(r8a66597); + wait_ms(100); + + enable_controller(r8a66597); + r8a66597_port_power(r8a66597, 0 , 1); + + /* check usb device */ + check_usb_device_connecting(r8a66597); + + wait_ms(50); + + return 0; +} + +int usb_lowlevel_stop(void) +{ + disable_controller(&gr8a66597); + + return 0; +} + +#endif /* CONFIG_USB_R8A66597_HCD */ + diff --git a/drivers/usb/r8a66597.h b/drivers/usb/r8a66597.h new file mode 100644 index 000000000..54a1f26ae --- /dev/null +++ b/drivers/usb/r8a66597.h @@ -0,0 +1,663 @@ +/* + * R8A66597 HCD (Host Controller Driver) for u-boot + * + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#ifndef __R8A66597_H__ +#define __R8A66597_H__ + +#define SYSCFG0 0x00 +#define SYSCFG1 0x02 +#define SYSSTS0 0x04 +#define SYSSTS1 0x06 +#define DVSTCTR0 0x08 +#define DVSTCTR1 0x0A +#define TESTMODE 0x0C +#define PINCFG 0x0E +#define DMA0CFG 0x10 +#define DMA1CFG 0x12 +#define CFIFO 0x14 +#define D0FIFO 0x18 +#define D1FIFO 0x1C +#define CFIFOSEL 0x20 +#define CFIFOCTR 0x22 +#define CFIFOSIE 0x24 +#define D0FIFOSEL 0x28 +#define D0FIFOCTR 0x2A +#define D1FIFOSEL 0x2C +#define D1FIFOCTR 0x2E +#define INTENB0 0x30 +#define INTENB1 0x32 +#define INTENB2 0x34 +#define BRDYENB 0x36 +#define NRDYENB 0x38 +#define BEMPENB 0x3A +#define SOFCFG 0x3C +#define INTSTS0 0x40 +#define INTSTS1 0x42 +#define INTSTS2 0x44 +#define BRDYSTS 0x46 +#define NRDYSTS 0x48 +#define BEMPSTS 0x4A +#define FRMNUM 0x4C +#define UFRMNUM 0x4E +#define USBADDR 0x50 +#define USBREQ 0x54 +#define USBVAL 0x56 +#define USBINDX 0x58 +#define USBLENG 0x5A +#define DCPCFG 0x5C +#define DCPMAXP 0x5E +#define DCPCTR 0x60 +#define PIPESEL 0x64 +#define PIPECFG 0x68 +#define PIPEBUF 0x6A +#define PIPEMAXP 0x6C +#define PIPEPERI 0x6E +#define PIPE1CTR 0x70 +#define PIPE2CTR 0x72 +#define PIPE3CTR 0x74 +#define PIPE4CTR 0x76 +#define PIPE5CTR 0x78 +#define PIPE6CTR 0x7A +#define PIPE7CTR 0x7C +#define PIPE8CTR 0x7E +#define PIPE9CTR 0x80 +#define PIPE1TRE 0x90 +#define PIPE1TRN 0x92 +#define PIPE2TRE 0x94 +#define PIPE2TRN 0x96 +#define PIPE3TRE 0x98 +#define PIPE3TRN 0x9A +#define PIPE4TRE 0x9C +#define PIPE4TRN 0x9E +#define PIPE5TRE 0xA0 +#define PIPE5TRN 0xA2 +#define DEVADD0 0xD0 +#define DEVADD1 0xD2 +#define DEVADD2 0xD4 +#define DEVADD3 0xD6 +#define DEVADD4 0xD8 +#define DEVADD5 0xDA +#define DEVADD6 0xDC +#define DEVADD7 0xDE +#define DEVADD8 0xE0 +#define DEVADD9 0xE2 +#define DEVADDA 0xE4 + +/* System Configuration Control Register */ +#define XTAL 0xC000 /* b15-14: Crystal selection */ +#define XTAL48 0x8000 /* 48MHz */ +#define XTAL24 0x4000 /* 24MHz */ +#define XTAL12 0x0000 /* 12MHz */ +#define XCKE 0x2000 /* b13: External clock enable */ +#define PLLC 0x0800 /* b11: PLL control */ +#define SCKE 0x0400 /* b10: USB clock enable */ +#define PCSDIS 0x0200 /* b9: not CS wakeup */ +#define LPSME 0x0100 /* b8: Low power sleep mode */ +#define HSE 0x0080 /* b7: Hi-speed enable */ +#define DCFM 0x0040 /* b6: Controller function select */ +#define DRPD 0x0020 /* b5: D+/- pull down control */ +#define DPRPU 0x0010 /* b4: D+ pull up control */ +#define USBE 0x0001 /* b0: USB module operation enable */ + +/* System Configuration Status Register */ +#define OVCBIT 0x8000 /* b15-14: Over-current bit */ +#define OVCMON 0xC000 /* b15-14: Over-current monitor */ +#define SOFEA 0x0020 /* b5: SOF monitor */ +#define IDMON 0x0004 /* b3: ID-pin monitor */ +#define LNST 0x0003 /* b1-0: D+, D- line status */ +#define SE1 0x0003 /* SE1 */ +#define FS_KSTS 0x0002 /* Full-Speed K State */ +#define FS_JSTS 0x0001 /* Full-Speed J State */ +#define LS_JSTS 0x0002 /* Low-Speed J State */ +#define LS_KSTS 0x0001 /* Low-Speed K State */ +#define SE0 0x0000 /* SE0 */ + +/* Device State Control Register */ +#define EXTLP0 0x0400 /* b10: External port */ +#define VBOUT 0x0200 /* b9: VBUS output */ +#define WKUP 0x0100 /* b8: Remote wakeup */ +#define RWUPE 0x0080 /* b7: Remote wakeup sense */ +#define USBRST 0x0040 /* b6: USB reset enable */ +#define RESUME 0x0020 /* b5: Resume enable */ +#define UACT 0x0010 /* b4: USB bus enable */ +#define RHST 0x0007 /* b1-0: Reset handshake status */ +#define HSPROC 0x0004 /* HS handshake is processing */ +#define HSMODE 0x0003 /* Hi-Speed mode */ +#define FSMODE 0x0002 /* Full-Speed mode */ +#define LSMODE 0x0001 /* Low-Speed mode */ +#define UNDECID 0x0000 /* Undecided */ + +/* Test Mode Register */ +#define UTST 0x000F /* b3-0: Test select */ +#define H_TST_PACKET 0x000C /* HOST TEST Packet */ +#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */ +#define H_TST_K 0x000A /* HOST TEST K */ +#define H_TST_J 0x0009 /* HOST TEST J */ +#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */ +#define P_TST_PACKET 0x0004 /* PERI TEST Packet */ +#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */ +#define P_TST_K 0x0002 /* PERI TEST K */ +#define P_TST_J 0x0001 /* PERI TEST J */ +#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */ + +/* Data Pin Configuration Register */ +#define LDRV 0x8000 /* b15: Drive Current Adjust */ +#define VIF1 0x0000 /* VIF = 1.8V */ +#define VIF3 0x8000 /* VIF = 3.3V */ +#define INTA 0x0001 /* b1: USB INT-pin active */ + +/* DMAx Pin Configuration Register */ +#define DREQA 0x4000 /* b14: Dreq active select */ +#define BURST 0x2000 /* b13: Burst mode */ +#define DACKA 0x0400 /* b10: Dack active select */ +#define DFORM 0x0380 /* b9-7: DMA mode select */ +#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */ +#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */ +#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */ +#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */ +#define DENDA 0x0040 /* b6: Dend active select */ +#define PKTM 0x0020 /* b5: Packet mode */ +#define DENDE 0x0010 /* b4: Dend enable */ +#define OBUS 0x0004 /* b2: OUTbus mode */ + +/* CFIFO/DxFIFO Port Select Register */ +#define RCNT 0x8000 /* b15: Read count mode */ +#define REW 0x4000 /* b14: Buffer rewind */ +#define DCLRM 0x2000 /* b13: DMA buffer clear mode */ +#define DREQE 0x1000 /* b12: DREQ output enable */ +#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) +#define MBW 0x0800 +#else +#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */ +#endif +#define MBW_8 0x0000 /* 8bit */ +#define MBW_16 0x0400 /* 16bit */ +#define BIGEND 0x0100 /* b8: Big endian mode */ +#define BYTE_LITTLE 0x0000 /* little dendian */ +#define BYTE_BIG 0x0100 /* big endifan */ +#define ISEL 0x0020 /* b5: DCP FIFO port direction select */ +#define CURPIPE 0x000F /* b2-0: PIPE select */ + +/* CFIFO/DxFIFO Port Control Register */ +#define BVAL 0x8000 /* b15: Buffer valid flag */ +#define BCLR 0x4000 /* b14: Buffer clear */ +#define FRDY 0x2000 /* b13: FIFO ready */ +#define DTLN 0x0FFF /* b11-0: FIFO received data length */ + +/* Interrupt Enable Register 0 */ +#define VBSE 0x8000 /* b15: VBUS interrupt */ +#define RSME 0x4000 /* b14: Resume interrupt */ +#define SOFE 0x2000 /* b13: Frame update interrupt */ +#define DVSE 0x1000 /* b12: Device state transition interrupt */ +#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */ +#define BEMPE 0x0400 /* b10: Buffer empty interrupt */ +#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */ +#define BRDYE 0x0100 /* b8: Buffer ready interrupt */ + +/* Interrupt Enable Register 1 */ +#define OVRCRE 0x8000 /* b15: Over-current interrupt */ +#define BCHGE 0x4000 /* b14: USB us chenge interrupt */ +#define DTCHE 0x1000 /* b12: Detach sense interrupt */ +#define ATTCHE 0x0800 /* b11: Attach sense interrupt */ +#define EOFERRE 0x0040 /* b6: EOF error interrupt */ +#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */ +#define SACKE 0x0010 /* b4: SETUP ACK interrupt */ + +/* BRDY Interrupt Enable/Status Register */ +#define BRDY9 0x0200 /* b9: PIPE9 */ +#define BRDY8 0x0100 /* b8: PIPE8 */ +#define BRDY7 0x0080 /* b7: PIPE7 */ +#define BRDY6 0x0040 /* b6: PIPE6 */ +#define BRDY5 0x0020 /* b5: PIPE5 */ +#define BRDY4 0x0010 /* b4: PIPE4 */ +#define BRDY3 0x0008 /* b3: PIPE3 */ +#define BRDY2 0x0004 /* b2: PIPE2 */ +#define BRDY1 0x0002 /* b1: PIPE1 */ +#define BRDY0 0x0001 /* b1: PIPE0 */ + +/* NRDY Interrupt Enable/Status Register */ +#define NRDY9 0x0200 /* b9: PIPE9 */ +#define NRDY8 0x0100 /* b8: PIPE8 */ +#define NRDY7 0x0080 /* b7: PIPE7 */ +#define NRDY6 0x0040 /* b6: PIPE6 */ +#define NRDY5 0x0020 /* b5: PIPE5 */ +#define NRDY4 0x0010 /* b4: PIPE4 */ +#define NRDY3 0x0008 /* b3: PIPE3 */ +#define NRDY2 0x0004 /* b2: PIPE2 */ +#define NRDY1 0x0002 /* b1: PIPE1 */ +#define NRDY0 0x0001 /* b1: PIPE0 */ + +/* BEMP Interrupt Enable/Status Register */ +#define BEMP9 0x0200 /* b9: PIPE9 */ +#define BEMP8 0x0100 /* b8: PIPE8 */ +#define BEMP7 0x0080 /* b7: PIPE7 */ +#define BEMP6 0x0040 /* b6: PIPE6 */ +#define BEMP5 0x0020 /* b5: PIPE5 */ +#define BEMP4 0x0010 /* b4: PIPE4 */ +#define BEMP3 0x0008 /* b3: PIPE3 */ +#define BEMP2 0x0004 /* b2: PIPE2 */ +#define BEMP1 0x0002 /* b1: PIPE1 */ +#define BEMP0 0x0001 /* b0: PIPE0 */ + +/* SOF Pin Configuration Register */ +#define TRNENSEL 0x0100 /* b8: Select transaction enable period */ +#define BRDYM 0x0040 /* b6: BRDY clear timing */ +#define INTL 0x0020 /* b5: Interrupt sense select */ +#define EDGESTS 0x0010 /* b4: */ +#define SOFMODE 0x000C /* b3-2: SOF pin select */ +#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */ +#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */ +#define SOF_DISABLE 0x0000 /* SOF OUT Disable */ + +/* Interrupt Status Register 0 */ +#define VBINT 0x8000 /* b15: VBUS interrupt */ +#define RESM 0x4000 /* b14: Resume interrupt */ +#define SOFR 0x2000 /* b13: SOF frame update interrupt */ +#define DVST 0x1000 /* b12: Device state transition interrupt */ +#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */ +#define BEMP 0x0400 /* b10: Buffer empty interrupt */ +#define NRDY 0x0200 /* b9: Buffer not ready interrupt */ +#define BRDY 0x0100 /* b8: Buffer ready interrupt */ +#define VBSTS 0x0080 /* b7: VBUS input port */ +#define DVSQ 0x0070 /* b6-4: Device state */ +#define DS_SPD_CNFG 0x0070 /* Suspend Configured */ +#define DS_SPD_ADDR 0x0060 /* Suspend Address */ +#define DS_SPD_DFLT 0x0050 /* Suspend Default */ +#define DS_SPD_POWR 0x0040 /* Suspend Powered */ +#define DS_SUSP 0x0040 /* Suspend */ +#define DS_CNFG 0x0030 /* Configured */ +#define DS_ADDS 0x0020 /* Address */ +#define DS_DFLT 0x0010 /* Default */ +#define DS_POWR 0x0000 /* Powered */ +#define DVSQS 0x0030 /* b5-4: Device state */ +#define VALID 0x0008 /* b3: Setup packet detected flag */ +#define CTSQ 0x0007 /* b2-0: Control transfer stage */ +#define CS_SQER 0x0006 /* Sequence error */ +#define CS_WRND 0x0005 /* Control write nodata status stage */ +#define CS_WRSS 0x0004 /* Control write status stage */ +#define CS_WRDS 0x0003 /* Control write data stage */ +#define CS_RDSS 0x0002 /* Control read status stage */ +#define CS_RDDS 0x0001 /* Control read data stage */ +#define CS_IDST 0x0000 /* Idle or setup stage */ + +/* Interrupt Status Register 1 */ +#define OVRCR 0x8000 /* b15: Over-current interrupt */ +#define BCHG 0x4000 /* b14: USB bus chenge interrupt */ +#define DTCH 0x1000 /* b12: Detach sense interrupt */ +#define ATTCH 0x0800 /* b11: Attach sense interrupt */ +#define EOFERR 0x0040 /* b6: EOF-error interrupt */ +#define SIGN 0x0020 /* b5: Setup ignore interrupt */ +#define SACK 0x0010 /* b4: Setup acknowledge interrupt */ + +/* Frame Number Register */ +#define OVRN 0x8000 /* b15: Overrun error */ +#define CRCE 0x4000 /* b14: Received data error */ +#define FRNM 0x07FF /* b10-0: Frame number */ + +/* Micro Frame Number Register */ +#define UFRNM 0x0007 /* b2-0: Micro frame number */ + +/* Default Control Pipe Maxpacket Size Register */ +/* Pipe Maxpacket Size Register */ +#define DEVSEL 0xF000 /* b15-14: Device address select */ +#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */ + +/* Default Control Pipe Control Register */ +#define BSTS 0x8000 /* b15: Buffer status */ +#define SUREQ 0x4000 /* b14: Send USB request */ +#define CSCLR 0x2000 /* b13: complete-split status clear */ +#define CSSTS 0x1000 /* b12: complete-split status */ +#define SUREQCLR 0x0800 /* b11: stop setup request */ +#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ +#define SQSET 0x0080 /* b7: Sequence toggle bit set */ +#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ +#define PBUSY 0x0020 /* b5: pipe busy */ +#define PINGE 0x0010 /* b4: ping enable */ +#define CCPL 0x0004 /* b2: Enable control transfer complete */ +#define PID 0x0003 /* b1-0: Response PID */ +#define PID_STALL11 0x0003 /* STALL */ +#define PID_STALL 0x0002 /* STALL */ +#define PID_BUF 0x0001 /* BUF */ +#define PID_NAK 0x0000 /* NAK */ + +/* Pipe Window Select Register */ +#define PIPENM 0x0007 /* b2-0: Pipe select */ + +/* Pipe Configuration Register */ +#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */ +#define R8A66597_ISO 0xC000 /* Isochronous */ +#define R8A66597_INT 0x8000 /* Interrupt */ +#define R8A66597_BULK 0x4000 /* Bulk */ +#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */ +#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */ +#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */ +#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */ +#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */ +#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */ + +/* Pipe Buffer Configuration Register */ +#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */ +#define BUFNMB 0x007F /* b6-0: Pipe buffer number */ +#define PIPE0BUF 256 +#define PIPExBUF 64 + +/* Pipe Maxpacket Size Register */ +#define MXPS 0x07FF /* b10-0: Maxpacket size */ + +/* Pipe Cycle Configuration Register */ +#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */ +#define IITV 0x0007 /* b2-0: Isochronous interval */ + +/* Pipex Control Register */ +#define BSTS 0x8000 /* b15: Buffer status */ +#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */ +#define CSCLR 0x2000 /* b13: complete-split status clear */ +#define CSSTS 0x1000 /* b12: complete-split status */ +#define ATREPM 0x0400 /* b10: Auto repeat mode */ +#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */ +#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ +#define SQSET 0x0080 /* b7: Sequence toggle bit set */ +#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ +#define PBUSY 0x0020 /* b5: pipe busy */ +#define PID 0x0003 /* b1-0: Response PID */ + +/* PIPExTRE */ +#define TRENB 0x0200 /* b9: Transaction counter enable */ +#define TRCLR 0x0100 /* b8: Transaction counter clear */ + +/* PIPExTRN */ +#define TRNCNT 0xFFFF /* b15-0: Transaction counter */ + +/* DEVADDx */ +#define UPPHUB 0x7800 +#define HUBPORT 0x0700 +#define USBSPD 0x00C0 +#define RTPORT 0x0001 + +#define R8A66597_MAX_NUM_PIPE 10 +#define R8A66597_BUF_BSIZE 8 +#define R8A66597_MAX_DEVICE 10 +#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) +#define R8A66597_MAX_ROOT_HUB 1 +#else +#define R8A66597_MAX_ROOT_HUB 2 +#endif +#define R8A66597_MAX_SAMPLING 5 +#define R8A66597_RH_POLL_TIME 10 + +#define BULK_IN_PIPENUM 3 +#define BULK_IN_BUFNUM 8 + +#define BULK_OUT_PIPENUM 4 +#define BULK_OUT_BUFNUM 40 + +#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5)) +#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9)) +#define make_devsel(addr) (addr << 12) + +struct r8a66597 { + unsigned long reg; + unsigned short pipe_config; /* bit field */ + unsigned short port_status; + unsigned short port_change; + u16 speed; /* HSMODE or FSMODE or LSMODE */ + unsigned char rh_devnum; +}; + +static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset) +{ + return inw(r8a66597->reg + offset); +} + +static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, + unsigned long offset, void *buf, + int len) +{ + int i; +#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) + unsigned long fifoaddr = r8a66597->reg + offset; + unsigned long count; + unsigned long *p = buf; + + count = len / 4; + for (i = 0; i < count; i++) + inl(p[i], r8a66597->reg + offset); + + if (len & 0x00000003) { + unsigned long tmp = inl(fifoaddr); + memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03); + } +#else + unsigned short *p = buf; + + len = (len + 1) / 2; + for (i = 0; i < len; i++) + p[i] = inw(r8a66597->reg + offset); +#endif +} + +static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, + unsigned long offset) +{ + outw(val, r8a66597->reg + offset); +} + +static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, + unsigned long offset, void *buf, + int len) +{ + int i; + unsigned long fifoaddr = r8a66597->reg + offset; +#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) + unsigned long count; + unsigned char *pb; + unsigned long *p = buf; + + count = len / 4; + for (i = 0; i < count; i++) + outl(p[i], fifoaddr); + + if (len & 0x00000003) { + pb = (unsigned char *)buf + count * 4; + for (i = 0; i < (len & 0x00000003); i++) { + if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND) + outb(pb[i], fifoaddr + i); + else + outb(pb[i], fifoaddr + 3 - i); + } + } +#else + int odd = len & 0x0001; + unsigned short *p = buf; + + len = len / 2; + for (i = 0; i < len; i++) + outw(p[i], fifoaddr); + + if (odd) { + unsigned char *pb = (unsigned char *)(buf + len); + outb(*pb, fifoaddr); + } +#endif +} + +static inline void r8a66597_mdfy(struct r8a66597 *r8a66597, + u16 val, u16 pat, unsigned long offset) +{ + u16 tmp; + tmp = r8a66597_read(r8a66597, offset); + tmp = tmp & (~pat); + tmp = tmp | val; + r8a66597_write(r8a66597, tmp, offset); +} + +#define r8a66597_bclr(r8a66597, val, offset) \ + r8a66597_mdfy(r8a66597, 0, val, offset) +#define r8a66597_bset(r8a66597, val, offset) \ + r8a66597_mdfy(r8a66597, val, 0, offset) + +static inline unsigned long get_syscfg_reg(int port) +{ + return port == 0 ? SYSCFG0 : SYSCFG1; +} + +static inline unsigned long get_syssts_reg(int port) +{ + return port == 0 ? SYSSTS0 : SYSSTS1; +} + +static inline unsigned long get_dvstctr_reg(int port) +{ + return port == 0 ? DVSTCTR0 : DVSTCTR1; +} + +static inline unsigned long get_dmacfg_reg(int port) +{ + return port == 0 ? DMA0CFG : DMA1CFG; +} + +static inline unsigned long get_intenb_reg(int port) +{ + return port == 0 ? INTENB1 : INTENB2; +} + +static inline unsigned long get_intsts_reg(int port) +{ + return port == 0 ? INTSTS1 : INTSTS2; +} + +static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port) +{ + unsigned long dvstctr_reg = get_dvstctr_reg(port); + + return r8a66597_read(r8a66597, dvstctr_reg) & RHST; +} + +static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port, + int power) +{ + unsigned long dvstctr_reg = get_dvstctr_reg(port); + + if (power) + r8a66597_bset(r8a66597, VBOUT, dvstctr_reg); + else + r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg); +} + +#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2) +#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4) +#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4) +#define get_devadd_addr(address) (DEVADD0 + address * 2) + + +/* USB HUB CONSTANTS (not OHCI-specific; see hub.h, based on usb_ohci.h) */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + + +/* OHCI ROOT HUB REGISTER MASKS */ + +/* roothub.portstatus [i] bits */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ + +/* roothub.status bits */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + + +#endif /* __R8A66597_H__ */ + diff --git a/drivers/usb/usbdcore_omap1510.c b/drivers/usb/usbdcore_omap1510.c index 84bb936d8..4e3239f58 100644 --- a/drivers/usb/usbdcore_omap1510.c +++ b/drivers/usb/usbdcore_omap1510.c @@ -28,7 +28,7 @@ #include <common.h> -#if defined(CONFIG_OMAP1510) && defined(CONFIG_USB_DEVICE) +#if ((defined(CONFIG_OMAP1510) || defined(CONFIG_OMAP1610)) && defined(CONFIG_USB_DEVICE)) #include <asm/io.h> #ifdef CONFIG_OMAP_SX1 @@ -1109,21 +1109,43 @@ int udc_init (void) */ outw ((1 << 4) | (1 << 5), CLOCK_CTRL); UDCREG (CLOCK_CTRL); + +#ifdef CONFIG_OMAP1510 + /* This code was originally implemented for OMAP1510 and + * therefore is only applicable for OMAP1510 boards. For + * OMAP5912 or OMAP16xx the register APLL_CTRL does not + * exist and DPLL_CTRL is already configured. + */ + /* Set and check APLL */ outw (0x0008, APLL_CTRL); UDCREG (APLL_CTRL); /* Set and check DPLL */ outw (0x2210, DPLL_CTRL); UDCREG (DPLL_CTRL); - /* Set and check SOFT */ - outw ((1 << 4) | (1 << 3) | 1, SOFT_REQ); +#endif + /* Set and check SOFT + * The below line of code has been changed to perform a + * read-modify-write instead of a simple write for + * configuring the SOFT_REQ register. This allows the code + * to be compatible with OMAP5912 and OMAP16xx devices + */ + outw ((1 << 4) | (1 << 3) | 1 | (inw(SOFT_REQ)), SOFT_REQ); + /* Short delay to wait for DPLL */ udelay (1000); /* Print banner with device revision */ udc_rev = inw (UDC_REV) & 0xff; +#ifdef CONFIG_OMAP1510 printf ("USB: TI OMAP1510 USB function module rev %d.%d\n", udc_rev >> 4, udc_rev & 0xf); +#endif + +#ifdef CONFIG_OMAP1610 + printf ("USB: TI OMAP5912 USB function module rev %d.%d\n", + udc_rev >> 4, udc_rev & 0xf); +#endif #ifdef CONFIG_OMAP_SX1 i2c_read (0x32, 0x04, 1, &value, 1); diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 68b9861d4..d313e9098 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -751,24 +751,10 @@ void video_puts (const char *s) fb ++; \ } -#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP) #define FILL_15BIT_555RGB(r,g,b) { \ *(unsigned short *)fb = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \ fb += 2; \ } -#else -static int tgl; -static unsigned short p0; -#define FILL_15BIT_555RGB(r,g,b) { \ - if (!tgl++) { \ - p0 = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \ - } else { \ - tgl=0; \ - *(unsigned long *)(fb-2) = (SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3)))<<16) | p0; \ - } \ - fb += 2; \ -} -#endif #define FILL_16BIT_565RGB(r,g,b) { \ *(unsigned short *)fb = SWAP16((unsigned short)((((r)>>3)<<11) | (((g)>>2)<<5) | ((b)>>3))); \ @@ -796,6 +782,20 @@ static unsigned short p0; } #endif +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) +static void inline fill_555rgb_pswap(uchar *fb, int x, + u8 r, u8 g, u8 b) +{ + ushort *dst = (ushort *)fb; + ushort color = (ushort)(((r >> 3) << 10) | + ((g >> 3) << 5) | + (b >> 3)); + if (x & 1) + *(--dst) = color; + else + *(++dst) = color; +} +#endif /* * Display the BMP file located at address bmp_image. @@ -927,11 +927,20 @@ int video_display_bitmap (ulong bmp_image, int x, int y) break; case GDF_15BIT_555RGB: while (ycount--) { +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) + int xpos = x; +#endif WATCHDOG_RESET (); xcount = width; while (xcount--) { cte = bmp->color_table[*bmap++]; +#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP) FILL_15BIT_555RGB (cte.red, cte.green, cte.blue); +#else + fill_555rgb_pswap (fb, xpos++, cte.red, + cte.green, cte.blue); + fb += 2; +#endif } bmap += padded_line; fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; @@ -993,10 +1002,19 @@ int video_display_bitmap (ulong bmp_image, int x, int y) break; case GDF_15BIT_555RGB: while (ycount--) { +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) + int xpos = x; +#endif WATCHDOG_RESET (); xcount = width; while (xcount--) { +#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP) FILL_15BIT_555RGB (bmap[2], bmap[1], bmap[0]); +#else + fill_555rgb_pswap (fb, xpos++, bmap[2], + bmap[1], bmap[0]); + fb += 2; +#endif bmap += 3; } bmap += padded_line; @@ -1071,7 +1089,9 @@ void logo_plot (void *screen, int width, int x, int y) int ycount = VIDEO_LOGO_HEIGHT; unsigned char r, g, b, *logo_red, *logo_blue, *logo_green; unsigned char *source; - unsigned char *dest = (unsigned char *)screen + ((y * width * VIDEO_PIXEL_SIZE) + x); + unsigned char *dest = (unsigned char *)screen + + ((y * width * VIDEO_PIXEL_SIZE) + + x * VIDEO_PIXEL_SIZE); #ifdef CONFIG_VIDEO_BMP_LOGO source = bmp_logo_bitmap; @@ -1101,6 +1121,9 @@ void logo_plot (void *screen, int width, int x, int y) } while (ycount--) { +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) + int xpos = x; +#endif xcount = VIDEO_LOGO_WIDTH; while (xcount--) { r = logo_red[*source - VIDEO_LOGO_LUT_OFFSET]; @@ -1119,15 +1142,7 @@ void logo_plot (void *screen, int width, int x, int y) *(unsigned short *) dest = SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3))); #else - { - if (!tgl++) { - p0 = SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3))); - } else { - *(unsigned long *)(dest-2) = - (SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3)))<<16) | p0; - tgl=0; - } - } + fill_555rgb_pswap (dest, xpos++, r, g, b); #endif break; case GDF_16BIT_565RGB: diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h index e4b68aba7..66db29649 100644 --- a/include/configs/FPS850L.h +++ b/include/configs/FPS850L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -65,10 +65,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/fps850L/uImage\0" \ + "hostname=FPS850L\0" \ + "bootfile=FPS850L/uImage\0" \ "fdt_addr=40040000\0" \ "kernel_addr=40060000\0" \ "ramdisk_addr=40200000\0" \ + "u-boot=FPS850L/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -106,10 +113,14 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -180,11 +191,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ @@ -194,6 +209,20 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + +/*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h index ed612c339..84607ccc3 100644 --- a/include/configs/FPS860L.h +++ b/include/configs/FPS860L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -65,10 +65,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/fps850L/uImage\0" \ + "hostname=FPS860L\0" \ + "bootfile=FPS860L/uImage\0" \ "fdt_addr=40040000\0" \ "kernel_addr=40060000\0" \ "ramdisk_addr=40200000\0" \ + "u-boot=FPS860L/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -106,10 +113,14 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -180,11 +191,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ @@ -194,6 +209,20 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + +/*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -306,9 +335,11 @@ #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -337,12 +368,42 @@ /* * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 */ -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ @@ -372,4 +433,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_SCC1_ENET + #endif /* __CONFIG_H */ diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h index 11e5c63ed..21d90c303 100644 --- a/include/configs/NSCU.h +++ b/include/configs/NSCU.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -67,9 +67,16 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/NSCU/uImage\0" \ + "hostname=NSCU\0" \ + "bootfile=${hostname}/uImage\0" \ "kernel_addr=40080000\0" \ "ramdisk_addr=40180000\0" \ + "u-boot=${hostname}/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -110,20 +117,24 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 +#define CONFIG_CMDLINE_EDITING 1 /* add command line history +*/ #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif @@ -186,21 +197,26 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 100be7cab..f807271ba 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -37,6 +37,8 @@ #define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ #ifdef CONFIG_LCD /* with LCD controller ? */ +#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ +#define CONFIG_LCD_INFO 1 /* ... and some board info */ #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ #endif @@ -69,10 +71,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM823L/uImage\0" \ + "hostname=TQM823L\0" \ + "bootfile=TQM823L/uImage\0" \ "fdt_addr=40040000\0" \ "kernel_addr=40060000\0" \ "ramdisk_addr=40200000\0" \ + "u-boot=TQM823L/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -113,7 +122,9 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP @@ -122,6 +133,8 @@ #endif +#define CONFIG_NETCONSOLE + /* * Miscellaneous configurable options */ @@ -196,7 +209,7 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -213,6 +226,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 40dc26bf7..431ae8c5a 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -69,10 +69,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM823M/uImage\0" \ + "hostname=TQM823M\0" \ + "bootfile=TQM823M/uImage\0" \ "fdt_addr=40080000\0" \ "kernel_addr=400A0000\0" \ "ramdisk_addr=40280000\0" \ + "u-boot=TQM823M/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -113,11 +120,16 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -210,6 +222,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ + "128k(dtb)," \ + "1920k(kernel)," \ + "5632(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 3097bc316..7946c13a1 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -65,10 +65,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM850L/uImage\0" \ + "hostname=TQM850L\0" \ + "bootfile=TQM850L/uImage\0" \ "fdt_addr=40040000\0" \ "kernel_addr=40060000\0" \ "ramdisk_addr=40200000\0" \ + "u-boot=TQM850L/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -104,11 +111,15 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + /* * Miscellaneous configurable options */ @@ -183,7 +194,7 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -200,6 +211,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index becf82c8b..777776d42 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -63,10 +63,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM850M/uImage\0" \ + "hostname=TQM850M\0" \ + "bootfile=TQM850M/uImage\0" \ "fdt_addr=40080000\0" \ "kernel_addr=400A0000\0" \ "ramdisk_addr=40280000\0" \ + "u-boot=TQM850M/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -102,11 +109,16 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -199,6 +211,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ + "128k(dtb)," \ + "1920k(kernel)," \ + "5632(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 8ca890611..0549cbd94 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -68,10 +68,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM855L/uImage\0" \ + "hostname=TQM855L\0" \ + "bootfile=TQM855L/uImage\0" \ "fdt_addr=40040000\0" \ "kernel_addr=40060000\0" \ "ramdisk_addr=40200000\0" \ + "u-boot=TQM855L/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -108,11 +115,16 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -187,7 +199,7 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -204,6 +216,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 2696ea502..bc092b7f2 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -68,10 +68,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM855M/uImage\0" \ + "hostname=TQM855M\0" \ + "bootfile=TQM855M/uImage\0" \ "fdt_addr=40080000\0" \ "kernel_addr=400A0000\0" \ "ramdisk_addr=40280000\0" \ + "u-boot=TQM855M/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -141,12 +148,17 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_EEPROM #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -239,6 +251,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ + "128k(dtb)," \ + "1920k(kernel)," \ + "5632(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index f66aace31..065156fe3 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -68,10 +68,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM860L/uImage\0" \ + "hostname=TQM860L\0" \ + "bootfile=TQM860L/uImage\0" \ "fdt_addr=40040000\0" \ "kernel_addr=40060000\0" \ "ramdisk_addr=40200000\0" \ + "u-boot=TQM860L/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -110,6 +117,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP @@ -190,7 +198,7 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -207,6 +215,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 00b78534a..ff610bfe3 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -68,15 +68,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM860M/uImage\0" \ + "hostname=TQM860M\0" \ + "bootfile=TQM860M/uImage\0" \ "fdt_addr=400C0000\0" \ "kernel_addr=40100000\0" \ "ramdisk_addr=40280000\0" \ + "u-boot=TQM860M/u-image.bin\0" \ "load=tftp 200000 ${u-boot}\0" \ - "update=protect off 40000000 +${filesize};" \ - "erase 40000000 +${filesize};" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ "cp.b 200000 40000000 ${filesize};" \ - "protect on 40000000 +${filesize}\0" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -115,10 +117,14 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -210,6 +216,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ + "128k(dtb)," \ + "1920k(kernel)," \ + "5632(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 7813a20dc..33ff8a909 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -71,10 +71,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM862L/uImage\0" \ + "hostname=TQM862L\0" \ + "bootfile=TQM862L/uImage\0" \ "fdt_addr=40040000\0" \ "kernel_addr=40060000\0" \ "ramdisk_addr=40200000\0" \ + "u-boot=TQM862L/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -111,11 +118,16 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -190,7 +202,7 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -207,6 +219,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 05395e0d4..1ec44319e 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -71,10 +71,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM862M/uImage\0" \ + "hostname=TQM862M\0" \ + "bootfile=TQM862M/uImage\0" \ "fdt_addr=40080000\0" \ "kernel_addr=400A0000\0" \ "ramdisk_addr=40280000\0" \ + "u-boot=TQM862M/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -111,11 +118,16 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#define CONFIG_NETCONSOLE + + /* * Miscellaneous configurable options */ @@ -208,6 +220,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ + "128k(dtb)," \ + "1920k(kernel)," \ + "5632(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index d033875dc..0cee9f4fe 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -80,15 +80,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM866M/uImage\0" \ + "hostname=TQM866M\0" \ + "bootfile=TQM866M/uImage\0" \ "fdt_addr=400C0000\0" \ "kernel_addr=40100000\0" \ "ramdisk_addr=40280000\0" \ + "u-boot=TQM866M/u-image.bin\0" \ "load=tftp 200000 ${u-boot}\0" \ - "update=protect off 40000000 +${filesize};" \ - "erase 40000000 +${filesize};" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ "cp.b 200000 40000000 ${filesize};" \ - "protect on 40000000 +${filesize}\0" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -157,9 +159,14 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + + +#define CONFIG_NETCONSOLE /* @@ -253,6 +260,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ + "128k(dtb)," \ + "1920k(kernel)," \ + "5632(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index f104e68f1..091da803a 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -308,6 +308,7 @@ #define CONFIG_PHY_ADDR 0x1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_FEC_AN_TIMEOUT 1 +#define CONFIG_HAS_ETH0 /* * Configure on-board RTC @@ -478,10 +479,10 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 #define OF_CPU "PowerPC,5121@0" -#define OF_SOC "soc@80000000" -#define OF_SOC_OLD "soc5121@80000000" +#define OF_SOC_COMPAT "fsl,mpc5121-immr" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc@80000000/serial@11300" diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index 7713eaaf5..5a6566320 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -38,7 +38,11 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING #define CONFIG_CMD_ENV +#define CONFIG_CMD_NFS +#define CONFIG_CMD_JFFS2 #define CONFIG_BOOTDELAY -1 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01" @@ -113,4 +117,9 @@ #define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ #define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) +/* Ether */ +#define CONFIG_SH_ETHER 1 +#define CONFIG_SH_ETHER_USE_PORT (1) +#define CONFIG_SH_ETHER_PHY_ADDR (0x01) + #endif /* __SH7763RDP_H */ diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h index 6bb075d27..54d9421d7 100644 --- a/include/configs/virtlab2.h +++ b/include/configs/virtlab2.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -37,10 +37,6 @@ #define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */ #define CONFIG_TQM8xxL 1 -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE @@ -70,9 +66,17 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM823L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ + "hostname=virtlab2\0" \ + "bootfile=virtlab2/uImage\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ + "u-boot=virtlab2/u-image.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=prot off 40000000 +${filesize};" \ + "era 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -114,6 +118,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP @@ -122,15 +127,16 @@ #endif +#define CONFIG_NETCONSOLE + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif @@ -197,7 +203,7 @@ /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_USE_BUFFER_WRITE 1 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -214,6 +220,18 @@ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" + +#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ + "128k(dtb)," \ + "1664k(kernel)," \ + "2m(rootfs)," \ + "4m(data)" + +/*----------------------------------------------------------------------- * Hardware Information Block */ #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ diff --git a/include/dataflash.h b/include/dataflash.h index 80f0633aa..de041397d 100644 --- a/include/dataflash.h +++ b/include/dataflash.h @@ -135,9 +135,9 @@ struct dataflash_addr { int cs; }; /*-------------------------------------------------------------------------------------------------*/ - #define AT45DB161 0x2c #define AT45DB021 0x14 +#define AT45DB081 0x24 #define AT45DB321 0x34 #define AT45DB642 0x3c #define AT45DB128 0x10 diff --git a/include/image.h b/include/image.h index 46138fa78..4b9c58271 100644 --- a/include/image.h +++ b/include/image.h @@ -220,7 +220,6 @@ typedef struct bootm_headers { #endif int verify; /* getenv("verify")[0] != 'n' */ - int autostart; /* getenv("autostart")[0] != 'n' */ struct lmb *lmb; /* for memory mgmt */ } bootm_headers_t; diff --git a/include/mpc512x.h b/include/mpc512x.h index b4cc2b9e9..a76b1ca21 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -347,41 +347,226 @@ /* IO Control Register */ +#define IOCTL_MEM 0x000 +#define IOCTL_GP 0x004 +#define IOCTL_LPC_CLK 0x008 +#define IOCTL_LPC_OE 0x00C +#define IOCTL_LPC_RWB 0x010 +#define IOCTL_LPC_ACK 0x014 +#define IOCTL_LPC_CS0 0x018 +#define IOCTL_NFC_CE0 0x01C +#define IOCTL_LPC_CS1 0x020 +#define IOCTL_LPC_CS2 0x024 +#define IOCTL_LPC_AX03 0x028 +#define IOCTL_EMB_AX02 0x02C +#define IOCTL_EMB_AX01 0x030 +#define IOCTL_EMB_AX00 0x034 +#define IOCTL_EMB_AD31 0x038 +#define IOCTL_EMB_AD30 0x03C +#define IOCTL_EMB_AD29 0x040 +#define IOCTL_EMB_AD28 0x044 +#define IOCTL_EMB_AD27 0x048 +#define IOCTL_EMB_AD26 0x04C +#define IOCTL_EMB_AD25 0x050 +#define IOCTL_EMB_AD24 0x054 +#define IOCTL_EMB_AD23 0x058 +#define IOCTL_EMB_AD22 0x05C +#define IOCTL_EMB_AD21 0x060 +#define IOCTL_EMB_AD20 0x064 +#define IOCTL_EMB_AD19 0x068 +#define IOCTL_EMB_AD18 0x06C +#define IOCTL_EMB_AD17 0x070 +#define IOCTL_EMB_AD16 0x074 +#define IOCTL_EMB_AD15 0x078 +#define IOCTL_EMB_AD14 0x07C +#define IOCTL_EMB_AD13 0x080 +#define IOCTL_EMB_AD12 0x084 +#define IOCTL_EMB_AD11 0x088 +#define IOCTL_EMB_AD10 0x08C +#define IOCTL_EMB_AD09 0x090 +#define IOCTL_EMB_AD08 0x094 +#define IOCTL_EMB_AD07 0x098 +#define IOCTL_EMB_AD06 0x09C +#define IOCTL_EMB_AD05 0x0A0 +#define IOCTL_EMB_AD04 0x0A4 +#define IOCTL_EMB_AD03 0x0A8 +#define IOCTL_EMB_AD02 0x0AC +#define IOCTL_EMB_AD01 0x0B0 +#define IOCTL_EMB_AD00 0x0B4 +#define IOCTL_PATA_CE1 0x0B8 +#define IOCTL_PATA_CE2 0x0BC +#define IOCTL_PATA_ISOLATE 0x0C0 +#define IOCTL_PATA_IOR 0x0C4 +#define IOCTL_PATA_IOW 0x0C8 +#define IOCTL_PATA_IOCHRDY 0x0CC +#define IOCTL_PATA_INTRQ 0x0D0 +#define IOCTL_PATA_DRQ 0x0D4 +#define IOCTL_PATA_DACK 0x0D8 +#define IOCTL_NFC_WP 0x0DC +#define IOCTL_NFC_RB 0x0E0 +#define IOCTL_NFC_ALE 0x0E4 +#define IOCTL_NFC_CLE 0x0E8 +#define IOCTL_NFC_WE 0x0EC +#define IOCTL_NFC_RE 0x0F0 +#define IOCTL_PCI_AD31 0x0F4 +#define IOCTL_PCI_AD30 0x0F8 +#define IOCTL_PCI_AD29 0x0FC +#define IOCTL_PCI_AD28 0x100 +#define IOCTL_PCI_AD27 0x104 +#define IOCTL_PCI_AD26 0x108 +#define IOCTL_PCI_AD25 0x10C +#define IOCTL_PCI_AD24 0x110 +#define IOCTL_PCI_AD23 0x114 +#define IOCTL_PCI_AD22 0x118 +#define IOCTL_PCI_AD21 0x11C +#define IOCTL_PCI_AD20 0x120 +#define IOCTL_PCI_AD19 0x124 +#define IOCTL_PCI_AD18 0x128 +#define IOCTL_PCI_AD17 0x12C +#define IOCTL_PCI_AD16 0x130 +#define IOCTL_PCI_AD15 0x134 +#define IOCTL_PCI_AD14 0x138 +#define IOCTL_PCI_AD13 0x13C +#define IOCTL_PCI_AD12 0x140 +#define IOCTL_PCI_AD11 0x144 +#define IOCTL_PCI_AD10 0x148 +#define IOCTL_PCI_AD09 0x14C +#define IOCTL_PCI_AD08 0x150 +#define IOCTL_PCI_AD07 0x154 +#define IOCTL_PCI_AD06 0x158 +#define IOCTL_PCI_AD05 0x15C +#define IOCTL_PCI_AD04 0x160 +#define IOCTL_PCI_AD03 0x164 +#define IOCTL_PCI_AD02 0x168 +#define IOCTL_PCI_AD01 0x16C +#define IOCTL_PCI_AD00 0x170 +#define IOCTL_PCI_CBE0 0x174 +#define IOCTL_PCI_CBE1 0x178 +#define IOCTL_PCI_CBE2 0x17C +#define IOCTL_PCI_CBE3 0x180 +#define IOCTL_PCI_GNT2 0x184 +#define IOCTL_PCI_REQ2 0x188 +#define IOCTL_PCI_GNT1 0x18C +#define IOCTL_PCI_REQ1 0x190 +#define IOCTL_PCI_GNT0 0x194 +#define IOCTL_PCI_REQ0 0x198 +#define IOCTL_PCI_INTA 0x19C +#define IOCTL_PCI_CLK 0x1A0 +#define IOCTL_PCI_RST_OUT 0x1A4 +#define IOCTL_PCI_FRAME 0x1A8 +#define IOCTL_PCI_IDSEL 0x1AC +#define IOCTL_PCI_DEVSEL 0x1B0 +#define IOCTL_PCI_IRDY 0x1B4 +#define IOCTL_PCI_TRDY 0x1B8 +#define IOCTL_PCI_STOP 0x1BC +#define IOCTL_PCI_PAR 0x1C0 +#define IOCTL_PCI_PERR 0x1C4 +#define IOCTL_PCI_SERR 0x1C8 +#define IOCTL_SPDIF_TXCLK 0x1CC +#define IOCTL_SPDIF_TX 0x1D0 +#define IOCTL_SPDIF_RX 0x1D4 +#define IOCTL_I2C0_SCL 0x1D8 +#define IOCTL_I2C0_SDA 0x1DC +#define IOCTL_I2C1_SCL 0x1E0 +#define IOCTL_I2C1_SDA 0x1E4 +#define IOCTL_I2C2_SCL 0x1E8 +#define IOCTL_I2C2_SDA 0x1EC +#define IOCTL_IRQ0 0x1F0 +#define IOCTL_IRQ1 0x1F4 +#define IOCTL_CAN1_TX 0x1F8 +#define IOCTL_CAN2_TX 0x1FC +#define IOCTL_J1850_TX 0x200 +#define IOCTL_J1850_RX 0x204 +#define IOCTL_PSC_MCLK_IN 0x208 +#define IOCTL_PSC0_0 0x20C +#define IOCTL_PSC0_1 0x210 +#define IOCTL_PSC0_2 0x214 +#define IOCTL_PSC0_3 0x218 +#define IOCTL_PSC0_4 0x21C +#define IOCTL_PSC1_0 0x220 +#define IOCTL_PSC1_1 0x224 +#define IOCTL_PSC1_2 0x228 +#define IOCTL_PSC1_3 0x22C +#define IOCTL_PSC1_4 0x230 +#define IOCTL_PSC2_0 0x234 +#define IOCTL_PSC2_1 0x238 +#define IOCTL_PSC2_2 0x23C +#define IOCTL_PSC2_3 0x240 +#define IOCTL_PSC2_4 0x244 +#define IOCTL_PSC3_0 0x248 +#define IOCTL_PSC3_1 0x24C +#define IOCTL_PSC3_2 0x250 +#define IOCTL_PSC3_3 0x254 +#define IOCTL_PSC3_4 0x258 +#define IOCTL_PSC4_0 0x25C +#define IOCTL_PSC4_1 0x260 +#define IOCTL_PSC4_2 0x264 +#define IOCTL_PSC4_3 0x268 +#define IOCTL_PSC4_4 0x26C +#define IOCTL_PSC5_0 0x270 +#define IOCTL_PSC5_1 0x274 +#define IOCTL_PSC5_2 0x278 +#define IOCTL_PSC5_3 0x27C +#define IOCTL_PSC5_4 0x280 +#define IOCTL_PSC6_0 0x284 +#define IOCTL_PSC6_1 0x288 +#define IOCTL_PSC6_2 0x28C +#define IOCTL_PSC6_3 0x290 +#define IOCTL_PSC6_4 0x294 +#define IOCTL_PSC7_0 0x298 +#define IOCTL_PSC7_1 0x29C +#define IOCTL_PSC7_2 0x2A0 +#define IOCTL_PSC7_3 0x2A4 +#define IOCTL_PSC7_4 0x2A8 +#define IOCTL_PSC8_0 0x2AC +#define IOCTL_PSC8_1 0x2B0 +#define IOCTL_PSC8_2 0x2B4 +#define IOCTL_PSC8_3 0x2B8 +#define IOCTL_PSC8_4 0x2BC +#define IOCTL_PSC9_0 0x2C0 +#define IOCTL_PSC9_1 0x2C4 +#define IOCTL_PSC9_2 0x2C8 +#define IOCTL_PSC9_3 0x2CC +#define IOCTL_PSC9_4 0x2D0 +#define IOCTL_PSC10_0 0x2D4 +#define IOCTL_PSC10_1 0x2D8 +#define IOCTL_PSC10_2 0x2DC +#define IOCTL_PSC10_3 0x2E0 +#define IOCTL_PSC10_4 0x2E4 +#define IOCTL_PSC11_0 0x2E8 +#define IOCTL_PSC11_1 0x2EC +#define IOCTL_PSC11_2 0x2F0 +#define IOCTL_PSC11_3 0x2F4 +#define IOCTL_PSC11_4 0x2F8 +#define IOCTL_HRESET 0x2FC +#define IOCTL_SRESET 0x300 +#define IOCTL_CKSTP_OUT 0x304 +#define IOCTL_USB2_VBUS_PWR_FAULT 0x308 +#define IOCTL_USB2_VBUS_PWR_SELECT 0x30C +#define IOCTL_USB2_PHY_DRVV_BUS 0x310 -/* Indexes in regs array */ -#define MEM_IDX 0x00 -#define PATA_CE1_IDX 0x2e -#define PATA_CE2_IDX 0x2f -#define PATA_ISOLATE_IDX 0x30 -#define PATA_IOR_IDX 0x31 -#define PATA_IOW_IDX 0x32 -#define PATA_IOCHRDY_IDX 0x33 -#define PATA_INTRQ_IDX 0x34 -#define PATA_DRQ_IDX 0x35 -#define PATA_DACK_IDX 0x36 -#define SPDIF_TXCLOCK_IDX 0x73 -#define SPDIF_TX_IDX 0x74 -#define SPDIF_RX_IDX 0x75 -#define PSC0_0_IDX 0x83 -#define PSC0_1_IDX 0x84 -#define PSC0_2_IDX 0x85 -#define PSC0_3_IDX 0x86 -#define PSC0_4_IDX 0x87 -#define PSC1_0_IDX 0x88 -#define PSC1_1_IDX 0x89 -#define PSC1_2_IDX 0x8a -#define PSC1_3_IDX 0x8b -#define PSC1_4_IDX 0x8c -#define PSC2_0_IDX 0x8d -#define PSC2_1_IDX 0x8e -#define PSC2_2_IDX 0x8f -#define PSC2_3_IDX 0x90 -#define PSC2_4_IDX 0x91 +#ifndef __ASSEMBLY__ + + +/* IO pin fields */ +#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ +#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ +#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */ +#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */ +#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */ +#define IO_PIN_DS(v) ((v)) /* slew rate */ -#define IOCTRL_FUNCMUX_SHIFT 7 -#define IOCTRL_FUNCMUX_FEC 1 -#define IOCTRL_MUX_FEC (IOCTRL_FUNCMUX_FEC << IOCTRL_FUNCMUX_SHIFT) +typedef struct iopin_t { + int p_offset; /* offset from IOCTL_MEM_OFFSET */ + int nr_pins; /* number of pins to set this way */ + int bit_or; /* or in the value instead of overwrite */ + u_long val; /* value to write or or */ +}iopin_t; +void iopin_initialize(iopin_t *,int); +#endif + +/* Indexes in regs array */ /* Set for DDR */ #define IOCTRL_MUX_DDR 0x00000036 diff --git a/include/usb.h b/include/usb.h index 5a6ffddec..e68e98ead 100644 --- a/include/usb.h +++ b/include/usb.h @@ -171,7 +171,7 @@ struct usb_device { #if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \ defined(CONFIG_USB_OHCI_NEW) || defined (CONFIG_USB_SL811HS) || \ - defined(CONFIG_USB_ISP116X_HCD) + defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_R8A66597_HCD) int usb_lowlevel_init(void); int usb_lowlevel_stop(void); |