diff options
| -rw-r--r-- | drivers/mtd/st_smi.c | 34 | 
1 files changed, 21 insertions, 13 deletions
| diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 9769b284e..2c6d59ddb 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -108,11 +108,17 @@ static ulong flash_get_size(ulong base, int banknum)  {  	flash_info_t *info = &flash_info[banknum];  	struct flash_dev *dev; -	unsigned int value; +	int value;  	unsigned int density;  	int i;  	value = smi_read_id(info, banknum); + +	if (value < 0) { +		printf("Flash id could not be read\n"); +		return 0; +	} +  	density = (value >> 16) & 0xff;  	for (i = 0, dev = &flash_ids[0]; dev->density != 0x0; @@ -140,7 +146,7 @@ static ulong flash_get_size(ulong base, int banknum)   * This routine will get the status register of the flash chip present at the   * given bank   */ -static unsigned int smi_read_sr(int bank) +static int smi_read_sr(int bank)  {  	u32 ctrlreg1; @@ -174,13 +180,11 @@ static unsigned int smi_read_sr(int bank)   */  static int smi_wait_till_ready(int bank, int timeout)  { -	int count; -	unsigned int sr; +	int sr;  	/* One chip guarantees max 5 msec wait here after page writes,  	   but potentially three seconds (!) after page erase. */ -	for (count = 0; count < timeout; count++) { - +	do {  		sr = smi_read_sr(bank);  		if (sr < 0)  			break; @@ -189,7 +193,8 @@ static int smi_wait_till_ready(int bank, int timeout)  		/* Try again after 1m-sec */  		udelay(1000); -	} +	} while (timeout--); +  	printf("SMI controller is still in wait, timeout=%d\n", timeout);  	return -EIO;  } @@ -205,6 +210,7 @@ static int smi_write_enable(int bank)  {  	u32 ctrlreg1;  	int timeout = WMODE_TOUT; +	int sr;  	/* Store the CTRL REG1 state */  	ctrlreg1 = readl(&smicntl->smi_cr1); @@ -221,14 +227,16 @@ static int smi_write_enable(int bank)  	/* Restore the CTRL REG1 state */  	writel(ctrlreg1, &smicntl->smi_cr1); -	while (timeout--) { -		if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT))) +	do { +		sr = smi_read_sr(bank); +		if (sr < 0)  			break; -		udelay(1000); -	} +		else if (sr & (1 << (bank + WM_SHIFT))) +			return 0; -	if (timeout) -		return 0; +		/* Try again after 1m-sec */ +		udelay(1000); +	} while (timeout--);  	return -1;  } |