diff options
| -rw-r--r-- | CHANGELOG | 3 | ||||
| -rw-r--r-- | CREDITS | 10 | ||||
| -rw-r--r-- | MAKEALL | 2 | ||||
| -rw-r--r-- | Makefile | 5 | ||||
| -rw-r--r-- | README | 3 | ||||
| -rw-r--r-- | board/v37/Makefile | 40 | ||||
| -rw-r--r-- | board/v37/config.mk | 27 | ||||
| -rw-r--r-- | board/v37/flash.c | 559 | ||||
| -rw-r--r-- | board/v37/u-boot.lds | 142 | ||||
| -rw-r--r-- | board/v37/v37.c | 218 | ||||
| -rw-r--r-- | cpu/mpc8xx/lcd.c | 25 | ||||
| -rw-r--r-- | include/commproc.h | 62 | ||||
| -rw-r--r-- | include/configs/v37.h | 381 | ||||
| -rw-r--r-- | include/flash.h | 5 | ||||
| -rw-r--r-- | include/version.h | 2 |
15 files changed, 1459 insertions, 25 deletions
@@ -2,6 +2,9 @@ Changes since U-Boot 0.2.0: ====================================================================== +* Add support for V37 board + (patch by Jón Benediktsson, 11 Dec 2002) + * Update baudrate in bd_info when it gets changed * Add watchdog trigger points while waiting for serial port @@ -30,13 +30,17 @@ N: Pierre Aubert E: <p.aubert@staubli.com> D: Support for RPXClassic board +N: Jerry van Baren +E: <vanbaren@cideas.com> +D: BedBug port to 603e core (MPC82xx). Code for enhanced memory test. + N: Andre Beaudin E: <andre.beaudin@colubris.com> D: PCMCIA, Ethernet, TFTP -N: Jerry van Baren -E: <vanbaren@cideas.com> -D: BedBug port to 603e core (MPC82xx). Code for enhanced memory test. +N: Jon Benediktsson +E: jonb@marel.is +D: Support for Marel V37 board N: Raphael Bossek E: raphael.bossek@solutions4linux.de @@ -27,7 +27,7 @@ LIST_8xx=" \ RPXClassic RPXlite RRvision SM850 \ SPD823TS SXNI855T TQM823L TQM823L_LCD \ TQM850L TQM855L TQM860L TQM860L_FEC \ - TTTech + TTTech v37 \ " ######################################################################### @@ -380,6 +380,11 @@ TTTech_config: unconfig @echo "#define CONFIG_SHARP_LQ104V7DS01" >>include/config.h @./mkconfig -a TQM823L ppc mpc8xx tqm8xx +v37_config: unconfig + @echo "#define CONFIG_LCD" >include/config.h + @echo "#define CONFIG_SHARP_LQ084V1DG21" >>include/config.h + @./mkconfig $(@:_config=) ppc mpc8xx v37 + ######################################################################### ## PPC4xx Systems ######################################################################### @@ -337,7 +337,8 @@ The following options need to be configured: CONFIG_GENIETV, CONFIG_PM826, CONFIG_ppmc8260, CONFIG_GTH, CONFIG_RPXClassic, CONFIG_rsdproto, CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260, - CONFIG_EBONY, CONFIG_sacsng, CONFIG_FPS860L + CONFIG_EBONY, CONFIG_sacsng, CONFIG_FPS860L, + CONFIG_V37 ARM based boards: ----------------- diff --git a/board/v37/Makefile b/board/v37/Makefile new file mode 100644 index 000000000..baecac914 --- /dev/null +++ b/board/v37/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $^ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/v37/config.mk b/board/v37/config.mk new file mode 100644 index 000000000..50cac972e --- /dev/null +++ b/board/v37/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Marel V37 boards +# +TEXT_BASE = 0x40000000 diff --git a/board/v37/flash.c b/board/v37/flash.c new file mode 100644 index 000000000..4de0e1475 --- /dev/null +++ b/board/v37/flash.c @@ -0,0 +1,559 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Yoo. Jonghoon, IPone, yooth@ipone.co.kr + * PPCboot port on RPXlite board + * + * Some of flash control words are modified. (from 2x16bit device + * to 4x8bit device) + * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices + * are not tested. + * + * (?) Does an RPXLite board which + * does not use AM29LV800 flash memory exist ? + * I don't know... + */ + +#include <common.h> +#include <mpc8xx.h> + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips); +static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id); +static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + short manu, dev_id; + int i; + + /* Init: no FLASHes known */ + for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Do sizing to get full correct info */ + + flash_get_id_word((void*)CFG_FLASH_BASE0,&manu,&dev_id); + + size_b0 = flash_get_size(manu, dev_id, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE0, &flash_info[0],0); + + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (0 - size_b0); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE0 + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, + &flash_info[0]); +#endif + + flash_get_id_long((void*)CFG_FLASH_BASE1,&manu,&dev_id); + + size_b1 = 2 * flash_get_size(manu, dev_id, &flash_info[1]); + + flash_get_offsets(CFG_FLASH_BASE1, &flash_info[1],1); + + memctl->memc_or1 = CFG_OR_TIMING_FLASH | (0 - size_b1); + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0+size_b1); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips) +{ + int i, addr_shift; + vu_short *addr = (vu_short*)base; + + addr[0x555] = 0x00AA ; + addr[0xAAA] = 0x0055 ; + addr[0x555] = 0x0090 ; + + addr_shift = (two_chips ? 2 : 1 ); + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + (0x00000000<<addr_shift); + info->start[1] = base + (0x00002000<<addr_shift); + info->start[2] = base + (0x00003000<<addr_shift); + info->start[3] = base + (0x00004000<<addr_shift); + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + ((i-3) * (0x00008000<<addr_shift)) ; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - (0x00002000<<addr_shift); + info->start[i--] = base + info->size - (0x00003000<<addr_shift); + info->start[i--] = base + info->size - (0x00004000<<addr_shift); + for (; i >= 0; i--) { + info->start[i] = base + i * (0x00008000<<addr_shift); + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (vu_short *)(info->start[i]); + info->protect[i] = addr[1<<addr_shift] & 1 ; + } + + addr = (vu_short *)info->start[0]; + *addr = 0xF0F0; /* reset bank */ +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_TOSH: printf ("TOSHIBA "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; i<info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id) +{ + vu_short *addr = (vu_short*)ptr; + + addr[0x555] = 0x00AA ; + addr[0xAAA] = 0x0055 ; + addr[0x555] = 0x0090 ; + + *ptr_manuf = addr[0]; + *ptr_dev_id = addr[1]; + + addr[0] = 0xf0f0; /* return to normal */ +} + +static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id) +{ + vu_short *addr = (vu_short*)ptr; + vu_short *addr1, *addr2, *addr3; + + addr1 = (vu_short*) ( ((int)ptr) + (0x5555<<2) ); + addr2 = (vu_short*) ( ((int)ptr) + (0x2AAA<<2) ); + addr3 = (vu_short*) ( ((int)ptr) + (0x5555<<2) ); + + *addr1 = 0xAAAA; + *addr2 = 0x5555; + *addr3 = 0x9090; + + *ptr_manuf = addr[0]; + *ptr_dev_id = addr[2]; + + addr[0] = 0xf0f0; /* return to normal */ +} + +static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info) +{ + switch (manu) { + case ((short)AMD_MANUFACT): + info->flash_id = FLASH_MAN_AMD; + break; + case ((short)FUJ_MANUFACT): + info->flash_id = FLASH_MAN_FUJ; + break; + case ((short)TOSH_MANUFACT): + info->flash_id = FLASH_MAN_TOSH; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + + switch (dev_id) { + case ((short)TOSH_ID_FVT160): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 1 MB */ + + case ((short)TOSH_ID_FVB160): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 1 MB */ + + case ((short)AMD_ID_LV400T): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case ((short)AMD_ID_LV400B): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case ((short)AMD_ID_LV800T): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case ((short)AMD_ID_LV800B): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00400000; //%%% Size doubled by yooth + break; /* => 4 MB */ + + case ((short)AMD_ID_LV160T): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 4 MB */ + + case ((short)AMD_ID_LV160B): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 4 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + return(info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_short *addr = (vu_short*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x555] = (vu_short)0xAAAAAAAA; + addr[0xAAA] = (vu_short)0x55555555; + addr[0x555] = (vu_short)0x80808080; + addr[0x555] = (vu_short)0xAAAAAAAA; + addr[0xAAA] = (vu_short)0x55555555; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_short *)(info->start[sect]) ; + addr[0] = (vu_short)0x30303030 ; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_short *)(info->start[l_sect]); + while ((addr[0] & 0x8080) != 0x8080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (vu_short *)info->start[0]; + addr[0] = (vu_short)0xF0F0F0F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i<l; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + for (; i<4 && cnt>0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_short *addr = (vu_short *)(info->start[0]); + vu_short sdata; + + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + /* First write upper 16 bits */ + sdata = (short)(data>>16); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x555] = 0xAAAA; + addr[0xAAA] = 0x5555; + addr[0x555] = 0xA0A0; + + *((vu_short *)dest) = sdata; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_short *)dest) & 0x8080) != (sdata & 0x8080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + + /* Now write lower 16 bits */ + sdata = (short)(data&0xffff); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x555] = 0xAAAA; + addr[0xAAA] = 0x5555; + addr[0x555] = 0xA0A0; + + *((vu_short *)dest + 1) = sdata; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_short *)dest + 1) & 0x8080) != (sdata & 0x8080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds new file mode 100644 index 000000000..4db2e4511 --- /dev/null +++ b/board/v37/u-boot.lds @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + +/* + . = env_offset; +*/ + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + + + + + diff --git a/board/v37/v37.c b/board/v37/v37.c new file mode 100644 index 000000000..764aff791 --- /dev/null +++ b/board/v37/v37.c @@ -0,0 +1,218 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Yoo. Jonghoon, IPone, yooth@ipone.co.kr + * PPCboot port on RPXlite board + * + * DRAM related UPMA register values are modified. + * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS + */ + +#include <common.h> +#include "mpc8xx.h" + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (void); + +/* ------------------------------------------------------------------------- */ + +#define MBYTE (1024*1024) +#define DRAM_DELAY 0x00000379 /* DRAM delay count */ +#define _NOT_USED_ 0xFFFFCC25 + +const uint sdram_table[] = +{ + /* single read. (offset 0 in upm RAM) */ + 0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000, + 0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, + + /* burst read. (Offset 8 in upm RAM) */ + 0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000, + 0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* single write. (Offset 0x18 in upm RAM) */ + 0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* burst write. (Offset 0x20 in upm RAM) */ + 0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000, + 0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* Refresh cycle, offset 0x30 */ + 0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* Exception, 0ffset 0x3C */ + 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +}; +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + * Return 1 for now. + * + */ + +int checkboard (void) +{ + printf("Marel V37\n") ; + return (0) ; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long temp; + volatile int delay_cnt; + long int ramsize; + + ramsize = dram_size(); + + /* Refresh clock prescalar */ + memctl->memc_mptpr = 0x400 ; + + if( ramsize == 32*MBYTE ) + temp = 0xd0904110; + else /* 16MB */ + temp = 0xd0802110; + + memctl->memc_mbmr = temp; + + upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + /* Map controller banks 2 to the SDRAM bank */ + memctl->memc_or2 = 0xA00 | (0 - ramsize); + memctl->memc_br2 = 0xC1; + + memctl->memc_mbmr = temp | 0x08; + memctl->memc_mcr = 0x80804130; + + delay_cnt = 0; + while( delay_cnt++ < DRAM_DELAY ) + ; + + /* Run MRS command in location 5-8 of UPMB */ + + memctl->memc_mbmr = temp | 0x04; + memctl->memc_mar = 0x88; + + memctl->memc_mcr = 0x80804105; + + delay_cnt = 0; + while( delay_cnt++ < DRAM_DELAY ) + ; + +#ifdef CONFIG_CAN_DRIVER + /* Initialize OR3 / BR3 */ + memctl->memc_or3 = CFG_OR3_CAN; + memctl->memc_br3 = CFG_BR3_CAN; + + /* Initialize MBMR */ + memctl->memc_mamr = MAMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ + + /* Initialize UPMB for CAN: single read */ + memctl->memc_mdr = 0xFFFFC004; + memctl->memc_mcr = 0x0100 | UPMA; + + memctl->memc_mdr = 0x0FFFD004; + memctl->memc_mcr = 0x0101 | UPMA; + + memctl->memc_mdr = 0x0FFFC000; + memctl->memc_mcr = 0x0102 | UPMA; + + memctl->memc_mdr = 0x3FFFC004; + memctl->memc_mcr = 0x0103 | UPMA; + + memctl->memc_mdr = 0xFFFFDC05; + memctl->memc_mcr = 0x0104 | UPMA; + + /* Initialize UPMB for CAN: single write */ + memctl->memc_mdr = 0xFFFCC004; + memctl->memc_mcr = 0x0118 | UPMA; + + memctl->memc_mdr = 0xCFFCD004; + memctl->memc_mcr = 0x0119 | UPMA; + + memctl->memc_mdr = 0x0FFCC000; + memctl->memc_mcr = 0x011A | UPMA; + + memctl->memc_mdr = 0x7FFCC004; + memctl->memc_mcr = 0x011B | UPMA; + + memctl->memc_mdr = 0xFFFDCC05; + memctl->memc_mcr = 0x011C | UPMA; +#endif /* CONFIG_CAN_DRIVER */ + + return (dram_size()); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Find size of RAM from configuration pins. + * The input pins that contain the memory size are also the debug port + * pins. Normally they are configured as debug port pins. To be able + * to read the memory configuration, we must deactivate the debug port + * and enable the pcmcia input pins. Then return the register to + * previous state. + */ + +static long int dram_size () +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile sysconf8xx_t *siu = &immap->im_siu_conf; + volatile pcmconf8xx_t *pcm = &immap->im_pcmcia; + long int i, memory=1; + unsigned long siu_mcr; + + siu_mcr = siu->sc_siumcr; + siu->sc_siumcr = siu_mcr & 0xFF9FFFFF; + for(i=0; i<10; i++) i = i; + + memory = (pcm->pcmc_pipr>>12) & 0x3; + + siu->sc_siumcr = siu_mcr; + + switch( memory ) + { + case 1: + return( 32*MBYTE ); + case 2: + return( 64*MBYTE ); + default: + break; + } + return( 16*MBYTE ); +} diff --git a/cpu/mpc8xx/lcd.c b/cpu/mpc8xx/lcd.c index dbc38e39d..f6dda607e 100644 --- a/cpu/mpc8xx/lcd.c +++ b/cpu/mpc8xx/lcd.c @@ -43,6 +43,12 @@ #define CONFIG_LCD_LOGO #define LCD_INFO /* Display Logo, (C) and system info */ #endif + +#ifdef CONFIG_V37 +#undef CONFIG_LCD_LOGO +#undef LCD_INFO +#endif + /* #define LCD_TEST_PATTERN */ /* color backgnd for frame/color adjust */ /* #define CFG_INVERT_COLORS */ /* Not needed - adjust vl_dp instead */ /************************************************************************/ @@ -190,6 +196,18 @@ static vidinfo_t panel_info = { /* wbl, vpw, lcdac, wbf */ }; #endif /* CONFIG_SHARP_LQ64D341 */ + +#ifdef CONFIG_SHARP_LQ084V1DG21 +/* + * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan. + */ +static vidinfo_t panel_info = { + 640, 480, 171, 129, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_LOW, + 3, 0, 0, 1, 1, 160, 3, 0, 48 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_SHARP_LQ084V1DG21 */ + /*----------------------------------------------------------------------*/ #ifdef CONFIG_HLD1045 @@ -947,6 +965,13 @@ static void lcd_enable (void) /* Enable the LCD panel */ immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */ lcdp->lcd_lccr |= LCCR_PON; + +#ifdef CONFIG_V37 + /* Turn on display backlight */ + immr->im_cpm.cp_pbpar |= 0x00008000; + immr->im_cpm.cp_pbdir |= 0x00008000; +#endif + #if defined(CONFIG_LWMON) { uchar c = pic_read (0x60); c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */ diff --git a/include/commproc.h b/include/commproc.h index 42db99897..159c294f8 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -1100,6 +1100,34 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */ #endif /* CONFIG_MHPC */ +/*** NETVIA *******************************************************/ + +#if defined(CONFIG_NETVIA) +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC2 use. + */ +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ +#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ + +#define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */ +#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */ + +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ + +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to + * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. + */ +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002f00) + +#endif /* CONFIG_NETVIA */ + /*** RPXCLASSIC *****************************************************/ #ifdef CONFIG_RPXCLASSIC @@ -1309,31 +1337,27 @@ typedef struct scc_enet { # endif /* CONFIG_FEC_ENET */ #endif /* CONFIG_TQM860L, CONFIG_TQM855L */ -#if defined(CONFIG_NETVIA) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. +/*** V37 **********************************************************/ + +#ifdef CONFIG_V37 +/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of + * this may be unique to the Marel V37 configuration. + * Note TENA is on Port B. */ #define PROFF_ENET PROFF_SCC2 #define CPM_CR_ENET CPM_CR_CH_SCC2 #define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ - -#define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */ -#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ +#define PA_ENET_RXD ((ushort)0x0004) +#define PA_ENET_TXD ((ushort)0x0008) +#define PA_ENET_TCLK ((ushort)0x0400) +#define PA_ENET_RCLK ((ushort)0x0200) +#define PB_ENET_TENA ((uint)0x00002000) +#define PC_ENET_CLSN ((ushort)0x0040) +#define PC_ENET_RENA ((ushort)0x0080) -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ #define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002f00) - -#endif /* CONFIG_NETVIA */ +#define SICR_ENET_CLKRT ((uint)0x00002e00) +#endif /* CONFIG_V37 */ /*********************************************************************/ diff --git a/include/configs/v37.h b/include/configs/v37.h new file mode 100644 index 000000000..f5274404a --- /dev/null +++ b/include/configs/v37.h @@ -0,0 +1,381 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ +#define CONFIG_V37 1 /* ...on a Marel V37 board */ + +#define CONFIG_LCD +#define CONFIG_SHARP_LQ084V1DG21 +#undef CONFIG_LCD_LOGO + +/*----------------------------------------------------------------------------- + * I2C Configuration + *----------------------------------------------------------------------------- + */ +#define CONFIG_I2C 1 +#define CFG_I2C_SLAVE 0x2 + +#define CONFIG_8xx_CONS_SMC1 1 +#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */ +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 /* console baudrate = 115kbps */ +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ +#endif + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_BOOTCOMMAND \ + "tftpboot; " \ + "setenv bootargs console=tty0 " \ + "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DATE ) + + +/* Flash banks JFFS2 should use */ +#define CFG_JFFS2_FIRST_BANK 1 +#define CFG_JFFS2_NUM_BANKS 1 + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE0 0x40000000 +#define CFG_FLASH_BASE1 0x60000000 +#define CFG_FLASH_BASE CFG_FLASH_BASE1 + +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE0 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_NVRAM 1 +#define CFG_ENV_ADDR 0x80000000/* Address of Environment */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +#define CFG_ENV_OFFSET 0 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR 0xFFFFFF88 +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) +/* +#define CFG_PISCR (PISCR_PS | PISCR_PITF) +*/ + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + */ +/* up to 50 MHz we use a 1:1 clock */ +#define CFG_PLPRCR ( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS ) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +/* up to 50 MHz we use a 1:1 clock */ +#define CFG_SCCR (SCCR_COM00 | SCCR_TBS) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0x0082000F +/*#define CFG_DER 0*/ + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ + +#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ + +#define CFG_OR_TIMING_FLASH 0xF56 + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V) + +#define CFG_OR5_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR5_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V) + +/* + * BR1 and OR1 (Battery backed SRAM) + */ +#define CFG_BR1_PRELIM 0x80000401 +#define CFG_OR1_PRELIM 0xFFC00736 + +/* + * BR2 and OR2 (SDRAM) + */ +#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB */ + +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* Marel V37 mem setting */ + +#define CFG_BR3_CAN 0xC0000401 +#define CFG_OR3_CAN 0xFFFF0724 + +/* +#define CFG_BR3_PRELIM 0xFA400001 +#define CFG_OR3_PRELIM 0xFFFF8910 +#define CFG_BR4_PRELIM 0xFA000401 +#define CFG_OR4_PRELIM 0xFFFE0970 +*/ + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* + * Refresh clock Prescalar + */ +#define CFG_MPTPR MPTPR_PTP_DIV16 + +/* + * MAMR settings for SDRAM + */ + +/* 10 column SDRAM */ +#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ + MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + + +#endif /* __CONFIG_H */ diff --git a/include/flash.h b/include/flash.h index 3150e3dc3..b4c8bad3d 100644 --- a/include/flash.h +++ b/include/flash.h @@ -111,6 +111,7 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot); #define INTEL_MANUFACT 0x00890089 /* INTEL manuf. ID in D23..D16, D7..D0 */ #define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */ #define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */ +#define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */ /* Micron Technologies (INTEL compat.) */ #define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */ @@ -206,6 +207,9 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot); #define SHARP_ID_28F008SC 0xA6A6A6A6 /* LH28F008SCT-L12 1Mx8, 16 64k blocks */ /* LH28F008SCR-L85 1Mx8, 16 64k blocks */ +#define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ +#define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ + /*----------------------------------------------------------------------- * Internal FLASH identification codes * @@ -301,6 +305,7 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot); #define FLASH_MAN_BM 0x00020000 /* Bright Microelectronics */ #define FLASH_MAN_MX 0x00030000 /* MXIC */ #define FLASH_MAN_STM 0x00040000 +#define FLASH_MAN_TOSH 0x00050000 /* Toshiba */ #define FLASH_MAN_SST 0x00100000 #define FLASH_MAN_INTEL 0x00300000 #define FLASH_MAN_MT 0x00400000 diff --git a/include/version.h b/include/version.h index b501028bd..5249f2a59 100644 --- a/include/version.h +++ b/include/version.h @@ -24,6 +24,6 @@ #ifndef __VERSION_H__ #define __VERSION_H__ -#define U_BOOT_VERSION "U-Boot 0.2.1" +#define U_BOOT_VERSION "U-Boot 0.2.2" #endif /* __VERSION_H__ */ |