diff options
| -rw-r--r-- | board/freescale/mpc8610hpcd/config.mk | 2 | ||||
| -rw-r--r-- | board/trizepsiv/eeprom.c | 1 | ||||
| -rw-r--r-- | cpu/ppc4xx/44x_spd_ddr2.c | 7 | ||||
| -rw-r--r-- | cpu/pxa/start.S | 6 | ||||
| -rw-r--r-- | drivers/net/tsec.c | 6 | ||||
| -rw-r--r-- | drivers/net/tsec.h | 11 | ||||
| -rw-r--r-- | drivers/pcmcia/pxa_pcmcia.c | 8 | ||||
| -rw-r--r-- | drivers/rtc/m41t62.c | 4 | ||||
| -rw-r--r-- | include/asm-arm/io.h | 2 | ||||
| -rw-r--r-- | lib_arm/board.c | 1 | ||||
| -rw-r--r-- | lib_m68k/board.c | 1 | ||||
| -rw-r--r-- | nand_spl/board/amcc/canyonlands/ddr2_fixed.c | 12 | ||||
| -rw-r--r-- | tools/mkimage.c | 22 | 
13 files changed, 46 insertions, 37 deletions
| diff --git a/board/freescale/mpc8610hpcd/config.mk b/board/freescale/mpc8610hpcd/config.mk index 64ac4dcd7..99e7bd479 100644 --- a/board/freescale/mpc8610hpcd/config.mk +++ b/board/freescale/mpc8610hpcd/config.mk @@ -22,4 +22,4 @@  TEXT_BASE = 0xfff00000  PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC8610=1 -maltivec -mabi=altivec -msoft-float -O2 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8610=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c index 3d3bc0022..7a2b90585 100644 --- a/board/trizepsiv/eeprom.c +++ b/board/trizepsiv/eeprom.c @@ -24,7 +24,6 @@  #include <common.h>  #include <command.h> -static unsigned char srom[128];  extern u16 read_srom_word(int);  extern void write_srom_word(int offset, u16 val); diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 5b5de4854..ec76b718b 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -1,7 +1,10 @@  /*   * cpu/ppc4xx/44x_spd_ddr2.c   * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a - * DDR2 controller (non Denali Core). Those are 440SP/SPe. + * DDR2 controller (non Denali Core). Those currently are: + * + * 405:		405EX + * 440/460:	440SP/440SPe/460EX/460GT   *   * (C) Copyright 2007-2008   * Stefan Roese, DENX Software Engineering, sr@denx.de. @@ -2078,7 +2081,7 @@ static void program_bxcf(unsigned long *dimm_populated,  				if (num_banks == 4)  					ind = 0;  				else -					ind = 5; +					ind = 5 << 8;  				switch (num_col_addr) {  				case 0x08:  					mode |= (SDRAM_BXCF_M_AM_0 + ind); diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index 31f408dfa..1cdb7091d 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -166,17 +166,13 @@ _start_armboot: .word start_armboot  /*									    */  /****************************************************************************/  /* mk@tbd: Fix this! */ -#if defined(CONFIG_PXA250) || defined(CONFIG_CPU_MONAHANS) +#undef RCSR  #undef ICMR  #undef OSMR3  #undef OSCR  #undef OWER  #undef OIER -#endif /* CONFIG_PXA250 || CONFIG_CPU_MONAHANS */ -#ifdef CONFIG_PXA250 -#undef RCSR  #undef CCCR -#endif /* CONFIG_PXA250 */  /* Interrupt-Controller base address					    */  IC_BASE:	   .word	   0x40d00000 diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9d22aa38b..f86bfd7ee 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -1277,6 +1277,12 @@ struct phy_info phy_info_VSC8601 = {  				{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},  #ifdef CFG_VSC8601_SKEWFIX  				{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, +if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX) +				{MIIM_EXT_PAGE_ACCESS,1,NULL}, +#define VSC8101_SKEW	(CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12) +				{MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, +				{MIIM_EXT_PAGE_ACCESS,0,NULL}, +#endif  #endif  				{miim_end,}  				 }, diff --git a/drivers/net/tsec.h b/drivers/net/tsec.h index cfa7d1aad..597ea1d3c 100644 --- a/drivers/net/tsec.h +++ b/drivers/net/tsec.h @@ -112,6 +112,8 @@  #define MIIM_GBIT_CONTROL	0x9  #define MIIM_GBIT_CONTROL_INIT	0xe00 +#define MIIM_EXT_PAGE_ACCESS	0x1f +  /* Broadcom BCM54xx -- taken from linux sungem_phy */  #define MIIM_BCM54xx_AUXSTATUS			0x19  #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK	0x0700 @@ -161,8 +163,9 @@  /* Entry for Vitesse VSC8601 regs starts here (Not complete) */  /* Vitesse VSC8601 Extended PHY Control Register 1 */ -#define MIIM_VSC8601_EPHY_CON			0x17 +#define MIIM_VSC8601_EPHY_CON		0x17  #define MIIM_VSC8601_EPHY_CON_INIT_SKEW	0x1120 +#define MIIM_VSC8601_SKEW_CTRL		0x1c  /* 88E1011 PHY Status Register */  #define MIIM_88E1011_PHY_STATUS         0x11 @@ -177,9 +180,9 @@  #define MIIM_88E1011_PHY_MDI_X_AUTO	0x0060  /* 88E1111 PHY LED Control Register */ -#define MIIM_88E1111_PHY_LED_CONTROL   24 -#define MIIM_88E1111_PHY_LED_DIRECT    0x4100 -#define MIIM_88E1111_PHY_LED_COMBINE   0x411C +#define MIIM_88E1111_PHY_LED_CONTROL	24 +#define MIIM_88E1111_PHY_LED_DIRECT	0x4100 +#define MIIM_88E1111_PHY_LED_COMBINE	0x411C  /* 88E1145 Extended PHY Specific Control Register */  #define MIIM_88E1145_PHY_EXT_CR 20 diff --git a/drivers/pcmcia/pxa_pcmcia.c b/drivers/pcmcia/pxa_pcmcia.c index 6020e4628..65427efdb 100644 --- a/drivers/pcmcia/pxa_pcmcia.c +++ b/drivers/pcmcia/pxa_pcmcia.c @@ -35,8 +35,10 @@ int pcmcia_on (void)  	debug ("%s\n", __FUNCTION__);  	i = 0; -	while (reg_arr[i]) -		*((volatile unsigned int *) reg_arr[i++]) |= reg_arr[i++]; +	while (reg_arr[i]) { +		(*(volatile unsigned int *) reg_arr[i]) |= reg_arr[i + 1]; +		i += 2; +	}  	udelay (1000);  	debug ("%s: programmed mem controller \n", __FUNCTION__); @@ -44,7 +46,7 @@ int pcmcia_on (void)  #ifdef CONFIG_EXADRON1  /*define useful BCR masks */ -#define BCR_CF_INIT_VAL  		    0x00007230 +#define BCR_CF_INIT_VAL			    0x00007230  #define BCR_CF_PWRON_BUSOFF_RESETOFF_VAL    0x00007231  #define BCR_CF_PWRON_BUSOFF_RESETON_VAL     0x00007233  #define BCR_CF_PWRON_BUSON_RESETON_VAL      0x00007213 diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index cf2a9574a..89d4ccdb2 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -81,7 +81,7 @@ int rtc_get(struct rtc_time *tm)  	tm->tm_hour = BCD2BIN(buf[M41T62_REG_HOUR] & 0x3f);  	tm->tm_mday = BCD2BIN(buf[M41T62_REG_DAY] & 0x3f);  	tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07; -	tm->tm_mon = BCD2BIN(buf[M41T62_REG_MON] & 0x1f) - 1; +	tm->tm_mon = BCD2BIN(buf[M41T62_REG_MON] & 0x1f);  	/* assume 20YY not 19YY, and ignore the Century Bit */  	/* U-Boot needs to add 1900 here */ @@ -119,7 +119,7 @@ void rtc_set(struct rtc_time *tm)  	buf[M41T62_REG_DAY] =  		BIN2BCD(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f);  	buf[M41T62_REG_MON] = -		BIN2BCD(tm->tm_mon + 1) | (buf[M41T62_REG_MON] & ~0x1f); +		BIN2BCD(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f);  	/* assume 20YY not 19YY */  	buf[M41T62_REG_YEAR] = BIN2BCD(tm->tm_year % 100); diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index c33b9e8d3..f4ae30700 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -123,7 +123,7 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);   * only.  Their primary purpose is to access PCI and ISA peripherals.   *   * Note that for a big endian machine, this implies that the following - * big endian mode connectivity is in place, as described by numerious + * big endian mode connectivity is in place, as described by numerous   * ARM documents:   *   *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31 diff --git a/lib_arm/board.c b/lib_arm/board.c index 22d573a39..67506b35e 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -44,6 +44,7 @@  #include <devices.h>  #include <version.h>  #include <net.h> +#include <serial.h>  #ifdef CONFIG_DRIVER_SMC91111  #include "../drivers/net/smc91111.h" diff --git a/lib_m68k/board.c b/lib_m68k/board.c index 915920641..6654f971b 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -45,6 +45,7 @@  #include <status_led.h>  #endif  #include <net.h> +#include <serial.h>  #if defined(CONFIG_CMD_BEDBUG)  #include <cmd_bedbug.h>  #endif diff --git a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c index 79f3b0f42..9010fca15 100644 --- a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c +++ b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c @@ -49,20 +49,21 @@ long int initdram(int board_type)  	 * enabled. This will only work for the same memory  	 * configuration as used here:  	 * -	 * Crucial CT6464AC53E.4FE - 512MB SO-DIMM +	 * Crucial CT6464AC667.8FB - 512MB SO-DIMM  	 *  	 */  	mtsdram(SDRAM_MCOPT2, 0x00000000); -	mtsdram(SDRAM_MCOPT1, 0x05322000); +	mtsdram(SDRAM_MCOPT1, 0x05122000);  	mtsdram(SDRAM_MODT0, 0x01000000); -	mtsdram(SDRAM_CODT, 0x00800021); +	mtsdram(SDRAM_CODT, 0x02800021);  	mtsdram(SDRAM_WRDTR, 0x82000823);  	mtsdram(SDRAM_CLKTR, 0x40000000);  	mtsdram(SDRAM_MB0CF, 0x00000201); +	mtsdram(SDRAM_MB1CF, 0x00000201);  	mtsdram(SDRAM_RTR, 0x06180000);  	mtsdram(SDRAM_SDTR1, 0x80201000);  	mtsdram(SDRAM_SDTR2, 0x42103243); -	mtsdram(SDRAM_SDTR3, 0x0A0D0D1A); +	mtsdram(SDRAM_SDTR3, 0x0A0D0D16);  	mtsdram(SDRAM_MMODE, 0x00000632);  	mtsdram(SDRAM_MEMODE, 0x00000040);  	mtsdram(SDRAM_INITPLR0, 0xB5380000); @@ -86,7 +87,8 @@ long int initdram(int board_type)  	wait_init_complete(); -	mtdcr(SDRAM_R0BAS, 0x0000F000);		/* MQ0_B0BAS */ +	mtdcr(SDRAM_R0BAS, 0x0000F800);		/* MQ0_B0BAS */ +	mtdcr(SDRAM_R1BAS, 0x0400F800);		/* MQ0_B1BAS */  	mtsdram(SDRAM_RDCC, 0x40000000);  	mtsdram(SDRAM_RQDC, 0x80000038); diff --git a/tools/mkimage.c b/tools/mkimage.c index ea7a826f8..967fe9a77 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -28,7 +28,7 @@  extern int errno;  #ifndef MAP_FAILED -#define MAP_FAILED (-1) +#define MAP_FAILED (void *)(-1)  #endif  extern	unsigned long	crc32 (unsigned long crc, const char *buf, unsigned int len); @@ -218,9 +218,8 @@ NXTARG:		;  			exit (EXIT_FAILURE);  		} -		ptr = (unsigned char *)mmap(0, sbuf.st_size, -					    PROT_READ, MAP_SHARED, ifd, 0); -		if ((caddr_t)ptr == (caddr_t)-1) { +		ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, ifd, 0); +		if (ptr == MAP_FAILED) {  			fprintf (stderr, "%s: Can't read %s: %s\n",  				cmdname, imagefile, strerror(errno));  			exit (EXIT_FAILURE); @@ -330,9 +329,8 @@ NXTARG:		;  		exit (EXIT_FAILURE);  	} -	ptr = (unsigned char *)mmap(0, sbuf.st_size, -				    PROT_READ|PROT_WRITE, MAP_SHARED, ifd, 0); -	if (ptr == (unsigned char *)MAP_FAILED) { +	ptr = mmap(0, sbuf.st_size, PROT_READ|PROT_WRITE, MAP_SHARED, ifd, 0); +	if (ptr == MAP_FAILED) {  		fprintf (stderr, "%s: Can't map %s: %s\n",  			cmdname, imagefile, strerror(errno));  		exit (EXIT_FAILURE); @@ -410,9 +408,8 @@ copy_file (int ifd, const char *datafile, int pad)  		exit (EXIT_FAILURE);  	} -	ptr = (unsigned char *)mmap(0, sbuf.st_size, -				    PROT_READ, MAP_SHARED, dfd, 0); -	if (ptr == (unsigned char *)MAP_FAILED) { +	ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, dfd, 0); +	if (ptr == MAP_FAILED) {  		fprintf (stderr, "%s: Can't read %s: %s\n",  			cmdname, datafile, strerror(errno));  		exit (EXIT_FAILURE); @@ -594,9 +591,8 @@ static void fit_handle_file (void)  		exit (EXIT_FAILURE);  	} -	ptr = (unsigned char *)mmap (0, sbuf.st_size, -			PROT_READ|PROT_WRITE, MAP_SHARED, tfd, 0); -	if ((caddr_t)ptr == (caddr_t)-1) { +	ptr = mmap (0, sbuf.st_size, PROT_READ|PROT_WRITE, MAP_SHARED, tfd, 0); +	if (ptr == MAP_FAILED) {  		fprintf (stderr, "%s: Can't read %s: %s\n",  				cmdname, tmpfile, strerror(errno));  		unlink (tmpfile); |