diff options
| -rw-r--r-- | board/freescale/mpc8610hpcd/Makefile | 10 | ||||
| -rw-r--r-- | board/freescale/mpc8610hpcd/ddr.c | 79 | ||||
| -rw-r--r-- | board/freescale/mpc8610hpcd/mpc8610hpcd.c | 3 | ||||
| -rw-r--r-- | include/configs/MPC8610HPCD.h | 43 |
4 files changed, 106 insertions, 29 deletions
diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile index a457c32e8..930a2063a 100644 --- a/board/freescale/mpc8610hpcd/Makefile +++ b/board/freescale/mpc8610hpcd/Makefile @@ -23,14 +23,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_FSL_DDR2) += ddr.o +COBJS-y += law.o COBJS-${CONFIG_FSL_DIU_FB} += mpc8610hpcd_diu.o -COBJS += ${COBJS-y} - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c new file mode 100644 index 000000000..2d22da177 --- /dev/null +++ b/board/freescale/mpc8610hpcd/ddr.c @@ -0,0 +1,79 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> + +static void +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_bus_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS1; + } + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 10; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index ff1b892b5..c9dde4d1a 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -26,6 +26,7 @@ #include <asm/processor.h> #include <asm/immap_86xx.h> #include <asm/immap_fsl_pci.h> +#include <asm/fsl_ddr_sdram.h> #include <i2c.h> #include <asm/io.h> #include <libfdt.h> @@ -122,7 +123,7 @@ initdram(int board_type) long dram_size = 0; #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram(); + dram_size = fsl_ddr_sdram(); #else dram_size = fixed_sdram(); #endif diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index e9371a2f3..0c1c4fc7c 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -8,7 +8,6 @@ /* * MPC8610HPCD board configuration file - * */ #ifndef __CONFIG_H @@ -45,14 +44,6 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE - -#define CONFIG_SPD_EEPROM /* Use SPD for DDR */ -#undef CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ @@ -89,25 +80,28 @@ #define CFG_DIU_ADDR (CFG_CCSRBAR+0x2c000) -/* - * DDR Setup - */ +/* DDR Setup */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SPD_EEPROM /* Use SPD for DDR */ +#define CONFIG_DDR_SPD + +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE #define CONFIG_VERY_BIG_RAM #define MPC86xx_DDR_SDRAM_CLK_CNTL -#if defined(CONFIG_SPD_EEPROM) -/* - * Determine DDR configuration from I2C interface. - */ -#define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ -#else -/* - * Manually set up DDR1 parameters - */ +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ +/* These are used when DDR doesn't use SPD. */ #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ #if 0 /* TODO */ @@ -130,7 +124,10 @@ #define CFG_DDR_ERR_INT_EN 0x00000000 #define CFG_DDR_ERR_DIS 0x00000000 #define CFG_DDR_SBE 0x000f0000 - /* Not used in fixed_sdram function */ + +/* + * FIXME: Not used in fixed_sdram function + */ #define CFG_DDR_MODE 0x00000022 #define CFG_DDR_CS1_BNDS 0x00000000 #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ @@ -138,7 +135,7 @@ #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ #endif -#endif + #define CONFIG_ID_EEPROM #define CFG_I2C_EEPROM_NXID |