diff options
175 files changed, 5338 insertions, 1338 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 36b47b741..28c052d7a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1203,6 +1203,7 @@ Mark Jonas <mark.jonas@de.bosch.com> Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> MS7720SE SH7720 + R0P77520000RZ SH7752 R0P77570030RL SH7757 R0P77850011RL SH7785 @@ -24,7 +24,7 @@ VERSION = 2013 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else @@ -869,7 +869,7 @@ clobber: tidy @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map} @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map} @rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst} - @rm -f $(obj)MLO + @rm -f $(obj)MLO MLO.byteswap @rm -f $(obj)SPL @rm -f $(obj)tools/xway-swap-bytes @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c @@ -616,6 +616,14 @@ The following options need to be configured: boot loader that has already initialized the UART. Define this variable to flush the UART at init time. + CONFIG_SYS_NS16550_BROKEN_TEMT + + 16550 UART set the Transmitter Empty (TEMT) Bit when all output + has finished and the transmitter is totally empty. U-Boot waits + for this bit to be set to initialize the serial console. On some + broken platforms this bit is not set in SPL making U-Boot to + hang while waiting for TEMT. Define this option to avoid it. + - Console Interface: Depending on board, define exactly one serial port @@ -849,6 +857,7 @@ The following options need to be configured: CONFIG_CMD_LOADS loads CONFIG_CMD_MD5SUM print md5 message digest (requires CONFIG_CMD_MEMORY and CONFIG_MD5) + CONFIG_CMD_MEMINFO * Display detailed memory information CONFIG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base, loop, loopw, mtest CONFIG_CMD_MISC Misc functions like sleep etc @@ -2378,6 +2387,15 @@ CBFS (Coreboot Filesystem) support run-time determined information about the hardware to the environment. These will be named board_name, board_rev. + CONFIG_DELAY_ENVIRONMENT + + Normally the environment is loaded when the board is + intialised so that it is available to U-Boot. This inhibits + that so that the environment is not available until + explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL + this is instead controlled by the value of + /config/load-environment. + - DataFlash Support: CONFIG_HAS_DATAFLASH @@ -2404,6 +2422,11 @@ CBFS (Coreboot Filesystem) support CONFIG_SF_DEFAULT_MODE (see include/spi.h) CONFIG_SF_DEFAULT_SPEED in Hz + CONFIG_CMD_SF_TEST + + Define this option to include a destructive SPI flash + test ('sf test'). + - SystemACE Support: CONFIG_SYSTEMACE @@ -3448,6 +3471,16 @@ use the "saveenv" command to store a valid environment. space for already greatly restricted images, including but not limited to NAND_SPL configurations. +- CONFIG_DISPLAY_BOARDINFO + Display information about the board that U-Boot is running on + when U-Boot starts up. The board function checkboard() is called + to do this. + +- CONFIG_DISPLAY_BOARDINFO_LATE + Similar to the previous option, but display this information + later, once stdio is running and output goes to the LCD, if + present. + Low Level (hardware related) configuration options: --------------------------------------------------- diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 5d3b4c229..a067b8a18 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -165,13 +165,7 @@ next: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -188,14 +182,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -245,7 +235,15 @@ fixnext: add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop - b clear_bss + bx lr + +#endif + +relocate_done: + + bx lr + +#ifndef CONFIG_SPL_BUILD _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -253,54 +251,13 @@ _rel_dyn_end_ofs: .word __rel_dyn_end - _start _dynsym_start_ofs: .word __dynsym_start - _start -#endif -clear_bss: -#ifdef CONFIG_SPL_BUILD - /* No relocation for SPL */ - ldr r0, =__bss_start - ldr r1, =__bss_end__ -#else - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 #endif - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_NAND_SPL - ldr r0, _nand_boot_ofs - mov pc, r0 -_nand_boot_ofs: - .word nand_boot -#else -jump_2_ram: - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: -_board_init_r_ofs: - .word board_init_r - _start -#endif + bx lr /* ************************************************************************* diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 667a0e0c4..40df4b161 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -224,12 +224,7 @@ skip_tcmdisable: */ bl lowlevel_init /* go setup pll,mux,memory */ -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -246,14 +241,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -343,49 +334,9 @@ mmu_enable: skip_hw_init: #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: -#ifndef CONFIG_NAND_SPL - bl coloured_LED_init - bl red_led_on -#endif -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_NAND_SPL - ldr pc, _nand_boot - -_nand_boot: .word nand_boot -#else - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr +relocate_done: -_board_init_r_ofs: - .word board_init_r - _start -#endif + bx lr _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -399,6 +350,11 @@ _mmu_table_base: .word mmu_table #endif + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + mov pc, lr + #ifndef CONFIG_NAND_SPL /* * we assume that cache operation is done before. (eg. cleanup_before_linux()) diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index c2a7763ff..771d3869c 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -147,12 +147,7 @@ reset: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -169,14 +164,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -228,43 +219,10 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: +relocate_done: - bl coloured_LED_init - bl red_led_on -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ mov pc, lr -_board_init_r_ofs: - .word board_init_r - _start - _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: @@ -272,6 +230,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + mov pc, lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 14c9156c0..511d21d33 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -182,12 +182,7 @@ copyex: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -204,14 +199,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -263,51 +254,10 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: - - bl coloured_LED_init - bl red_led_on -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_NAND_SPL - ldr r0, _nand_boot_ofs - mov pc, r0 +relocate_done: -_nand_boot_ofs: - .word nand_boot -#else - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ mov pc, lr -_board_init_r_ofs: - .word board_init_r - _start -#endif - _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: @@ -315,6 +265,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + mov pc, lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index 3a483f6ca..e8d6d71c1 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -34,10 +34,6 @@ #include <config.h> #include <version.h> -#if defined(CONFIG_OMAP1510) -#include <./configs/omap1510.h> -#endif - /* ************************************************************************* * @@ -176,12 +172,7 @@ poll1: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -198,14 +189,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -257,51 +244,10 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: - - bl coloured_LED_init - bl red_led_on -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_NAND_SPL - ldr r0, _nand_boot_ofs - mov pc, r0 +relocate_done: -_nand_boot_ofs: - .word nand_boot -#else - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ mov pc, lr -_board_init_r_ofs: - .word board_init_r - _start -#endif - _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: @@ -309,6 +255,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + mov pc, lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c index 93485523b..0448c0b13 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c @@ -193,6 +193,19 @@ void at91_spi1_hw_init(unsigned long cs_mask) } #endif +#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI) +void at91_uhp_hw_init(void) +{ + /* Enable VBus on UHP ports */ + at91_set_pio_output(AT91_PIO_PORTD, 18, 0); /* port A */ + at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* port B */ +#if defined(CONFIG_USB_OHCI_NEW) + /* port C is OHCI only */ + at91_set_pio_output(AT91_PIO_PORTD, 20, 0); /* port C */ +#endif +} +#endif + #ifdef CONFIG_MACB void at91_macb_hw_init(void) { diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.c b/arch/arm/cpu/arm926ejs/davinci/reset.c index 968fb035c..80f1ce9d3 100644 --- a/arch/arm/cpu/arm926ejs/davinci/reset.c +++ b/arch/arm/cpu/arm926ejs/davinci/reset.c @@ -16,7 +16,7 @@ void reset_cpu(unsigned long a) { struct davinci_timer *const wdttimer = - (struct davinci_timer *)DAVINCI_TIMER1_BASE; + (struct davinci_timer *)DAVINCI_WDOG_BASE; writel(0x08, &wdttimer->tgcr); writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr); writel(0, &wdttimer->tim12); diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c index 03eb2de52..0ba6f098c 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c @@ -31,7 +31,7 @@ static u32 kirkwood_variant(void) #define MPP_CTRL(i) (KW_MPP_BASE + (i* 4)) #define MPP_NR_REGS (1 + MPP_MAX/8) -void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save) +void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save) { u32 mpp_ctrl[MPP_NR_REGS]; unsigned int variant_mask; diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 2188f7e35..66a8b654b 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -36,12 +36,6 @@ #include <common.h> #include <version.h> -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#elif defined(CONFIG_OMAP730) -#include <./configs/omap730.h> -#endif - /* ************************************************************************* * @@ -198,20 +192,7 @@ reset: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: -#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) -#else -#ifdef CONFIG_SPL_BUILD - ldr sp, =(CONFIG_SPL_STACK) -#else - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) -#endif -#endif - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -229,15 +210,11 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start sub r9, r6, r0 /* r9 <- relocation offset */ cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + moveq r9, #0 /* no relocation. offset(r9) = 0 */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -289,56 +266,9 @@ fixnext: blo fixloop #endif -clear_bss: -#ifdef CONFIG_SPL_BUILD - /* No relocation for SPL */ - ldr r0, =__bss_start - ldr r1, =__bss_end__ -#else - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 -#endif - mov r2, #0x00000000 /* clear */ +relocate_done: -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: - -#ifndef CONFIG_SPL_BUILD - bl coloured_LED_init - bl red_led_on -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_NAND_SPL - ldr r0, _nand_boot_ofs - mov pc, r0 - -_nand_boot_ofs: - .word nand_boot -#else - ldr r0, _board_init_r_ofs - ldr r1, _TEXT_BASE - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr - -_board_init_r_ofs: - .word board_init_r - _start -#endif + bx lr _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -346,8 +276,14 @@ _rel_dyn_end_ofs: .word __rel_dyn_end - _start _dynsym_start_ofs: .word __dynsym_start - _start + #endif + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + bx lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 30e21835c..a7a98a4e5 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -147,12 +147,7 @@ reset: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -169,14 +164,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -228,46 +219,10 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_NAND_SPL - ldr pc, _nand_boot +relocate_done: -_nand_boot: .word nand_boot -#else - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ mov pc, lr -_board_init_r_ofs: - .word board_init_r - _start -#endif - _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: @@ -275,6 +230,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + mov pc, lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index a133d19bc..c189849fa 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -143,12 +143,7 @@ reset: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -165,14 +160,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -224,50 +215,9 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: - - bl coloured_LED_init - bl red_led_on -#endif +relocate_done: -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_NAND_SPL - ldr r0, _nand_boot_ofs - mov pc, r0 - -_nand_boot_ofs: - .word nand_boot -#else - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr - -_board_init_r_ofs: - .word board_init_r - _start -#endif + bx lr _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -276,6 +226,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + mov pc, lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index 74875b325..70c443edb 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -18,10 +18,12 @@ LIB = $(obj)lib$(SOC).o COBJS += clock.o COBJS += sys_info.o +COBJS += mem.o COBJS += ddr.o COBJS += emif4.o COBJS += board.o COBJS += mux.o +COBJS-$(CONFIG_NAND_OMAP_GPMC) += elm.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index da5bc7318..ab313265d 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -25,6 +25,7 @@ #include <asm/arch/ddr_defs.h> #include <asm/arch/clock.h> #include <asm/arch/gpio.h> +#include <asm/arch/mem.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 0b4cb4e52..d7d98d111 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -151,6 +151,16 @@ static void enable_per_clocks(void) ; #endif /* CONFIG_SERIAL6 */ + /* GPMC */ + writel(PRCM_MOD_EN, &cmper->gpmcclkctrl); + while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN) + ; + + /* ELM */ + writel(PRCM_MOD_EN, &cmper->elmclkctrl); + while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN) + ; + /* MMC0*/ writel(PRCM_MOD_EN, &cmper->mmc0clkctrl); while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN) diff --git a/arch/arm/cpu/armv7/am33xx/elm.c b/arch/arm/cpu/armv7/am33xx/elm.c new file mode 100644 index 000000000..9eed23d75 --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/elm.c @@ -0,0 +1,212 @@ +/* + * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com> + * Mansoor Ahamed <mansoor.ahamed@ti.com> + * + * BCH Error Location Module (ELM) support. + * + * NOTE: + * 1. Supports only continuous mode. Dont see need for page mode in uboot + * 2. Supports only syndrome polynomial 0. i.e. poly local variable is + * always set to ELM_DEFAULT_POLY. Dont see need for other polynomial + * sets in uboot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/cpu.h> +#include <asm/arch/omap_gpmc.h> +#include <asm/arch/elm.h> + +#define ELM_DEFAULT_POLY (0) + +struct elm *elm_cfg; + +/** + * elm_load_syndromes - Load BCH syndromes based on nibble selection + * @syndrome: BCH syndrome + * @nibbles: + * @poly: Syndrome Polynomial set to use + * + * Load BCH syndromes based on nibble selection + */ +static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) +{ + u32 *ptr; + u32 val; + + /* reg 0 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0]; + val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) | + (syndrome[3] << 24); + writel(val, ptr); + /* reg 1 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1]; + val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) | + (syndrome[7] << 24); + writel(val, ptr); + + /* BCH 8-bit with 26 nibbles (4*8=32) */ + if (nibbles > 13) { + /* reg 2 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2]; + val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) | + (syndrome[11] << 24); + writel(val, ptr); + /* reg 3 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3]; + val = syndrome[12] | (syndrome[13] << 8) | + (syndrome[14] << 16) | (syndrome[15] << 24); + writel(val, ptr); + } + + /* BCH 16-bit with 52 nibbles (7*8=56) */ + if (nibbles > 26) { + /* reg 4 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4]; + val = syndrome[16] | (syndrome[17] << 8) | + (syndrome[18] << 16) | (syndrome[19] << 24); + writel(val, ptr); + + /* reg 5 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5]; + val = syndrome[20] | (syndrome[21] << 8) | + (syndrome[22] << 16) | (syndrome[23] << 24); + writel(val, ptr); + + /* reg 6 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]; + val = syndrome[24] | (syndrome[25] << 8) | + (syndrome[26] << 16) | (syndrome[27] << 24); + writel(val, ptr); + } +} + +/** + * elm_check_errors - Check for BCH errors and return error locations + * @syndrome: BCH syndrome + * @nibbles: + * @error_count: Returns number of errrors in the syndrome + * @error_locations: Returns error locations (in decimal) in this array + * + * Check the provided syndrome for BCH errors and return error count + * and locations in the array passed. Returns -1 if error is not correctable, + * else returns 0 + */ +int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, + u32 *error_locations) +{ + u8 poly = ELM_DEFAULT_POLY; + s8 i; + u32 location_status; + + elm_load_syndromes(syndrome, nibbles, poly); + + /* start processing */ + writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]) + | ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID), + &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]); + + /* wait for processing to complete */ + while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1) + ; + /* clear status */ + writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)), + &elm_cfg->irqstatus); + + /* check if correctable */ + location_status = readl(&elm_cfg->error_location[poly].location_status); + if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK)) + return -1; + + /* get error count */ + *error_count = readl(&elm_cfg->error_location[poly].location_status) & + ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK; + + for (i = 0; i < *error_count; i++) { + error_locations[i] = + readl(&elm_cfg->error_location[poly].error_location_x[i]); + } + + return 0; +} + + +/** + * elm_config - Configure ELM module + * @level: 4 / 8 / 16 bit BCH + * + * Configure ELM module based on BCH level. + * Set mode as continuous mode. + * Currently we are using only syndrome 0 and syndromes 1 to 6 are not used. + * Also, the mode is set only for syndrome 0 + */ +int elm_config(enum bch_level level) +{ + u32 val; + u8 poly = ELM_DEFAULT_POLY; + u32 buffer_size = 0x7FF; + + /* config size and level */ + val = (u32)(level) & ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK; + val |= ((buffer_size << ELM_LOCATION_CONFIG_ECC_SIZE_POS) & + ELM_LOCATION_CONFIG_ECC_SIZE_MASK); + writel(val, &elm_cfg->location_config); + + /* config continous mode */ + /* enable interrupt generation for syndrome polynomial set */ + writel((readl(&elm_cfg->irqenable) | (0x1 << poly)), + &elm_cfg->irqenable); + /* set continuous mode for the syndrome polynomial set */ + writel((readl(&elm_cfg->page_ctrl) & ~(0x1 << poly)), + &elm_cfg->page_ctrl); + + return 0; +} + +/** + * elm_reset - Do a soft reset of ELM + * + * Perform a soft reset of ELM and return after reset is done. + */ +void elm_reset(void) +{ + /* initiate reset */ + writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET), + &elm_cfg->sysconfig); + + /* wait for reset complete and normal operation */ + while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) != + ELM_SYSSTATUS_RESETDONE) + ; +} + +/** + * elm_init - Initialize ELM module + * + * Initialize ELM support. Currently it does only base address init + * and ELM reset. + */ +void elm_init(void) +{ + elm_cfg = (struct elm *)ELM_BASE; + elm_reset(); +} diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c new file mode 100644 index 000000000..b8f54abae --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Author : + * Mansoor Ahamed <mansoor.ahamed@ti.com> + * + * Initial Code from: + * Manikandan Pillai <mani.pillai@ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <command.h> + +struct gpmc *gpmc_cfg; + +#if defined(CONFIG_CMD_NAND) +static const u32 gpmc_m_nand[GPMC_MAX_REG] = { + M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, 0 +}; +#endif + + +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, + u32 size) +{ + writel(0, &cs->config7); + sdelay(1000); + /* Delay for settling */ + writel(gpmc_config[0], &cs->config1); + writel(gpmc_config[1], &cs->config2); + writel(gpmc_config[2], &cs->config3); + writel(gpmc_config[3], &cs->config4); + writel(gpmc_config[4], &cs->config5); + writel(gpmc_config[5], &cs->config6); + /* Enable the config */ + writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), &cs->config7); + sdelay(2000); +} + +/***************************************************** + * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode (SDRAM in x32). + * This code can only be executed from SRAM or SDRAM. + *****************************************************/ +void gpmc_init(void) +{ + /* putting a blanket check on GPMC based on ZeBu for now */ + gpmc_cfg = (struct gpmc *)GPMC_BASE; + +#ifdef CONFIG_CMD_NAND + const u32 *gpmc_config = NULL; + u32 base = 0; + u32 size = 0; +#endif + /* global settings */ + writel(0x00000008, &gpmc_cfg->sysconfig); + writel(0x00000100, &gpmc_cfg->irqstatus); + writel(0x00000200, &gpmc_cfg->irqenable); + writel(0x00000012, &gpmc_cfg->config); + /* + * Disable the GPMC0 config set by ROM code + */ + writel(0, &gpmc_cfg->cs[0].config7); + sdelay(1000); + +#ifdef CONFIG_CMD_NAND + gpmc_config = gpmc_m_nand; + + base = PISMO1_NAND_BASE; + size = PISMO1_NAND_SIZE; + enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); +#endif +} diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 1f2fa027c..0efc80dde 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -25,9 +25,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)libomap-common.o -SOBJS := reset.o - -COBJS := timer.o +COBJS := reset.o +COBJS += timer.o COBJS += utils.o ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 0f19141cc..2b584e0a5 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -21,6 +21,7 @@ #include <asm/omap_common.h> #include <asm/arch/omap.h> #include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> /* * This is used to verify if the configuration header diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 30dcf1b0b..88253cf8c 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -33,6 +33,8 @@ #include <asm/utils.h> #include <linux/compiler.h> +static int emif1_enabled = -1, emif2_enabled = -1; + void set_lpmode_selfrefresh(u32 base) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; @@ -1109,6 +1111,7 @@ void emif_post_init_config(u32 base) void dmm_init(u32 base) { const struct dmm_lisa_map_regs *lisa_map_regs; + u32 i, section, valid; #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS emif_get_dmm_regs(&lisa_map_regs); @@ -1216,6 +1219,29 @@ void dmm_init(u32 base) writel(lisa_map_regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); } + + /* + * EMIF should be configured only when + * memory is mapped on it. Using emif1_enabled + * and emif2_enabled variables for this. + */ + emif1_enabled = 0; + emif2_enabled = 0; + for (i = 0; i < 4; i++) { + section = __raw_readl(DMM_BASE + i*4); + valid = (section & EMIF_SDRC_MAP_MASK) >> + (EMIF_SDRC_MAP_SHIFT); + if (valid == 3) { + emif1_enabled = 1; + emif2_enabled = 1; + break; + } else if (valid == 1) { + emif1_enabled = 1; + } else if (valid == 2) { + emif2_enabled = 1; + } + } + } /* @@ -1255,15 +1281,20 @@ void sdram_init(void) writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl); } - do_sdram_init(EMIF1_BASE); - do_sdram_init(EMIF2_BASE); - if (!in_sdram) dmm_init(DMM_BASE); + if (emif1_enabled) + do_sdram_init(EMIF1_BASE); + + if (emif2_enabled) + do_sdram_init(EMIF2_BASE); + if (!(in_sdram || warm_reset())) { - emif_post_init_config(EMIF1_BASE); - emif_post_init_config(EMIF2_BASE); + if (emif1_enabled) + emif_post_init_config(EMIF1_BASE); + if (emif2_enabled) + emif_post_init_config(EMIF2_BASE); } /* for the shadow registers to take effect */ diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index f3cd81ad9..89c587e31 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -478,7 +478,7 @@ void omap3_outer_cache_disable(void) */ omap3_update_aux_cr(0, 0x2); } -#endif +#endif /* !CONFIG_SYS_L2CACHE_OFF */ #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) @@ -486,4 +486,4 @@ void enable_caches(void) /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } -#endif +#endif /* !CONFIG_SYS_DCACHE_OFF */ diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c index 2fe5ac7c3..d04a5a10d 100644 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ b/arch/arm/cpu/armv7/omap3/mem.c @@ -42,14 +42,7 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG5, M_NAND_GPMC_CONFIG6, 0 }; - -#if defined(CONFIG_ENV_IS_IN_NAND) -#define GPMC_CS 0 -#else -#define GPMC_CS 1 -#endif - -#endif +#endif /* CONFIG_CMD_NAND */ #if defined(CONFIG_CMD_ONENAND) static const u32 gpmc_onenand[GPMC_MAX_REG] = { @@ -60,14 +53,7 @@ static const u32 gpmc_onenand[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG5, ONENAND_GPMC_CONFIG6, 0 }; - -#if defined(CONFIG_ENV_IS_IN_ONENAND) -#define GPMC_CS 0 -#else -#define GPMC_CS 1 -#endif - -#endif +#endif /* CONFIG_CMD_ONENAND */ /******************************************************** * mem_ok() - test used to see if timings are correct diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index f6d9b97bb..e32bf118b 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -113,18 +113,18 @@ u32 get_sdr_cs_offset(u32 cs) * - Test CS to make sure it's OK for use */ static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, - u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr) + struct board_sdrc_timings *timings) { /* Setup timings we got from the board. */ - writel(mcfg, &sdrc_base->cs[cs].mcfg); - writel(ctrla, &sdrc_actim_base->ctrla); - writel(ctrlb, &sdrc_actim_base->ctrlb); - writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); + writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); + writel(timings->ctrla, &sdrc_actim_base->ctrla); + writel(timings->ctrlb, &sdrc_actim_base->ctrlb); + writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); writel(CMD_NOP, &sdrc_base->cs[cs].manual); writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(mr, &sdrc_base->cs[cs].mr); + writel(timings->mr, &sdrc_base->cs[cs].mr); /* * Test ram in this bank @@ -143,7 +143,7 @@ static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, void do_sdrc_init(u32 cs, u32 early) { struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1; - u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr; + struct board_sdrc_timings timings; sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; @@ -158,7 +158,7 @@ void do_sdrc_init(u32 cs, u32 early) * setup CS1. */ #ifdef CONFIG_SPL_BUILD - get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr); + get_board_mem_timings(&timings); #endif if (early) { /* reset sdrc controller */ @@ -177,11 +177,9 @@ void do_sdrc_init(u32 cs, u32 early) writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); #ifdef CONFIG_SPL_BUILD - write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb, - rfr_ctrl, mr); + write_sdrc_timings(CS0, sdrc_actim_base0, &timings); make_cs1_contiguous(); - write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb, - rfr_ctrl, mr); + write_sdrc_timings(CS1, sdrc_actim_base1, &timings); #endif } @@ -193,14 +191,12 @@ void do_sdrc_init(u32 cs, u32 early) * so we may be asked now to setup CS1. */ if (cs == CS1) { - mcfg = readl(&sdrc_base->cs[CS0].mcfg), - rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); - ctrla = readl(&sdrc_actim_base0->ctrla), - ctrlb = readl(&sdrc_actim_base0->ctrlb); - mr = readl(&sdrc_base->cs[CS0].mr); - write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb, - rfr_ctrl, mr); - + timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg), + timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); + timings.ctrla = readl(&sdrc_actim_base0->ctrla); + timings.ctrlb = readl(&sdrc_actim_base0->ctrlb); + timings.mr = readl(&sdrc_base->cs[CS0].mr); + write_sdrc_timings(cs, sdrc_actim_base1, &timings); } } diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 5bd0a88fd..12c58033d 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -44,7 +44,7 @@ */ #define printf(fmt, args...) #define puts(s) -#endif +#endif /* !CONFIG_SPL_BUILD */ struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100; diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 2c34e48f4..f4123aaff 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -116,7 +116,7 @@ void do_io_settings(void) if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_2)) writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2); } -#endif +#endif /* CONFIG_SPL_BUILD */ /* dummy fuction for omap4 */ void config_data_eye_leveling_samples(u32 emif_base) @@ -182,4 +182,4 @@ void v7_outer_cache_disable(void) { set_pl310_ctrl_reg(0); } -#endif +#endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7df97c5a3..dcc1f831b 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -155,12 +155,7 @@ reset: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -177,14 +172,10 @@ ENTRY(relocate_code) mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -233,34 +224,22 @@ fixnext: add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop - b clear_bss + +relocate_done: + + bx lr + _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: .word __rel_dyn_end - _start _dynsym_start_ofs: .word __dynsym_start - _start +ENDPROC(relocate_code) -clear_bss: - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: +#endif -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -jump_2_ram: +ENTRY(c_runtime_cpu_setup) /* * If I-cache is enabled invalidate it */ @@ -279,20 +258,9 @@ jump_2_ram: mcr p15, 0, r0, c12, c0, 0 @Set VBAR #endif /* !Tegra20 */ - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr + bx lr -_board_init_r_ofs: - .word board_init_r - _start -ENDPROC(relocate_code) -#endif +ENDPROC(c_runtime_cpu_setup) /************************************************************************* * diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index c12f1a7db..efb5a400c 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -245,12 +245,7 @@ reset: orr r0,r0,#0x13 msr cpsr,r0 -/* Set initial stackpointer in SDRAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -267,14 +262,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -326,42 +317,9 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: - - bl coloured_LED_init - bl red_led_on -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr +relocate_done: -_board_init_r_ofs: - .word board_init_r - _start + bx lr _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -370,6 +328,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + bx lr + /****************************************************************************/ /* */ /* Interrupt handling */ diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 536cf5c97..72af86970 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -164,12 +164,7 @@ reset: bl lock_cache_for_stack #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0, =0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ #ifndef CONFIG_SPL_BUILD @@ -186,10 +181,6 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - /* Disable the Dcache RAM lock for stack now */ #ifdef CONFIG_CPU_PXA25X bl cpu_init_crit @@ -198,7 +189,7 @@ stack_setup: adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -250,48 +241,9 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: -#endif /* #ifndef CONFIG_SPL_BUILD */ - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_ONENAND_SPL - ldr r0, _onenand_boot_ofs - mov pc, r0 - -_onenand_boot_ofs: - .word onenand_boot -#else -jump_2_ram: - ldr r0, _board_init_r_ofs - ldr r1, _TEXT_BASE - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr +relocate_done: -_board_init_r_ofs: - .word board_init_r - _start -#endif + bx lr _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -299,7 +251,14 @@ _rel_dyn_end_ofs: .word __rel_dyn_end - _start _dynsym_start_ofs: .word __dynsym_start - _start + #endif + + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + bx lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index 323b923f1..4528c9198 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -128,12 +128,7 @@ reset: bl lowlevel_init #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -150,14 +145,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -209,42 +200,9 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: +relocate_done: - bl coloured_LED_init - bl red_led_on -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr - -_board_init_r_ofs: - .word board_init_r - _start + bx lr _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -253,6 +211,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + bx lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 1ea92d145..3144299af 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -132,12 +132,7 @@ reset: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -154,14 +149,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -213,40 +204,10 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ +relocate_done: -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ mov pc, lr -_board_init_r_ofs: - .word board_init_r - _start - _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: @@ -254,6 +215,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + mov pc, lr + /* ************************************************************************* * diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index d6c038e3a..16e8a8070 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -60,6 +60,59 @@ #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ +struct gpmc_cs { + u32 config1; /* 0x00 */ + u32 config2; /* 0x04 */ + u32 config3; /* 0x08 */ + u32 config4; /* 0x0C */ + u32 config5; /* 0x10 */ + u32 config6; /* 0x14 */ + u32 config7; /* 0x18 */ + u32 nand_cmd; /* 0x1C */ + u32 nand_adr; /* 0x20 */ + u32 nand_dat; /* 0x24 */ + u8 res[8]; /* blow up to 0x30 byte */ +}; + +struct bch_res_0_3 { + u32 bch_result_x[4]; +}; + +struct gpmc { + u8 res1[0x10]; + u32 sysconfig; /* 0x10 */ + u8 res2[0x4]; + u32 irqstatus; /* 0x18 */ + u32 irqenable; /* 0x1C */ + u8 res3[0x20]; + u32 timeout_control; /* 0x40 */ + u8 res4[0xC]; + u32 config; /* 0x50 */ + u32 status; /* 0x54 */ + u8 res5[0x8]; /* 0x58 */ + struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ + u8 res6[0x14]; /* 0x1E0 */ + u32 ecc_config; /* 0x1F4 */ + u32 ecc_control; /* 0x1F8 */ + u32 ecc_size_config; /* 0x1FC */ + u32 ecc1_result; /* 0x200 */ + u32 ecc2_result; /* 0x204 */ + u32 ecc3_result; /* 0x208 */ + u32 ecc4_result; /* 0x20C */ + u32 ecc5_result; /* 0x210 */ + u32 ecc6_result; /* 0x214 */ + u32 ecc7_result; /* 0x218 */ + u32 ecc8_result; /* 0x21C */ + u32 ecc9_result; /* 0x220 */ + u8 res7[12]; /* 0x224 */ + u32 testmomde_ctrl; /* 0x230 */ + u8 res8[12]; /* 0x234 */ + struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ +}; + +/* Used for board specific gpmc initialization */ +extern struct gpmc *gpmc_cfg; + /* Encapsulating core pll registers */ struct cm_wkuppll { unsigned int wkclkstctrl; /* offset 0x00 */ diff --git a/arch/arm/include/asm/arch-am33xx/elm.h b/arch/arm/include/asm/arch-am33xx/elm.h new file mode 100644 index 000000000..e80f7d48e --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/elm.h @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com> + * Mansoor Ahamed <mansoor.ahamed@ti.com> + * + * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap3 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_ELM_H +#define __ASM_ARCH_ELM_H +/* + * ELM Module Registers + */ + +/* ELM registers bit fields */ +#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2) +#define ELM_SYSCONFIG_SOFTRESET (0x2) +#define ELM_SYSSTATUS_RESETDONE_MASK (0x1) +#define ELM_SYSSTATUS_RESETDONE (0x1) +#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3) +#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000) +#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16) +#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000) +#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100) +#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F) + +#ifndef __ASSEMBLY__ + +enum bch_level { + BCH_4_BIT = 0, + BCH_8_BIT, + BCH_16_BIT +}; + + +/* BCH syndrome registers */ +struct syndrome { + u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */ + u8 res1[36]; /* 0x41c */ +}; + +/* BCH error status & location register */ +struct location { + u32 location_status; /* 0x800 */ + u8 res1[124]; /* 0x804 */ + u32 error_location_x[16]; /* 0x880.... */ + u8 res2[64]; /* 0x8c0 */ +}; + +/* BCH ELM register map - do not try to allocate memmory for this structure. + * We have used plenty of reserved variables to fill the slots in the ELM + * register memory map. + * Directly initialize the struct pointer to ELM base address. + */ +struct elm { + u32 rev; /* 0x000 */ + u8 res1[12]; /* 0x004 */ + u32 sysconfig; /* 0x010 */ + u32 sysstatus; /* 0x014 */ + u32 irqstatus; /* 0x018 */ + u32 irqenable; /* 0x01c */ + u32 location_config; /* 0x020 */ + u8 res2[92]; /* 0x024 */ + u32 page_ctrl; /* 0x080 */ + u8 res3[892]; /* 0x084 */ + struct syndrome syndrome_fragments[8]; /* 0x400 */ + u8 res4[512]; /* 0x600 */ + struct location error_location[8]; /* 0x800 */ +}; + +int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, + u32 *error_locations); +int elm_config(enum bch_level level); +void elm_reset(void); +void elm_init(void); +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_ELM_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 24ab365ea..6dd329690 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -80,6 +80,9 @@ #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE +/* GPMC Base address */ +#define GPMC_BASE 0x50000000 + /* CPSW Config space */ #define AM335X_CPSW_BASE 0x4A100000 #define AM335X_CPSW_MDIO_BASE 0x4A101000 diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h new file mode 100644 index 000000000..c3bf74e62 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mem.h @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * + * Author + * Mansoor Ahamed <mansoor.ahamed@ti.com> + * + * Initial Code from: + * Richard Woodruff <r-woodruff2@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +/* + * GPMC settings - + * Definitions is as per the following format + * #define <PART>_GPMC_CONFIG<x> <value> + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * M_NAND - Micron NAND + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define M_NAND_GPMC_CONFIG1 0x00000800 +#define M_NAND_GPMC_CONFIG2 0x001e1e00 +#define M_NAND_GPMC_CONFIG3 0x001e1e00 +#define M_NAND_GPMC_CONFIG4 0x16051807 +#define M_NAND_GPMC_CONFIG5 0x00151e1e +#define M_NAND_GPMC_CONFIG6 0x16000f80 +#define M_NAND_GPMC_CONFIG7 0x00000008 + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#define PISMO1_NOR 1 +#define PISMO1_NAND 2 +#define PISMO2_CS0 3 +#define PISMO2_CS1 4 +#define PISMO1_ONENAND 5 +#define DBG_MPDB 6 +#define PISMO2_NAND_CS0 7 +#define PISMO2_NAND_CS1 8 + +/* make it readable for the gpmc_init */ +#define PISMO1_NOR_BASE FLASH_BASE +#define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE +#define PISMO1_NAND_SIZE GPMC_SIZE_256M + +#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h new file mode 100644 index 000000000..572f9d0b2 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com> + * Rohit Choraria <rohitkc@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_OMAP_GPMC_H +#define __ASM_ARCH_OMAP_GPMC_H + +#define GPMC_BUF_EMPTY 0 +#define GPMC_BUF_FULL 1 + +#define ECCCLEAR (0x1 << 8) +#define ECCRESULTREG1 (0x1 << 0) +#define ECCSIZE512BYTE 0xFF +#define ECCSIZE1 (ECCSIZE512BYTE << 22) +#define ECCSIZE0 (ECCSIZE512BYTE << 12) +#define ECCSIZE0SEL (0x000 << 0) + +/* Generic ECC Layouts */ +/* Large Page x8 NAND device Layout */ +#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT {\ + .eccbytes = 12,\ + .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\ + 9, 10, 11, 12},\ + .oobfree = {\ + {.offset = 13,\ + .length = 51 } } \ +} +#endif + +/* Large Page x16 NAND device Layout */ +#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT {\ + .eccbytes = 12,\ + .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13},\ + .oobfree = {\ + {.offset = 14,\ + .length = 50 } } \ +} +#endif + +/* Small Page x8 NAND device Layout */ +#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT {\ + .eccbytes = 3,\ + .eccpos = {1, 2, 3},\ + .oobfree = {\ + {.offset = 4,\ + .length = 12 } } \ +} +#endif + +/* Small Page x16 NAND device Layout */ +#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT {\ + .eccbytes = 3,\ + .eccpos = {2, 3, 4},\ + .oobfree = {\ + {.offset = 5,\ + .length = 11 } } \ +} +#endif + +#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\ + .eccbytes = 32,\ + .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\ + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\ + 28, 29, 30, 31, 32, 33},\ + .oobfree = {\ + {.offset = 34,\ + .length = 30 } } \ +} + +#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\ + .eccbytes = 56,\ + .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\ + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\ + 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\ + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\ + 52, 53, 54, 55, 56, 57},\ + .oobfree = {\ + {.offset = 58,\ + .length = 6 } } \ +} + +#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\ + .eccbytes = 104,\ + .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\ + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\ + 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\ + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\ + 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\ + 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\ + 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\ + 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\ + 100, 101, 102, 103, 104, 105},\ + .oobfree = {\ + {.offset = 106,\ + .length = 8 } } \ +} +#endif /* __ASM_ARCH_OMAP_GPMC_H */ diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 9cf35e025..588d8de82 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -33,4 +33,7 @@ u32 get_device_type(void); void setup_clocks_for_console(void); void ddr_pll_config(unsigned int ddrpll_M); +void sdelay(unsigned long); +void gpmc_init(void); +void omap_nand_switch_ecc(int); #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h index 0e728c96d..de0f1b192 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9x5.h +++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h @@ -154,6 +154,8 @@ #define ATMEL_PIO_PORTS 4 #define CPU_HAS_PIO3 #define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP +#define ATMEL_ID_UHP ATMEL_ID_UHPHS /* * at91sam9x5 specific prototypes diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h index 57bfe8e78..009a6bb8f 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/include/asm/arch-kirkwood/cpu.h @@ -33,7 +33,7 @@ | (attr << 8) | (kw_winctrl_calcsize(size) << 16)) #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \ - ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c) + ((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c) #define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00) #define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08) diff --git a/arch/arm/include/asm/arch-kirkwood/mpp.h b/arch/arm/include/asm/arch-kirkwood/mpp.h index 8ceea7bb8..48d1477ff 100644 --- a/arch/arm/include/asm/arch-kirkwood/mpp.h +++ b/arch/arm/include/asm/arch-kirkwood/mpp.h @@ -312,6 +312,6 @@ #define MPP_MAX 49 -void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save); +void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save); #endif diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 9e52b12aa..d60f2addb 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -32,6 +32,15 @@ struct emu_hal_params { u32 param1; }; +/* Board SDRC timing values */ +struct board_sdrc_timings { + u32 mcfg; + u32 ctrla; + u32 ctrlb; + u32 rfr_ctrl; + u32 mr; +}; + void prcm_init(void); void per_clocks_enable(void); void ehci_clocks_enable(void); @@ -39,8 +48,8 @@ void ehci_clocks_enable(void); void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr); + +void get_board_mem_timings(struct board_sdrc_timings *timings); void identify_nand_chip(int *mfr, int *id); void emif4_init(void); void gpmc_init(void); diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 2b9af9380..41a26edfb 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -73,6 +73,7 @@ typedef struct global_data { unsigned long reloc_off; #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long tlb_addr; + unsigned long tlb_size; #endif const void *fdt_blob; /* Our device tree, NULL if none */ void **jt; /* jump table */ diff --git a/arch/arm/include/asm/omap_gpio.h b/arch/arm/include/asm/omap_gpio.h index 516cc4260..1ebfa8694 100644 --- a/arch/arm/include/asm/omap_gpio.h +++ b/arch/arm/include/asm/omap_gpio.h @@ -49,4 +49,11 @@ extern const struct gpio_bank *const omap_gpio_bank; #define METHOD_GPIO_24XX 4 +/** + * Check if gpio is valid. + * + * @param gpio GPIO number + * @return 1 if ok, 0 on error + */ +int gpio_is_valid(int gpio); #endif /* _GPIO_H_ */ diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 3422ac1c5..57111afd9 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -36,18 +36,21 @@ GLSOBJS += _umodsi3.o GLCOBJS += div0.o +SOBJS-y += crt0.o + ifndef CONFIG_SPL_BUILD COBJS-y += board.o COBJS-y += bootm.o COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o -COBJS-y += interrupts.o -COBJS-y += reset.o SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o else COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o endif +COBJS-y += interrupts.o +COBJS-y += reset.o + COBJS-y += cache.o COBJS-y += cache-cp15.o diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index e0cb6353a..cfe32cc92 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -40,6 +40,7 @@ #include <common.h> #include <command.h> +#include <environment.h> #include <malloc.h> #include <stdio_dev.h> #include <version.h> @@ -231,15 +232,23 @@ int __power_init_board(void) int power_init_board(void) __attribute__((weak, alias("__power_init_board"))); + /* Record the board_init_f() bootstage (after arch_cpu_init()) */ +static int mark_bootstage(void) +{ + bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); + + return 0; +} + init_fnc_t *init_sequence[] = { arch_cpu_init, /* basic arch cpu dependent setup */ - -#if defined(CONFIG_BOARD_EARLY_INIT_F) - board_early_init_f, -#endif + mark_bootstage, #ifdef CONFIG_OF_CONTROL fdtdec_check_fdt, #endif +#if defined(CONFIG_BOARD_EARLY_INIT_F) + board_early_init_f, +#endif timer_init, /* initialize timer */ #ifdef CONFIG_BOARD_POSTCLK_INIT board_postclk_init, @@ -277,13 +286,6 @@ void board_init_f(ulong bootflag) void *new_fdt = NULL; size_t fdt_size = 0; - bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07); - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); - memset((void *)gd, 0, sizeof(gd_t)); gd->mon_len = _bss_end_ofs; @@ -353,13 +355,14 @@ void board_init_f(ulong bootflag) #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) /* reserve TLB table */ - addr -= (4096 * 4); + gd->tlb_size = 4096 * 4; + addr -= gd->tlb_size; /* round down to next 64 kB limit */ addr &= ~(0x10000 - 1); gd->tlb_addr = addr; - debug("TLB table at: %08lx\n", addr); + debug("TLB table from %08lx to %08lx\n", addr, addr + gd->tlb_size); #endif /* round down to next 4 kB limit */ @@ -465,10 +468,6 @@ void board_init_f(ulong bootflag) gd->fdt_blob = new_fdt; } memcpy(id, (void *)gd, sizeof(gd_t)); - - relocate_code(addr_sp, id, addr); - - /* NOTREACHED - relocate_code() does not return */ } #if !defined(CONFIG_SYS_NO_FLASH) @@ -476,7 +475,38 @@ static char *failed = "*** failed ***\n"; #endif /* - ************************************************************************ + * Tell if it's OK to load the environment early in boot. + * + * If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see + * if this is OK (defaulting to saying it's not OK). + * + * NOTE: Loading the environment early can be a bad idea if security is + * important, since no verification is done on the environment. + * + * @return 0 if environment should not be loaded, !=0 if it is ok to load + */ +static int should_load_env(void) +{ +#ifdef CONFIG_OF_CONTROL + return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 0); +#elif defined CONFIG_DELAY_ENVIRONMENT + return 0; +#else + return 1; +#endif +} + +#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) && defined(CONFIG_OF_CONTROL) +static void display_fdt_model(const void *blob) +{ + const char *model; + + model = (char *)fdt_getprop(blob, 0, "model", NULL); + printf("Model: %s\n", model ? model : "<unknown>"); +} +#endif + +/************************************************************************ * * This is the next part if the initialization sequence: we are now * running from RAM and have a "normal" C environment, i. e. global @@ -493,8 +523,6 @@ void board_init_r(gd_t *id, ulong dest_addr) ulong flash_size; #endif - gd = id; - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r"); @@ -571,8 +599,8 @@ void board_init_r(gd_t *id, ulong dest_addr) #endif #ifdef CONFIG_GENERIC_MMC - puts("MMC: "); - mmc_initialize(gd->bd); + puts("MMC: "); + mmc_initialize(gd->bd); #endif #ifdef CONFIG_HAS_DATAFLASH @@ -581,7 +609,10 @@ void board_init_r(gd_t *id, ulong dest_addr) #endif /* initialize environment */ - env_relocate(); + if (should_load_env()) + env_relocate(); + else + set_default_env(NULL); #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) arm_pci_init(); @@ -598,6 +629,15 @@ void board_init_r(gd_t *id, ulong dest_addr) console_init_r(); /* fully init console as a device */ +#ifdef CONFIG_DISPLAY_BOARDINFO_LATE +# ifdef CONFIG_OF_CONTROL + /* Put this here so it appears on the LCD, now it is ready */ + display_fdt_model(gd->fdt_blob); +# else + checkboard(); +# endif +#endif + #if defined(CONFIG_ARCH_MISC_INIT) /* miscellaneous arch dependent initialisations */ arch_misc_init(); diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 6edf815d4..1cab27c22 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -153,8 +153,11 @@ static void cache_disable(uint32_t cache_bit) return; /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; - flush_dcache_all(); } + reg = get_cr(); + cp_delay(); + if (cache_bit == (CR_C | CR_M)) + flush_dcache_all(); set_cr(reg & ~cache_bit); } #endif diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S new file mode 100644 index 000000000..4f60958b1 --- /dev/null +++ b/arch/arm/lib/crt0.S @@ -0,0 +1,173 @@ +/* + * crt0 - C-runtime startup Code for ARM U-Boot + * + * Copyright (c) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm-offsets.h> + +/* + * This file handles the target-independent stages of the U-Boot + * start-up where a C runtime environment is needed. Its entry point + * is _main and is branched into from the target's start.S file. + * + * _main execution sequence is: + * + * 1. Set up initial environment for calling board_init_f(). + * This environment only provides a stack and a place to store + * the GD ('global data') structure, both located in some readily + * available RAM (SRAM, locked cache...). In this context, VARIABLE + * global data, initialized or not (BSS), are UNAVAILABLE; only + * CONSTANT initialized data are available. + * + * 2. Call board_init_f(). This function prepares the hardware for + * execution from system RAM (DRAM, DDR...) As system RAM may not + * be available yet, , board_init_f() must use the current GD to + * store any data which must be passed on to later stages. These + * data include the relocation destination, the future stack, and + * the future GD location. + * + * (the following applies only to non-SPL builds) + * + * 3. Set up intermediate environment where the stack and GD are the + * ones allocated by board_init_f() in system RAM, but BSS and + * initialized non-const data are still not available. + * + * 4. Call relocate_code(). This function relocates U-Boot from its + * current location into the relocation destination computed by + * board_init_f(). + * + * 5. Set up final environment for calling board_init_r(). This + * environment has BSS (initialized to 0), initialized non-const + * data (initialized to their intended value), and stack in system + * RAM. GD has retained values set by board_init_f(). Some CPUs + * have some work left to do at this point regarding memory, so + * call c_runtime_cpu_setup. + * + * 6. Branch to either nand_boot() or board_init_r(). + */ + +/* + * declare nand_boot() or board_init_r() to jump to at end of crt0 + */ + +#if defined(CONFIG_NAND_SPL) + +.globl nand_boot + +#elif ! defined(CONFIG_SPL_BUILD) + +.globl board_init_r + +#endif + +/* + * start and end of BSS + */ + +.globl __bss_start +.globl __bss_end__ + +/* + * entry point of crt0 sequence + */ + +.global _main + +_main: + +/* + * Set up initial C runtime environment and call board_init_f(0). + */ + +#if defined(CONFIG_NAND_SPL) + /* deprecated, use instead CONFIG_SPL_BUILD */ + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) +#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) + ldr sp, =(CONFIG_SPL_STACK) +#else + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) +#endif + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ + sub sp, #GD_SIZE /* allocate one GD above SP */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ + mov r8, sp /* GD is above SP */ + mov r0, #0 + bl board_init_f + +#if ! defined(CONFIG_SPL_BUILD) + +/* + * Set up intermediate environment (new sp and gd) and call + * relocate_code(addr_sp, gd, addr_moni). Trick here is that + * we'll return 'here' but relocated. + */ + + ldr sp, [r8, #GD_START_ADDR_SP] /* r8 = gd->start_addr_sp */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ + ldr r8, [r8, #GD_BD] /* r8 = gd->bd */ + sub r8, r8, #GD_SIZE /* new GD is below bd */ + + adr lr, here + ldr r0, [r8, #GD_RELOC_OFF] /* lr = gd->start_addr_sp */ + add lr, lr, r0 + ldr r0, [r8, #GD_START_ADDR_SP] /* r0 = gd->start_addr_sp */ + mov r1, r8 /* r1 = gd */ + ldr r2, [r8, #GD_RELOCADDR] /* r2 = gd->relocaddr */ + b relocate_code +here: + +/* Set up final (full) environment */ + + bl c_runtime_cpu_setup /* we still call old routine here */ + + ldr r0, =__bss_start /* this is auto-relocated! */ + ldr r1, =__bss_end__ /* this is auto-relocated! */ + + mov r2, #0x00000000 /* prepare zero to clear BSS */ + +clbss_l:cmp r0, r1 /* while not at end of BSS */ + strlo r2, [r0] /* clear 32-bit BSS word */ + addlo r0, r0, #4 /* move to next */ + blo clbss_l + + bl coloured_LED_init + bl red_led_on + +#if defined(CONFIG_NAND_SPL) + + /* call _nand_boot() */ + ldr pc, =nand_boot + +#else + + /* call board_init_r(gd_t *id, ulong dest_addr) */ + mov r0, r8 /* gd_t */ + ldr r1, [r8, #GD_RELOCADDR] /* dest_addr */ + /* call board_init_r */ + ldr pc, =board_init_r /* this is auto-relocated! */ + +#endif + + /* we should not return here. */ + +#endif diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index 794b8679f..e934cb6c2 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -402,14 +402,14 @@ void board_init_r (gd_t *id, ulong dest_addr) gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - serial_initialize(); - debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); WATCHDOG_RESET (); gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE; + serial_initialize(); + monitor_flash_len = (ulong)&__init_end - dest_addr; #if defined(CONFIG_NEEDS_MANUAL_RELOC) diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h index f1f49fe7f..af5c56f21 100644 --- a/arch/sh/include/asm/cpu_sh4.h +++ b/arch/sh/include/asm/cpu_sh4.h @@ -48,6 +48,8 @@ # include <asm/cpu_sh7724.h> #elif defined (CONFIG_CPU_SH7734) # include <asm/cpu_sh7734.h> +#elif defined (CONFIG_CPU_SH7752) +# include <asm/cpu_sh7752.h> #elif defined (CONFIG_CPU_SH7757) # include <asm/cpu_sh7757.h> #elif defined (CONFIG_CPU_SH7763) diff --git a/arch/sh/include/asm/cpu_sh7752.h b/arch/sh/include/asm/cpu_sh7752.h new file mode 100644 index 000000000..f0ad0e891 --- /dev/null +++ b/arch/sh/include/asm/cpu_sh7752.h @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CPU_SH7752_H_ +#define _ASM_CPU_SH7752_H_ + +#define CCR 0xFF00001C +#define WTCNT 0xFFCC0000 +#define CCR_CACHE_INIT 0x0000090b +#define CACHE_OC_NUM_WAYS 1 + +#ifndef __ASSEMBLY__ /* put C only stuff in this section */ +/* MMU */ +struct mmu_regs { + unsigned int reserved[4]; + unsigned int mmucr; +}; +#define MMU_BASE ((struct mmu_regs *)0xff000000) + +/* Watchdog */ +#define WTCSR0 0xffcc0002 +#define WRSTCSR_R 0xffcc0003 +#define WRSTCSR_W 0xffcc0002 +#define WTCSR_PREFIX 0xa500 +#define WRSTCSR_PREFIX 0x6900 +#define WRSTCSR_WOVF_PREFIX 0x9600 + +/* SCIF */ +#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */ +#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */ +#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */ + +/* TMU0 */ +#define TMU_BASE 0xFE430000 + +/* ETHER, GETHER MAC address */ +struct ether_mac_regs { + unsigned int reserved[114]; + unsigned int mahr; + unsigned int reserved2; + unsigned int malr; +}; +#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400) +#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00) +#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000) +#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800) + +/* GETHER */ +struct gether_control_regs { + unsigned int gbecont; +}; +#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100) +#define GBECONT_RMII1 0x00020000 +#define GBECONT_RMII0 0x00010000 + +/* SerMux */ +struct sermux_regs { + unsigned char smr0; + unsigned char smr1; + unsigned char smr2; + unsigned char smr3; + unsigned char smr4; + unsigned char smr5; +}; +#define SERMUX_BASE ((struct sermux_regs *)0xfe470000) + + +/* USB0/1 */ +struct usb_common_regs { + unsigned short reserved[129]; + unsigned short suspmode; +}; +#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000) +#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000) + +struct usb0_phy_regs { + unsigned short reset; + unsigned short reserved[4]; + unsigned short portsel; +}; +#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000) + +struct usb1_port_regs { + unsigned int port1sel; + unsigned int reserved; + unsigned int usb1intsts; +}; +#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000) + +struct usb1_alignment_regs { + unsigned int ehcidatac; /* 0xfe4fe018 */ + unsigned int reserved[63]; + unsigned int ohcidatac; +}; +#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018) + +/* GPIO */ +struct gpio_regs { + unsigned short pacr; + unsigned short pbcr; + unsigned short pccr; + unsigned short pdcr; + unsigned short pecr; + unsigned short pfcr; + unsigned short pgcr; + unsigned short phcr; + unsigned short picr; + unsigned short pjcr; + unsigned short pkcr; + unsigned short plcr; + unsigned short pmcr; + unsigned short pncr; + unsigned short pocr; + unsigned short reserved; + unsigned short pqcr; + unsigned short prcr; + unsigned short pscr; + unsigned short ptcr; + unsigned short pucr; + unsigned short pvcr; + unsigned short pwcr; + unsigned short pxcr; + unsigned short pycr; + unsigned short pzcr; + unsigned char padr; + unsigned char reserved_a; + unsigned char pbdr; + unsigned char reserved_b; + unsigned char pcdr; + unsigned char reserved_c; + unsigned char pddr; + unsigned char reserved_d; + unsigned char pedr; + unsigned char reserved_e; + unsigned char pfdr; + unsigned char reserved_f; + unsigned char pgdr; + unsigned char reserved_g; + unsigned char phdr; + unsigned char reserved_h; + unsigned char pidr; + unsigned char reserved_i; + unsigned char pjdr; + unsigned char reserved_j; + unsigned char pkdr; + unsigned char reserved_k; + unsigned char pldr; + unsigned char reserved_l; + unsigned char pmdr; + unsigned char reserved_m; + unsigned char pndr; + unsigned char reserved_n; + unsigned char podr; + unsigned char reserved_o; + unsigned char ppdr; + unsigned char reserved_p; + unsigned char pqdr; + unsigned char reserved_q; + unsigned char prdr; + unsigned char reserved_r; + unsigned char psdr; + unsigned char reserved_s; + unsigned char ptdr; + unsigned char reserved_t; + unsigned char pudr; + unsigned char reserved_u; + unsigned char pvdr; + unsigned char reserved_v; + unsigned char pwdr; + unsigned char reserved_w; + unsigned char pxdr; + unsigned char reserved_x; + unsigned char pydr; + unsigned char reserved_y; + unsigned char pzdr; + unsigned char reserved_z; + unsigned short ncer; + unsigned short ncmcr; + unsigned short nccsr; + unsigned char reserved2[2]; + unsigned short psel0; /* +0x70 */ + unsigned short psel1; + unsigned short psel2; + unsigned short psel3; + unsigned short psel4; + unsigned short psel5; + unsigned short psel6; + unsigned short reserved3[2]; + unsigned short psel7; +}; +#define GPIO_BASE ((struct gpio_regs *)0xffec0000) + +#endif /* ifndef __ASSEMBLY__ */ +#endif /* _ASM_CPU_SH7752_H_ */ diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 0e06c2915..e524f3511 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -39,7 +39,7 @@ int board_early_init_f(void) NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 101a80a70..0aa5345dd 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -39,7 +39,7 @@ int board_early_init_f(void) NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile new file mode 100644 index 000000000..b43c3d3bf --- /dev/null +++ b/board/LaCie/wireless_space/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o ../common/common.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg new file mode 100644 index 000000000..0daf5b539 --- /dev/null +++ b/board/LaCie/wireless_space/kwbimage.cfg @@ -0,0 +1,82 @@ +# +# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net> +# +# Based on netspace_v2 kwbimage.cfg: +# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand # Boot from NAND flash +NAND_PAGE_SIZE 800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Values taken from image original LaCie U-Boot header dump! + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1B1B1B9B + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register + +DATA 0xFFD01404 0x37743000 # DDR Controller Control Low + +DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) + +DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) + +DATA 0xFFD01410 0x0000CCCC # DDR Address Control + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control + +DATA 0xFFD01418 0x00000000 # DDR Operation + +DATA 0xFFD0141C 0x00000662 # DDR Mode + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode + +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High + +DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) + +DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled +DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +DATA 0xFFD20134 0x66666666 +DATA 0xFFD20138 0x66666666 +DATA 0xFFD10000 0x01112222 +DATA 0xFFD1000C 0x00000000 +DATA 0xFFD10104 0x00000000 +DATA 0xFFD10100 0x40000000 +# End of Header extension +DATA 0x0 0x0 diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c new file mode 100644 index 000000000..208065899 --- /dev/null +++ b/board/LaCie/wireless_space/wireless_space.c @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> + +#include "../common/common.h" +#include "netdev.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO configuration: start FAN at low speed, USB and HDD */ + +#define WIRELESS_SPACE_OE_LOW 0xFF006808 +#define WIRELESS_SPACE_OE_HIGH 0x0000F989 +#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080 +#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240 + +#define WIRELESS_SPACE_REAR_BUTTON 13 +#define WIRELESS_SPACE_FRONT_BUTTON 43 + +const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* Fan speed (bit 1) */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP13_GPIO, /* Red led */ + MPP14_GPIO, /* USB fuse */ + MPP15_SATA0_ACTn, + MPP16_GPIO, /* SATA 0 power */ + MPP17_GPIO, /* SATA 1 power */ + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, /* Gigabit Ethernet 1 */ + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GE1_8, + MPP29_GE1_9, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GE1_14, + MPP35_GE1_15, + MPP36_GPIO, /* Fan speed (bit 2) */ + MPP37_GPIO, /* Fan speed (bit 0) */ + MPP38_GPIO, /* Fan power */ + MPP39_GPIO, /* Fan rotation fail */ + MPP40_GPIO, /* Ethernet switch link */ + MPP41_GPIO, /* USB enable host vbus */ + MPP42_GPIO, /* LED clock control */ + MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */ + MPP44_GPIO, /* Red LED on/off */ + MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */ + MPP46_GPIO, /* Green LED on/off */ + MPP47_GPIO, /* LED (blue, green) SATA activity blink */ + MPP48_GPIO, /* Blue LED on/off */ + 0 +}; + +struct mv88e61xx_config swcfg = { + .name = "egiga0", + .vlancfg = MV88E61XX_VLANCFG_ROUTER, + .rgmii_delay = MV88E61XX_RGMII_DELAY_EN, + .led_init = MV88E61XX_LED_INIT_EN, + .mdip = MV88E61XX_MDIP_NOCHANGE, + .portstate = MV88E61XX_PORTSTT_FORWARDING, + .cpuport = 0x20, + .ports_enabled = 0x3F, +}; + +int board_early_init_f(void) +{ + /* Gpio configuration */ + kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, + WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +int board_init(void) +{ + /* Machine number */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* Boot parameters address */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) + if (!getenv("ethaddr")) { + uchar mac[6]; + if (lacie_read_mac_address(mac) == 0) + eth_setenv_enetaddr("ethaddr", mac); + } +#endif + return 0; +} +#endif + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and initialize PHY */ +void reset_phy(void) +{ + /* configure switch on egiga0 */ + mv88e61xx_switch_initialize(&swcfg); +} +#endif + +#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD) +/* Return GPIO button status */ +static int +do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (strcmp(argv[1], "button") == 0) { + if (strcmp(argv[2], "rear") == 0) + /* invert GPIO result for intuitive while/until use */ + return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON); + else if (strcmp(argv[2], "front") == 0) + return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON); + else + return -1; + } else { + return -1; + } +} + +U_BOOT_CMD(ws, 3, 0, do_ws, + "Return GPIO button status 0=off 1=on", + "- ws button rear|front: test buttons' states\n" +); +#endif diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index d6497aaa0..0caf34ff0 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -46,7 +46,7 @@ int board_early_init_f(void) DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, /* SPI Flash */ MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index f5c1c3cfd..3a52ab274 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -43,7 +43,7 @@ int board_early_init_f(void) GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index 43852f6b2..fb57faa52 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -45,7 +45,7 @@ int board_early_init_f(void) MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index d48f05a04..c59a32611 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -48,7 +48,7 @@ int board_early_init_f(void) OPENRD_OE_LOW, OPENRD_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index 1fd7677dc..adaa6a1a6 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -44,7 +44,7 @@ int board_early_init_f(void) RD6281A_OE_LOW, RD6281A_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 688d3086d..16efe645d 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -43,7 +43,7 @@ int board_early_init_f(void) SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index fc88520b2..4f1f899b9 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -47,7 +47,7 @@ int board_early_init_f(void) DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index edb088680..8773e6fd3 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -295,6 +295,9 @@ int board_init(void) at91_macb_hw_init(); #endif +#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI) + at91_uhp_hw_init(); +#endif #ifdef CONFIG_LCD at91sam9x5ek_lcd_hw_init(); #endif diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index 57776fb07..83eea04cb 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -49,9 +49,8 @@ * you can do this only with a working network connection. Therefore, a random * ethernet address is generated if none is set and a DHCP request is sent. * After a successful DHCP response is received, the network settings are - * configured and the ncip parameter is set to the serverip. Eg. for a working - * resuce mode, you should set 'next-server' to the host where the netconsole - * client is started. + * configured and the ncip is unset. Therefore, all netconsole packets are + * broadcasted. * Additionally, the bootsource is set to 'rescue'. */ @@ -76,7 +75,7 @@ int board_early_init_f(void) * Multi-Purpose Pins Functionality configuration * These strappings are taken from the original vendor uboot port. */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c index bac9ce55a..3b1c8ec2a 100644 --- a/board/cloudengines/pogo_e02/pogo_e02.c +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -45,7 +45,7 @@ int board_early_init_f(void) POGO_E02_OE_LOW, POGO_E02_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index 6c2e95b1d..edbb94198 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -32,6 +32,7 @@ #include <netdev.h> #include <net.h> #include <i2c.h> +#include <usb.h> #include <twl4030.h> #include <linux/compiler.h> @@ -41,6 +42,8 @@ #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> #include <asm/mach-types.h> +#include <asm/ehci-omap.h> +#include <asm/gpio.h> #include "eeprom.h" @@ -260,6 +263,36 @@ static void cm_t3x_set_common_muxconf(void) MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ + /* USB EHCI */ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ + + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ + + /* SB_T35_USB_HUB_RESET_GPIO */ + MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/ + /* I2C1 */ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ @@ -461,3 +494,47 @@ void __weak get_board_serial(struct tag_serialnr *serialnr) serialnr->low = 0; serialnr->high = 0; }; + +#ifdef CONFIG_USB_EHCI_OMAP +struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, +}; + +#define SB_T35_USB_HUB_RESET_GPIO 167 +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + u8 val; + int offset; + + if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) { + printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset", + SB_T35_USB_HUB_RESET_GPIO); + return -1; + } + + gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0); + udelay(10); + gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1); + udelay(1000); + + offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; + twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, offset); + /* Set GPIO6 and GPIO7 of TPS65930 as output */ + val |= 0xC0; + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, val, offset); + offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1; + /* Take both PHYs out of reset */ + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0xC0, offset); + udelay(1); + + return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(void) +{ + return omap_ehci_hcd_stop(); +} + +#endif /* CONFIG_USB_EHCI_OMAP */ diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index aaff2e868..56fe49527 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -91,15 +91,14 @@ int board_mmc_init(bd_t *bis) * provides the timing values back to the function that configures * the memory. We have either one or two banks of 128MB DDR. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { /* General SDRC config */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; /* AC timings */ - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *mr = MICRON_V_MR_165; + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->mr = MICRON_V_MR_165; } diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c index 11260fe5f..41879017e 100644 --- a/board/d-link/dns325/dns325.c +++ b/board/d-link/dns325/dns325.c @@ -44,7 +44,7 @@ int board_early_init_f(void) DNS325_OE_LOW, DNS325_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index 2aa000f23..b7f474e5e 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -274,7 +274,7 @@ int board_late_init(void) mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0); - gpio_direction_output(37, 1); + gpio_direction_output(IMX_GPIO_NR(2, 5), 1); } val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 2c8cb7a1c..60cd4f0cf 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -343,14 +343,13 @@ static void setup_iomux_i2c(void) static int power_init(void) { unsigned int val; - int ret = -1; + int ret; struct pmic *p; - int retval; if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { - retval = pmic_dialog_init(I2C_PMIC); - if (retval) - return retval; + ret = pmic_dialog_init(I2C_PMIC); + if (ret) + return ret; p = pmic_get("DIALOG_PMIC"); if (!p) @@ -359,20 +358,39 @@ static int power_init(void) /* Set VDDA to 1.25V */ val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); + if (ret) { + printf("Writing to BUCKCORE_REG failed: %d\n", ret); + return ret; + } - ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val); + pmic_reg_read(p, DA9053_SUPPLY_REG, &val); val |= DA9052_SUPPLY_VBCOREGO; - ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val); + ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val); + if (ret) { + printf("Writing to SUPPLY_REG failed: %d\n", ret); + return ret; + } /* Set Vcc peripheral to 1.30V */ - ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); - ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); + ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); + if (ret) { + printf("Writing to BUCKPRO_REG failed: %d\n", ret); + return ret; + } + + ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); + if (ret) { + printf("Writing to SUPPLY_REG failed: %d\n", ret); + return ret; + } + + return ret; } if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { - retval = pmic_init(I2C_PMIC); - if (retval) - return retval; + ret = pmic_init(I2C_PMIC); + if (ret) + return ret; p = pmic_get("FSL_PMIC"); if (!p) @@ -382,28 +400,50 @@ static int power_init(void) pmic_reg_read(p, REG_SW_0, &val); val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; ret = pmic_reg_write(p, REG_SW_0, val); + if (ret) { + printf("Writing to REG_SW_0 failed: %d\n", ret); + return ret; + } /* Set VCC as 1.30V on SW2 */ pmic_reg_read(p, REG_SW_1, &val); val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; - ret |= pmic_reg_write(p, REG_SW_1, val); + ret = pmic_reg_write(p, REG_SW_1, val); + if (ret) { + printf("Writing to REG_SW_1 failed: %d\n", ret); + return ret; + } /* Set global reset timer to 4s */ pmic_reg_read(p, REG_POWER_CTL2, &val); val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; - ret |= pmic_reg_write(p, REG_POWER_CTL2, val); + ret = pmic_reg_write(p, REG_POWER_CTL2, val); + if (ret) { + printf("Writing to REG_POWER_CTL2 failed: %d\n", ret); + return ret; + } /* Set VUSBSEL and VUSBEN for USB PHY supply*/ pmic_reg_read(p, REG_MODE_0, &val); val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); - ret |= pmic_reg_write(p, REG_MODE_0, val); + ret = pmic_reg_write(p, REG_MODE_0, val); + if (ret) { + printf("Writing to REG_MODE_0 failed: %d\n", ret); + return ret; + } /* Set SWBST to 5V in auto mode */ val = SWBST_AUTO; - ret |= pmic_reg_write(p, SWBST_CTRL, val); + ret = pmic_reg_write(p, SWBST_CTRL, val); + if (ret) { + printf("Writing to SWBST_CTRL failed: %d\n", ret); + return ret; + } + + return ret; } - return ret; + return -1; } static void clock_1GHz(void) @@ -462,12 +502,18 @@ int board_init(void) mxc_set_sata_internal_clock(); setup_iomux_i2c(); + + lcd_enable(); + + return 0; +} + +int board_late_init(void) +{ if (!power_init()) clock_1GHz(); print_cpuinfo(); - lcd_enable(); - return 0; } diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c index 0240fb547..65c4a1a4f 100644 --- a/board/freescale/mx6qsabresd/mx6qsabresd.c +++ b/board/freescale/mx6qsabresd/mx6qsabresd.c @@ -86,6 +86,20 @@ static void setup_iomux_enet(void) gpio_set_value(IMX_GPIO_NR(1, 25), 1); } +iomux_v3_cfg_t const usdhc2_pads[] = { + MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + iomux_v3_cfg_t const usdhc3_pads[] = { MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -100,28 +114,82 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } #ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[1] = { +struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR}, {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, }; +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) + int board_mmc_getcd(struct mmc *mmc) { - gpio_direction_input(IMX_GPIO_NR(2, 0)); - return !gpio_get_value(IMX_GPIO_NR(2, 0)); + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + return !gpio_get_value(USDHC2_CD_GPIO); + case USDHC3_BASE_ADDR: + return !gpio_get_value(USDHC3_CD_GPIO); + default: + return 1; /* eMMC/uSDHC4 is always present */ + } } int board_mmc_init(bd_t *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + int i; + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; } #endif diff --git a/board/h2200/h2200.c b/board/h2200/h2200.c index 30763061c..720b06e4c 100644 --- a/board/h2200/h2200.c +++ b/board/h2200/h2200.c @@ -22,9 +22,16 @@ #include <asm/arch/pxa.h> #include <asm/arch/pxa-regs.h> #include <asm/io.h> +#include <usb.h> DECLARE_GLOBAL_DATA_PTR; +int board_eth_init(bd_t *bis) +{ + usb_eth_initialize(bis); + return 0; +} + int board_init(void) { /* We have RAM, disable cache */ @@ -36,6 +43,10 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = 0xa0000100; + /* Let host see that device is disconnected */ + udc_disconnect(); + mdelay(500); + return 0; } diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c index 8cfb4e662..c54c95d28 100644 --- a/board/iomega/iconnect/iconnect.c +++ b/board/iomega/iconnect/iconnect.c @@ -41,7 +41,7 @@ int board_early_init_f(void) ICONNECT_OE_LOW, ICONNECT_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index a8257a300..a0f2aa3e4 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -72,27 +72,26 @@ void omap_rev_string(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; #else if (get_cpu_family() == CPU_OMAP34XX) { - *mcfg = NUMONYX_V_MCFG_165(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } else { - *mcfg = NUMONYX_V_MCFG_200(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_200; - *ctrlb = NUMONYX_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } #endif } diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 107cb7f8e..a41e752b8 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -59,27 +59,26 @@ void omap_rev_string(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; #else if (get_cpu_family() == CPU_OMAP34XX) { - *mcfg = NUMONYX_V_MCFG_165(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } else { - *mcfg = NUMONYX_V_MCFG_200(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_200; - *ctrlb = NUMONYX_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } #endif } diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c index 96410d77d..7a4e7b328 100644 --- a/board/karo/tk71/tk71.c +++ b/board/karo/tk71/tk71.c @@ -47,7 +47,7 @@ int board_early_init_f(void) TK71_OE_LOW, TK71_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index a90f1124f..6f407b78f 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -121,7 +121,7 @@ int i2c_make_abort(void) { #if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD) - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; /* diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 0c4dddc61..eda9199bb 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -54,7 +54,7 @@ DECLARE_GLOBAL_DATA_PTR; #define MASK_RBI_DEFECT_16 0x01 /* Multi-Purpose Pins Functionality configuration */ -u32 kwmpp_config[] = { +static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, @@ -193,15 +193,6 @@ void set_bootcount_addr(void) int misc_init_r(void) { - char *str; - int mach_type; - - str = getenv("mach_type"); - if (str != NULL) { - mach_type = simple_strtoul(str, NULL, 10); - printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); - gd->bd->bi_arch_number = mach_type; - } #if defined(CONFIG_KM_MGCOGE3UN) char *wait_for_ne; wait_for_ne = getenv("waitforne"); @@ -258,11 +249,6 @@ int board_early_init_f(void) int board_init(void) { - /* - * arch number of board - */ - gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD; - /* address of boot parameters */ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg index 6df2ad790..5aa0de252 100644 --- a/board/keymile/km_arm/kwbimage-memphis.cfg +++ b/board/keymile/km_arm/kwbimage-memphis.cfg @@ -55,9 +55,9 @@ DATA 0xFFD10008 0x00001100 # MPP Control 2 Register DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register -DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register -DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register -DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register + +# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! +# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage #Dram initalization DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg index b2f51936f..e5e9942c1 100644 --- a/board/keymile/km_arm/kwbimage.cfg +++ b/board/keymile/km_arm/kwbimage.cfg @@ -52,9 +52,9 @@ DATA 0xFFD10008 0x00001100 # MPP Control 2 Register DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register -DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register -DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register -DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register + +# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! +# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage #Dram initalization DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg index bcce9073f..5de8df70f 100644 --- a/board/keymile/km_arm/kwbimage_128M16_1.cfg +++ b/board/keymile/km_arm/kwbimage_128M16_1.cfg @@ -98,29 +98,8 @@ DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register # bit 19-18: 1, ECC RAM WTC RAM0 # bit 31-20: ???,Reserve -DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register -# bit 23-0: 0x000200, Addr Config tuning -# bit 31-24: 0, Reserved - -# ??? Missing register # CPU RAM Management Control2 Register - -DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register -# bit 15-0: 0x1C00, Opmux Tuning -# bit 31-16: 0, Pc Dp Tuning - -DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register -# bit 1-0: 1, addr clk tune -# bit 3-2: 0, reserved -# bit 5-4: 0, dtcmp clk tune -# bit 7-6: 0, reserved -# bit 9-8: 0, macdrv clk tune -# bit 11-10: 0, opmuxgm2 clk tune -# bit 15-14: 0, rf clk tune -# bit 17-16: 0, rfbypass clk tune -# bit 19-18: 0, pc dp clk tune -# bit 23-20: 0, icache clk tune -# bit 27:24: 0, dcache clk tune -# bit 31:28: 0, regfile tunin +# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! +# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage # SDRAM initalization DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg b/board/keymile/km_arm/kwbimage_256M8_1.cfg index 3e1237bbe..d0a09f61d 100644 --- a/board/keymile/km_arm/kwbimage_256M8_1.cfg +++ b/board/keymile/km_arm/kwbimage_256M8_1.cfg @@ -100,29 +100,8 @@ DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register # bit 19-18: 1, ECC RAM WTC RAM0 # bit 31-20: ?,Reserved -DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register -# bit 23-0: 0x000200, Addr Config tuning -# bit 31-24: 0, Reserved - -# ??? Missing register # CPU RAM Management Control2 Register - -DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register -# bit 15-0: 0x1C00, Opmux Tuning -# bit 31-16: 0, Pc Dp Tuning - -DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register -# bit 1-0: 1, addr clk tune -# bit 3-2: 0, reserved -# bit 5-4: 0, dtcmp clk tune -# bit 7-6: 0, reserved -# bit 9-8: 0, macdrv clk tune -# bit 11-10: 0, opmuxgm2 clk tune -# bit 15-14: 0, rf clk tune -# bit 17-16: 0, rfbypass clk tune -# bit 19-18: 0, pc dp clk tune -# bit 23-20: 0, icache clk tune -# bit 27:24: 0, dcache clk tune -# bit 31:28: 0, regfile tunin +# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! +# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage # SDRAM initalization DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register diff --git a/board/overo/overo.c b/board/overo/overo.c index c6d50a07a..fdf46a2aa 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -147,34 +147,33 @@ int get_board_revision(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; switch (get_board_revision()) { case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - *mcfg = MICRON_V_MCFG_165(256 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - *mcfg = HYNIX_V_MCFG_165(256 << 20); - *ctrla = HYNIX_V_ACTIMA_165; - *ctrlb = HYNIX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = HYNIX_V_MCFG_165(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_165; + timings->ctrlb = HYNIX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; default: - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } } #endif diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c index 5f0f3961d..cf4ca51fc 100644 --- a/board/raidsonic/ib62x0/ib62x0.c +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -45,7 +45,7 @@ int board_early_init_f(void) /* Set SATA activity LEDs to default off */ writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/renesas/sh7752evb/Makefile b/board/renesas/sh7752evb/Makefile new file mode 100644 index 000000000..196c992ad --- /dev/null +++ b/board/renesas/sh7752evb/Makefile @@ -0,0 +1,36 @@ +# +# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := sh7752evb.o spi-boot.o +SOBJS := lowlevel_init.o + +$(LIB): $(obj).depend $(COBJS) $(SOBJS) + $(call cmd_link_o_target, $(COBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/renesas/sh7752evb/lowlevel_init.S b/board/renesas/sh7752evb/lowlevel_init.S new file mode 100644 index 000000000..73c8ac466 --- /dev/null +++ b/board/renesas/sh7752evb/lowlevel_init.S @@ -0,0 +1,460 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/processor.h> +#include <asm/macro.h> + +.macro or32, addr, data + mov.l \addr, r1 + mov.l \data, r0 + mov.l @r1, r2 + or r2, r0 + mov.l r0, @r1 +.endm + +.macro wait_DBCMD + mov.l DBWAIT_A, r0 + mov.l @r0, r1 +.endm + + .global lowlevel_init + .section .spiboot1.text + .align 2 + +lowlevel_init: + /*------- GPIO -------*/ + write16 PDCR_A, PDCR_D ! SPI0 + write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1) + write16 PJCR_A, PJCR_D ! SCIF4 + write16 PTCR_A, PTCR_D ! STATUS + write16 PSEL1_A, PSEL1_D ! SPI0 + write16 PSEL2_A, PSEL2_D ! SPI0 + write16 PSEL5_A, PSEL5_D ! STATUS + + bra exit_gpio + nop + + .align 2 + +/*------- GPIO -------*/ +PDCR_A: .long 0xffec0006 +PGCR_A: .long 0xffec000c +PJCR_A: .long 0xffec0012 +PTCR_A: .long 0xffec0026 +PSEL1_A: .long 0xffec0072 +PSEL2_A: .long 0xffec0074 +PSEL5_A: .long 0xffec007a + +PDCR_D: .long 0x0000 +PGCR_D: .long 0x0004 +PJCR_D: .long 0x0000 +PTCR_D: .long 0x0000 +PSEL1_D: .long 0x0000 +PSEL2_D: .long 0x3000 +PSEL5_D: .long 0x0ffc + + .align 2 + +exit_gpio: + mov #0, r14 + mova 2f, r0 + mov.l PC_MASK, r1 + tst r0, r1 + bf 2f + + bra exit_pmb + nop + + .align 2 + +/* If CPU runs on SDRAM (PC=0x5???????) or not. */ +PC_MASK: .long 0x20000000 + +2: + mov #1, r14 + + mov.l EXPEVT_A, r0 + mov.l @r0, r0 + mov.l EXPEVT_POWER_ON_RESET, r1 + cmp/eq r0, r1 + bt 1f + + /* + * If EXPEVT value is manual reset or tlb multipul-hit, + * initialization of DDR3IF is not necessary. + */ + bra exit_ddr + nop + +1: + /*------- Reset -------*/ + write32 MRSTCR0_A, MRSTCR0_D + write32 MRSTCR1_A, MRSTCR1_D + + /* For Core Reset */ + mov.l DBACEN_A, r0 + mov.l @r0, r0 + cmp/eq #0, r0 + bt 3f + + /* + * If DBACEN == 1(DBSC was already enabled), we have to avoid the + * initialization of DDR3-SDRAM. + */ + bra exit_ddr + nop + +3: + /*------- DDR3IF -------*/ + /* oscillation stabilization time */ + wait_timer WAIT_OSC_TIME + + /* step 3 */ + write32 DBCMD_A, DBCMD_RSTL_VAL + wait_timer WAIT_30US + + /* step 4 */ + write32 DBCMD_A, DBCMD_PDEN_VAL + + /* step 5 */ + write32 DBKIND_A, DBKIND_D + + /* step 6 */ + write32 DBCONF_A, DBCONF_D + write32 DBTR0_A, DBTR0_D + write32 DBTR1_A, DBTR1_D + write32 DBTR2_A, DBTR2_D + write32 DBTR3_A, DBTR3_D + write32 DBTR4_A, DBTR4_D + write32 DBTR5_A, DBTR5_D + write32 DBTR6_A, DBTR6_D + write32 DBTR7_A, DBTR7_D + write32 DBTR8_A, DBTR8_D + write32 DBTR9_A, DBTR9_D + write32 DBTR10_A, DBTR10_D + write32 DBTR11_A, DBTR11_D + write32 DBTR12_A, DBTR12_D + write32 DBTR13_A, DBTR13_D + write32 DBTR14_A, DBTR14_D + write32 DBTR15_A, DBTR15_D + write32 DBTR16_A, DBTR16_D + write32 DBTR17_A, DBTR17_D + write32 DBTR18_A, DBTR18_D + write32 DBTR19_A, DBTR19_D + write32 DBRNK0_A, DBRNK0_D + + /* step 7 */ + write32 DBPDCNT3_A, DBPDCNT3_D + + /* step 8 */ + write32 DBPDCNT1_A, DBPDCNT1_D + write32 DBPDCNT2_A, DBPDCNT2_D + write32 DBPDLCK_A, DBPDLCK_D + write32 DBPDRGA_A, DBPDRGA_D + write32 DBPDRGD_A, DBPDRGD_D + + /* step 9 */ + wait_timer WAIT_30US + + /* step 10 */ + write32 DBPDCNT0_A, DBPDCNT0_D + + /* step 11 */ + wait_timer WAIT_30US + wait_timer WAIT_30US + + /* step 12 */ + write32 DBCMD_A, DBCMD_WAIT_VAL + wait_DBCMD + + /* step 13 */ + write32 DBCMD_A, DBCMD_RSTH_VAL + wait_DBCMD + + /* step 14 */ + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + + /* step 15 */ + write32 DBCMD_A, DBCMD_PDXT_VAL + + /* step 16 */ + write32 DBCMD_A, DBCMD_MRS2_VAL + + /* step 17 */ + write32 DBCMD_A, DBCMD_MRS3_VAL + + /* step 18 */ + write32 DBCMD_A, DBCMD_MRS1_VAL + + /* step 19 */ + write32 DBCMD_A, DBCMD_MRS0_VAL + + /* step 20 */ + write32 DBCMD_A, DBCMD_ZQCL_VAL + + write32 DBCMD_A, DBCMD_REF_VAL + write32 DBCMD_A, DBCMD_REF_VAL + wait_DBCMD + + /* step 21 */ + write32 DBADJ0_A, DBADJ0_D + write32 DBADJ1_A, DBADJ1_D + write32 DBADJ2_A, DBADJ2_D + + /* step 22 */ + write32 DBRFCNF0_A, DBRFCNF0_D + write32 DBRFCNF1_A, DBRFCNF1_D + write32 DBRFCNF2_A, DBRFCNF2_D + + /* step 23 */ + write32 DBCALCNF_A, DBCALCNF_D + + /* step 24 */ + write32 DBRFEN_A, DBRFEN_D + write32 DBCMD_A, DBCMD_SRXT_VAL + + /* step 25 */ + write32 DBACEN_A, DBACEN_D + + /* step 26 */ + wait_DBCMD + + bra exit_ddr + nop + + .align 2 + +EXPEVT_A: .long 0xff000024 +EXPEVT_POWER_ON_RESET: .long 0x00000000 + +/*------- Reset -------*/ +MRSTCR0_A: .long 0xffd50030 +MRSTCR0_D: .long 0xfe1ffe7f +MRSTCR1_A: .long 0xffd50034 +MRSTCR1_D: .long 0xfff3ffff + +/*------- DDR3IF -------*/ +DBCMD_A: .long 0xfe800018 +DBKIND_A: .long 0xfe800020 +DBCONF_A: .long 0xfe800024 +DBTR0_A: .long 0xfe800040 +DBTR1_A: .long 0xfe800044 +DBTR2_A: .long 0xfe800048 +DBTR3_A: .long 0xfe800050 +DBTR4_A: .long 0xfe800054 +DBTR5_A: .long 0xfe800058 +DBTR6_A: .long 0xfe80005c +DBTR7_A: .long 0xfe800060 +DBTR8_A: .long 0xfe800064 +DBTR9_A: .long 0xfe800068 +DBTR10_A: .long 0xfe80006c +DBTR11_A: .long 0xfe800070 +DBTR12_A: .long 0xfe800074 +DBTR13_A: .long 0xfe800078 +DBTR14_A: .long 0xfe80007c +DBTR15_A: .long 0xfe800080 +DBTR16_A: .long 0xfe800084 +DBTR17_A: .long 0xfe800088 +DBTR18_A: .long 0xfe80008c +DBTR19_A: .long 0xfe800090 +DBRNK0_A: .long 0xfe800100 +DBPDCNT0_A: .long 0xfe800200 +DBPDCNT1_A: .long 0xfe800204 +DBPDCNT2_A: .long 0xfe800208 +DBPDCNT3_A: .long 0xfe80020c +DBPDLCK_A: .long 0xfe800280 +DBPDRGA_A: .long 0xfe800290 +DBPDRGD_A: .long 0xfe8002a0 +DBADJ0_A: .long 0xfe8000c0 +DBADJ1_A: .long 0xfe8000c4 +DBADJ2_A: .long 0xfe8000c8 +DBRFCNF0_A: .long 0xfe8000e0 +DBRFCNF1_A: .long 0xfe8000e4 +DBRFCNF2_A: .long 0xfe8000e8 +DBCALCNF_A: .long 0xfe8000f4 +DBRFEN_A: .long 0xfe800014 +DBACEN_A: .long 0xfe800010 +DBWAIT_A: .long 0xfe80001c + +WAIT_OSC_TIME: .long 6000 +WAIT_30US: .long 13333 + +DBCMD_RSTL_VAL: .long 0x20000000 +DBCMD_PDEN_VAL: .long 0x1000d73c +DBCMD_WAIT_VAL: .long 0x0000d73c +DBCMD_RSTH_VAL: .long 0x2100d73c +DBCMD_PDXT_VAL: .long 0x110000c8 +DBCMD_MRS0_VAL: .long 0x28000930 +DBCMD_MRS1_VAL: .long 0x29000004 +DBCMD_MRS2_VAL: .long 0x2a000008 +DBCMD_MRS3_VAL: .long 0x2b000000 +DBCMD_ZQCL_VAL: .long 0x03000200 +DBCMD_REF_VAL: .long 0x0c000000 +DBCMD_SRXT_VAL: .long 0x19000000 +DBKIND_D: .long 0x00000007 +DBCONF_D: .long 0x0f030a01 +DBTR0_D: .long 0x00000007 +DBTR1_D: .long 0x00000006 +DBTR2_D: .long 0x00000000 +DBTR3_D: .long 0x00000007 +DBTR4_D: .long 0x00070007 +DBTR5_D: .long 0x0000001b +DBTR6_D: .long 0x00000014 +DBTR7_D: .long 0x00000005 +DBTR8_D: .long 0x00000015 +DBTR9_D: .long 0x00000006 +DBTR10_D: .long 0x00000008 +DBTR11_D: .long 0x00000007 +DBTR12_D: .long 0x0000000e +DBTR13_D: .long 0x00000056 +DBTR14_D: .long 0x00000006 +DBTR15_D: .long 0x00000004 +DBTR16_D: .long 0x00150002 +DBTR17_D: .long 0x000c0017 +DBTR18_D: .long 0x00000200 +DBTR19_D: .long 0x00000040 +DBRNK0_D: .long 0x00000001 +DBPDCNT0_D: .long 0x00000001 +DBPDCNT1_D: .long 0x00000001 +DBPDCNT2_D: .long 0x00000000 +DBPDCNT3_D: .long 0x00004010 +DBPDLCK_D: .long 0x0000a55a +DBPDRGA_D: .long 0x00000028 +DBPDRGD_D: .long 0x00017100 + +DBADJ0_D: .long 0x00000000 +DBADJ1_D: .long 0x00000000 +DBADJ2_D: .long 0x18061806 +DBRFCNF0_D: .long 0x000001ff +DBRFCNF1_D: .long 0x08001000 +DBRFCNF2_D: .long 0x00000000 +DBCALCNF_D: .long 0x0000ffff +DBRFEN_D: .long 0x00000001 +DBACEN_D: .long 0x00000001 + + .align 2 +exit_ddr: +#if defined(CONFIG_SH_32BIT) + /*------- set PMB -------*/ + write32 PASCR_A, PASCR_29BIT_D + write32 MMUCR_A, MMUCR_D + + /***************************************************************** + * ent virt phys v sz c wt + * 0 0xa0000000 0x00000000 1 128M 0 1 + * 1 0xa8000000 0x48000000 1 128M 0 1 + * 5 0x88000000 0x48000000 1 128M 1 1 + */ + write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D + write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D + write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D + write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D + write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D + write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D + + write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D + + write32 PASCR_A, PASCR_INIT + mov.l DUMMY_ADDR, r0 + icbi @r0 +#endif /* if defined(CONFIG_SH_32BIT) */ + +exit_pmb: + /* CPU is running on ILRAM? */ + mov r14, r0 + tst #1, r0 + bt 1f + + mov.l _stack_ilram, r15 + mov.l _spiboot_main, r0 +100: bsrf r0 + nop + + .align 2 +_spiboot_main: .long (spiboot_main - (100b + 4)) +_stack_ilram: .long 0xe5204000 + +1: + write32 CCR_A, CCR_D + + rts + nop + + .align 2 + +#if defined(CONFIG_SH_32BIT) +/*------- set PMB -------*/ +PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) +PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) +PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) +PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) +PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) +PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) +PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) +PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) +PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) +PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) +PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) +PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) +PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) +PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) +PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) +PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) + +PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) +PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) +PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) +PMB_ADDR_NOT_USE_D: .long 0x00000000 + +PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) +PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) +PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) + +/* ppn ub v s1 s0 c wt */ +PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) +PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) + +PASCR_A: .long 0xff000070 +DUMMY_ADDR: .long 0xa0000000 +PASCR_29BIT_D: .long 0x00000000 +PASCR_INIT: .long 0x80000080 +MMUCR_A: .long 0xff000010 +MMUCR_D: .long 0x00000004 /* clear ITLB */ +#endif /* CONFIG_SH_32BIT */ + +CCR_A: .long CCR +CCR_D: .long CCR_CACHE_INIT diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c new file mode 100644 index 000000000..e99659395 --- /dev/null +++ b/board/renesas/sh7752evb/sh7752evb.c @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/mmc.h> +#include <spi_flash.h> + +int checkboard(void) +{ + puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n"); + + return 0; +} + +static void init_gpio(void) +{ + struct gpio_regs *gpio = GPIO_BASE; + struct sermux_regs *sermux = SERMUX_BASE; + + /* GPIO */ + writew(0x0000, &gpio->pacr); /* GETHER */ + writew(0x0001, &gpio->pbcr); /* INTC */ + writew(0x0000, &gpio->pccr); /* PWMU, INTC */ + writew(0xeaff, &gpio->pecr); /* GPIO */ + writew(0x0000, &gpio->pfcr); /* WDT */ + writew(0x0000, &gpio->phcr); /* SPI1 */ + writew(0x0000, &gpio->picr); /* SDHI */ + writew(0x0003, &gpio->pkcr); /* SerMux */ + writew(0x0000, &gpio->plcr); /* SerMux */ + writew(0x0000, &gpio->pmcr); /* RIIC */ + writew(0x0000, &gpio->pncr); /* USB, SGPIO */ + writew(0x0000, &gpio->pocr); /* SGPIO */ + writew(0xd555, &gpio->pqcr); /* GPIO */ + writew(0x0000, &gpio->prcr); /* RIIC */ + writew(0x0000, &gpio->pscr); /* RIIC */ + writeb(0x00, &gpio->pudr); + writew(0x5555, &gpio->pucr); /* Debug LED */ + writew(0x0000, &gpio->pvcr); /* RSPI */ + writew(0x0000, &gpio->pwcr); /* EVC */ + writew(0x0000, &gpio->pxcr); /* LBSC */ + writew(0x0000, &gpio->pycr); /* LBSC */ + writew(0x0000, &gpio->pzcr); /* eMMC */ + writew(0xfe00, &gpio->psel0); + writew(0xff00, &gpio->psel3); + writew(0x771f, &gpio->psel4); + writew(0x00ff, &gpio->psel6); + writew(0xfc00, &gpio->psel7); + + writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */ +} + +static void init_usb_phy(void) +{ + struct usb_common_regs *common0 = USB0_COMMON_BASE; + struct usb_common_regs *common1 = USB1_COMMON_BASE; + struct usb0_phy_regs *phy = USB0_PHY_BASE; + struct usb1_port_regs *port = USB1_PORT_BASE; + struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; + + writew(0x0100, &phy->reset); /* set reset */ + /* port0 = USB0, port1 = USB1 */ + writew(0x0002, &phy->portsel); + writel(0x0001, &port->port1sel); /* port1 = Host */ + writew(0x0111, &phy->reset); /* clear reset */ + + writew(0x4000, &common0->suspmode); + writew(0x4000, &common1->suspmode); + +#if defined(__LITTLE_ENDIAN) + writel(0x00000000, &align->ehcidatac); + writel(0x00000000, &align->ohcidatac); +#endif +} + +static void init_gether_mdio(void) +{ + struct gpio_regs *gpio = GPIO_BASE; + + writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); + writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ +} + +static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) +{ + struct ether_mac_regs *ether; + unsigned char mac[6]; + unsigned long val; + + eth_parse_enetaddr(mac_string, mac); + + if (!channel) + ether = GETHER0_MAC_BASE; + else + ether = GETHER1_MAC_BASE; + + val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; + writel(val, ðer->mahr); + val = (mac[4] << 8) | mac[5]; + writel(val, ðer->malr); +} + +/***************************************************************** + * This PMB must be set on this timing. The lowlevel_init is run on + * Area 0(phys 0x00000000), so we have to map it. + * + * The new PMB table is following: + * ent virt phys v sz c wt + * 0 0xa0000000 0x40000000 1 128M 0 1 + * 1 0xa8000000 0x48000000 1 128M 0 1 + * 2 0xb0000000 0x50000000 1 128M 0 1 + * 3 0xb8000000 0x58000000 1 128M 0 1 + * 4 0x80000000 0x40000000 1 128M 1 1 + * 5 0x88000000 0x48000000 1 128M 1 1 + * 6 0x90000000 0x50000000 1 128M 1 1 + * 7 0x98000000 0x58000000 1 128M 1 1 + */ +static void set_pmb_on_board_init(void) +{ + struct mmu_regs *mmu = MMU_BASE; + + /* clear ITLB */ + writel(0x00000004, &mmu->mmucr); + + /* delete PMB for SPIBOOT */ + writel(0, PMB_ADDR_BASE(0)); + writel(0, PMB_DATA_BASE(0)); + + /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ + /* ppn ub v s1 s0 c wt */ + writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); + writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); + writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); + writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); + writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); + writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); + writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); + writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); + writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); + writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); + writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); + writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); +} + +int board_init(void) +{ + init_gpio(); + set_pmb_on_board_init(); + + init_usb_phy(); + init_gether_mdio(); + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + struct gpio_regs *gpio = GPIO_BASE; + + writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); + writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ + udelay(1); + writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ + udelay(200); + + return mmcif_mmc_init(); +} + +static int get_sh_eth_mac_raw(unsigned char *buf, int size) +{ + struct spi_flash *spi; + int ret; + + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (spi == NULL) { + printf("%s: spi_flash probe failed.\n", __func__); + return 1; + } + + ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf); + if (ret) { + printf("%s: spi_flash read failed.\n", __func__); + spi_flash_free(spi); + return 1; + } + spi_flash_free(spi); + + return 0; +} + +static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) +{ + memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)], + SH7752EVB_ETHERNET_MAC_SIZE); + mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ + + return 0; +} + +static void init_ethernet_mac(void) +{ + char mac_string[64]; + char env_string[64]; + int i; + unsigned char *buf; + + buf = malloc(256); + if (!buf) { + printf("%s: malloc failed.\n", __func__); + return; + } + get_sh_eth_mac_raw(buf, 256); + + /* Gigabit Ethernet */ + for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { + get_sh_eth_mac(i, mac_string, buf); + if (i == 0) + setenv("ethaddr", mac_string); + else { + sprintf(env_string, "eth%daddr", i); + setenv(env_string, mac_string); + } + set_mac_to_sh_giga_eth_register(i, mac_string); + } + + free(buf); +} + +int board_late_init(void) +{ + init_ethernet_mac(); + + return 0; +} + +int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i, ret; + char mac_string[256]; + struct spi_flash *spi; + unsigned char *buf; + + if (argc != 3) { + buf = malloc(256); + if (!buf) { + printf("%s: malloc failed.\n", __func__); + return 1; + } + + get_sh_eth_mac_raw(buf, 256); + + /* print current MAC address */ + for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { + get_sh_eth_mac(i, mac_string, buf); + printf("GETHERC ch%d = %s\n", i, mac_string); + } + free(buf); + return 0; + } + + /* new setting */ + memset(mac_string, 0xff, sizeof(mac_string)); + sprintf(mac_string, "%s\t%s", + argv[1], argv[2]); + + /* write MAC data to SPI rom */ + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (!spi) { + printf("%s: spi_flash probe failed.\n", __func__); + return 1; + } + + ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, + SH7752EVB_SPI_SECTOR_SIZE); + if (ret) { + printf("%s: spi_flash erase failed.\n", __func__); + return 1; + } + + ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, + sizeof(mac_string), mac_string); + if (ret) { + printf("%s: spi_flash write failed.\n", __func__); + spi_flash_free(spi); + return 1; + } + spi_flash_free(spi); + + puts("The writing of the MAC address to SPI ROM was completed.\n"); + + return 0; +} + +U_BOOT_CMD( + write_mac, 3, 1, do_write_mac, + "write MAC address for GETHERC", + "[GETHERC ch0] [GETHERC ch1]\n" +); diff --git a/board/renesas/sh7752evb/spi-boot.c b/board/renesas/sh7752evb/spi-boot.c new file mode 100644 index 000000000..91565d44d --- /dev/null +++ b/board/renesas/sh7752evb/spi-boot.c @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License. See the file "COPYING.LIB" in the main + * directory of this archive for more details. + */ + +#include <common.h> + +#define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE +#define CONFIG_SPI_ADDR 0x00000000 +#define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN +#define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE + +#define SPIWDMADR 0xFE001018 +#define SPIWDMCNTR 0xFE001020 +#define SPIDMCOR 0xFE001028 +#define SPIDMINTSR 0xFE001188 +#define SPIDMINTMR 0xFE001190 + +#define SPIDMINTSR_DMEND 0x00000004 + +#define TBR 0xFE002000 +#define RBR 0xFE002000 + +#define CR1 0xFE002008 +#define CR2 0xFE002010 +#define CR3 0xFE002018 +#define CR4 0xFE002020 + +/* CR1 */ +#define SPI_TBE 0x80 +#define SPI_TBF 0x40 +#define SPI_RBE 0x20 +#define SPI_RBF 0x10 +#define SPI_PFONRD 0x08 +#define SPI_SSDB 0x04 +#define SPI_SSD 0x02 +#define SPI_SSA 0x01 + +/* CR2 */ +#define SPI_RSTF 0x80 +#define SPI_LOOPBK 0x40 +#define SPI_CPOL 0x20 +#define SPI_CPHA 0x10 +#define SPI_L1M0 0x08 + +/* CR4 */ +#define SPI_TBEI 0x80 +#define SPI_TBFI 0x40 +#define SPI_RBEI 0x20 +#define SPI_RBFI 0x10 +#define SPI_SpiS0 0x02 +#define SPI_SSS 0x01 + +#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val +#define spi_read(addr) (*(volatile unsigned long *)(addr)) + +/* M25P80 */ +#define M25_READ 0x03 + +#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) +static void __uses_spiboot2 spi_reset(void) +{ + int timeout = 0x00100000; + + /* Make sure the last transaction is finalized */ + spi_write(0x00, CR3); + spi_write(0x02, CR1); + while (!(spi_read(CR4) & SPI_SpiS0)) { + if (timeout-- < 0) + break; + } + spi_write(0x00, CR1); + + spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ + spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); + + spi_write(0, SPIDMCOR); +} + +static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, + unsigned long len) +{ + spi_write(M25_READ, TBR); + spi_write((addr >> 16) & 0xFF, TBR); + spi_write((addr >> 8) & 0xFF, TBR); + spi_write(addr & 0xFF, TBR); + + spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); + spi_write((unsigned long)buf, SPIWDMADR); + spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); + spi_write(1, SPIDMCOR); + + spi_write(0xff, CR3); + spi_write(spi_read(CR1) | SPI_SSDB, CR1); + spi_write(spi_read(CR1) | SPI_SSA, CR1); + + while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) + ; + + /* Nagate SP0-SS0 */ + spi_write(0, CR1); +} + +void __uses_spiboot2 spiboot_main(void) +{ + void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; + + spi_reset(); + spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, + CONFIG_SPI_LENGTH); + + _start(); +} diff --git a/board/renesas/sh7752evb/u-boot.lds b/board/renesas/sh7752evb/u-boot.lds new file mode 100644 index 000000000..28449b677 --- /dev/null +++ b/board/renesas/sh7752evb/u-boot.lds @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * Copyright (C) 2012 + * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + * entry and reloct_dst will be provided via ldflags + */ + . = .; + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + KEEP(arch/sh/cpu/sh4/start.o (.text)) + *(.spiboot1.text) + *(.spiboot2.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + .u_boot_list : { + #include <u-boot.lst> + } + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss (NOLOAD) : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (__bss_end__ = .); +} diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index 147155990..c9eea9b30 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -98,9 +98,12 @@ int board_init(void) return 0; } +#ifndef CONFIG_SPL_BUILD int misc_init_r(void) { char *eth_addr; + struct tam3517_module_info info; + int ret; dieid_num_r(); @@ -108,12 +111,13 @@ int misc_init_r(void) if (eth_addr) return 0; -#ifndef CONFIG_SPL_BUILD - TAM3517_READ_MAC_FROM_EEPROM; -#endif + TAM3517_READ_EEPROM(&info, ret); + if (!ret) + TAM3517_READ_MAC_FROM_EEPROM(&info); return 0; } +#endif /* * Routine: set_muxconf_regs diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index 9622a8128..c516c75a0 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -73,10 +73,10 @@ static struct { static struct panel_config lcd_cfg[] = { { - .timing_h = PANEL_TIMING_H(4, 8, 41), - .timing_v = PANEL_TIMING_V(2, 4, 10), - .pol_freq = 0x00000000, /* Pol Freq */ - .divisor = 0x0001000d, /* 33Mhz Pixel Clock */ + .timing_h = PANEL_TIMING_H(40, 5, 2), + .timing_v = PANEL_TIMING_V(8, 8, 2), + .pol_freq = 0x00003000, /* Pol Freq */ + .divisor = 0x00010033, /* 9 Mhz Pixel Clock */ .panel_type = 0x01, /* TFT */ .data_lines = 0x03, /* 24 Bit RGB */ .load_mode = 0x02, /* Frame Mode */ @@ -258,21 +258,26 @@ int board_init(void) return 0; } +#ifndef CONFIG_SPL_BUILD int misc_init_r(void) { char *eth_addr; + struct tam3517_module_info info; + int ret; + TAM3517_READ_EEPROM(&info, ret); dieid_num_r(); - eth_addr = getenv("ethaddr"); - if (eth_addr) + if (ret) return 0; + eth_addr = getenv("ethaddr"); + if (!eth_addr) + TAM3517_READ_MAC_FROM_EEPROM(&info); -#ifndef CONFIG_SPL_BUILD - TAM3517_READ_MAC_FROM_EEPROM; -#endif + TAM3517_PRINT_SOM_INFO(&info); return 0; } +#endif /* * Routine: set_muxconf_regs diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index f0eca54c9..ed4229e25 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -44,7 +44,7 @@ static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; /* MII mode defines */ #define MII_MODE_ENABLE 0x0 -#define RGMII_MODE_ENABLE 0xA +#define RGMII_MODE_ENABLE 0x3A /* GPIO that controls power to DDR on EVM-SK */ #define GPIO_DDR_VTT_EN 7 @@ -318,6 +318,8 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gpmc_init(); + return 0; } diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 8437ef515..02837082c 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -171,6 +171,25 @@ static struct module_pin_mux mii1_pin_mux[] = { {-1}, }; +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); @@ -257,6 +276,9 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) /* In profile #2 i2c1 and spi0 conflict. */ if (profile & ~PROFILE_2) configure_module_pin_mux(i2c1_pin_mux); + /* Profiles 2 & 3 don't have NAND */ + if (profile & ~(PROFILE_2 | PROFILE_3)) + configure_module_pin_mux(nand_pin_mux); else if (profile == PROFILE_2) { configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index f20ebed45..b829a792b 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -144,8 +144,7 @@ static int get_board_revision(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { int pop_mfr, pop_id; @@ -156,29 +155,29 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, */ identify_nand_chip(&pop_mfr, &pop_id); - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; switch (get_board_revision()) { case REVISION_C4: if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) { /* 512MB DDR */ - *mcfg = NUMONYX_V_MCFG_165(512 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(512 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) { /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) { /* Beagleboard Rev C5, 256MB DDR */ - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; } case REVISION_XM_A: @@ -186,24 +185,24 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, case REVISION_XM_C: if (pop_mfr == 0) { /* 256MB DDR */ - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } else { /* 512MB DDR */ - *mcfg = NUMONYX_V_MCFG_165(512 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(512 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } break; default: /* Assume 128MB and Micron/165MHz timings to be safe */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } } #endif diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 61fc7b553..8a3aa0c5b 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -128,8 +128,7 @@ int board_init(void) * provides the timing values back to the function that configures * the memory. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { int pop_mfr, pop_id; @@ -142,17 +141,17 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { /* 256MB DDR */ - *mcfg = HYNIX_V_MCFG_200(256 << 20); - *ctrla = HYNIX_V_ACTIMA_200; - *ctrlb = HYNIX_V_ACTIMB_200; + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; } else { /* 128MB DDR */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; } - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - *mr = MICRON_V_MR_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mr = MICRON_V_MR_165; } #endif diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 35f5e15fc..85685ee7c 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -188,16 +188,15 @@ int spl_start_uboot(void) * provides the timing values back to the function that configures * the memory. We have either one or two banks of 128MB DDR. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { /* General SDRC config */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; /* AC timings */ - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; } diff --git a/boards.cfg b/boards.cfg index 388e4a446..e4b0d44fa 100644 --- a/boards.cfg +++ b/boards.cfg @@ -99,6 +99,7 @@ at91sam9m10g45ek_nandflash arm arm926ejs at91sam9m10g45ek atmel at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH at91sam9rlek_nandflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH at91sam9x5ek_nandflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH +at91sam9x5ek_dataflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH at91sam9x5ek_spiflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH at91sam9x5ek_mmc arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 @@ -171,6 +172,7 @@ netspace_lite_v2 arm arm926ejs netspace_v2 LaCie netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2 netspace_mini_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MINI_V2 netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2 +wireless_space arm arm926ejs wireless_space LaCie kirkwood dreamplug arm arm926ejs - Marvell kirkwood guruplug arm arm926ejs - Marvell kirkwood mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood @@ -375,8 +377,8 @@ M5235EVB m68k mcf523x m5235evb freesca M5235EVB_Flash32 m68k mcf523x m5235evb freescale - M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 cobra5272 m68k mcf52x2 cobra5272 - idmr m68k mcf52x2 -eb_cpu5282 m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xFF000000 -eb_cpu5282_internal m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xF0000000 +eb_cpu5282 m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 +eb_cpu5282_internal m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 TASREG m68k mcf52x2 tasreg esd M5208EVBE m68k mcf52x2 m5208evbe freescale M5249EVB m68k mcf52x2 m5249evb freescale @@ -1091,6 +1093,7 @@ ecovec sh sh4 ecovec renesas MigoR sh sh4 MigoR renesas - r2dplus sh sh4 r2dplus renesas - r7780mp sh sh4 r7780mp renesas - +sh7752evb sh sh4 sh7752evb renesas - sh7757lcr sh sh4 sh7757lcr renesas - sh7763rdp sh sh4 sh7763rdp renesas - sh7785lcr sh sh4 sh7785lcr renesas - diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index f7595c031..1b8a8c156 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -592,12 +592,18 @@ int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_NEEDS_MANUAL_RELOC static int relocated = 0; - /* relocate boot function table */ if (!relocated) { int i; + + /* relocate boot function table */ for (i = 0; i < ARRAY_SIZE(boot_os); i++) if (boot_os[i] != NULL) boot_os[i] += gd->reloc_off; + + /* relocate names of sub-command table */ + for (i = 0; i < ARRAY_SIZE(cmd_bootm_sub); i++) + cmd_bootm_sub[i].name += gd->reloc_off; + relocated = 1; } #endif diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 4d64cfffd..0f3ffc84f 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -33,6 +33,9 @@ #include <dataflash.h> #endif #include <watchdog.h> +#include <linux/compiler.h> + +DECLARE_GLOBAL_DATA_PTR; static int mod_mem(cmd_tbl_t *, int, int, int, char * const []); @@ -1203,6 +1206,22 @@ U_BOOT_CMD( #endif +#ifdef CONFIG_CMD_MEMINFO +__weak void board_show_dram(ulong size) +{ + puts("DRAM: "); + print_size(size, "\n"); +} + +static int do_mem_info(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + board_show_dram(gd->ram_size); + + return 0; +} +#endif + U_BOOT_CMD( base, 2, 1, do_mem_base, "print or set address offset", @@ -1243,3 +1262,11 @@ U_BOOT_CMD( "[.b, .w, .l] address value delay(ms)" ); #endif /* CONFIG_MX_CYCLIC */ + +#ifdef CONFIG_CMD_MEMINFO +U_BOOT_CMD( + meminfo, 3, 1, do_mem_info, + "display memory information", + "" +); +#endif diff --git a/common/cmd_setexpr.c b/common/cmd_setexpr.c index 7b140deea..5a042951d 100644 --- a/common/cmd_setexpr.c +++ b/common/cmd_setexpr.c @@ -57,12 +57,22 @@ static int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int w; /* Validate arguments */ - if ((argc != 5) || (strlen(argv[3]) != 1)) + if (argc != 5 && argc != 3) + return CMD_RET_USAGE; + if (argc == 5 && strlen(argv[3]) != 1) return CMD_RET_USAGE; w = cmd_get_data_size(argv[0], 4); a = get_arg(argv[2], w); + + if (argc == 3) { + sprintf(buf, "%lx", a); + setenv(argv[1], buf); + + return 0; + } + b = get_arg(argv[4], w); switch (argv[3][0]) { @@ -87,8 +97,11 @@ static int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( setexpr, 5, 0, do_setexpr, "set environment variable as the result of eval expression", - "[.b, .w, .l] name value1 <op> value2\n" + "[.b, .w, .l] name [*]value1 <op> [*]value2\n" " - set environment variable 'name' to the result of the evaluated\n" " express specified by <op>. <op> can be &, |, ^, +, -, *, /, %\n" - " size argument is only meaningful if value1 and/or value2 are memory addresses" + " size argument is only meaningful if value1 and/or value2 are\n" + " memory addresses (*)\n" + "setexpr[.b, .w, .l] name *value\n" + " - load a memory address into a variable" ); diff --git a/common/cmd_sf.c b/common/cmd_sf.c index 5ac1d0c4c..b1753587d 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -5,6 +5,7 @@ * Licensed under the GPL-2 or later. */ +#include <div64.h> #include <common.h> #include <malloc.h> #include <spi_flash.h> @@ -67,6 +68,23 @@ static int sf_parse_len_arg(char *arg, ulong *len) return 1; } +/** + * This function takes a byte length and a delta unit of time to compute the + * approximate bytes per second + * + * @param len amount of bytes currently processed + * @param start_ms start time of processing in ms + * @return bytes per second if OK, 0 on error + */ +static ulong bytes_per_second(unsigned int len, ulong start_ms) +{ + /* less accurate but avoids overflow */ + if (len >= ((unsigned int) -1) / 1024) + return len / (max(get_timer(start_ms) / 1024, 1)); + else + return 1024 * len / max(get_timer(start_ms), 1); +} + static int do_spi_flash_probe(int argc, char * const argv[]) { unsigned int bus = CONFIG_SF_DEFAULT_BUS; @@ -167,11 +185,26 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset, const char *end = buf + len; size_t todo; /* number of bytes to do in this pass */ size_t skipped = 0; /* statistics */ + const ulong start_time = get_timer(0); + size_t scale = 1; + const char *start_buf = buf; + ulong delta; + if (end - buf >= 200) + scale = (end - buf) / 100; cmp_buf = malloc(flash->sector_size); if (cmp_buf) { + ulong last_update = get_timer(0); + for (; buf < end && !err_oper; buf += todo, offset += todo) { todo = min(end - buf, flash->sector_size); + if (get_timer(last_update) > 100) { + printf(" \rUpdating, %zu%% %lu B/s", + 100 - (end - buf) / scale, + bytes_per_second(buf - start_buf, + start_time)); + last_update = get_timer(0); + } err_oper = spi_flash_update_block(flash, offset, todo, buf, cmp_buf, &skipped); } @@ -179,12 +212,17 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset, err_oper = "malloc"; } free(cmp_buf); + putc('\r'); if (err_oper) { printf("SPI flash failed in %s step\n", err_oper); return 1; } - printf("%zu bytes written, %zu bytes skipped\n", len - skipped, - skipped); + + delta = get_timer(start_time); + printf("%zu bytes written, %zu bytes skipped", len - skipped, + skipped); + printf(" in %ld.%lds, speed %ld B/s\n", + delta / 1000, delta % 1000, bytes_per_second(len, start_time)); return 0; } @@ -275,6 +313,161 @@ static int do_spi_flash_erase(int argc, char * const argv[]) return 0; } +#ifdef CONFIG_CMD_SF_TEST +enum { + STAGE_ERASE, + STAGE_CHECK, + STAGE_WRITE, + STAGE_READ, + + STAGE_COUNT, +}; + +static char *stage_name[STAGE_COUNT] = { + "erase", + "check", + "write", + "read", +}; + +struct test_info { + int stage; + int bytes; + unsigned base_ms; + unsigned time_ms[STAGE_COUNT]; +}; + +static void show_time(struct test_info *test, int stage) +{ + uint64_t speed; /* KiB/s */ + int bps; /* Bits per second */ + + speed = (long long)test->bytes * 1000; + do_div(speed, test->time_ms[stage] * 1024); + bps = speed * 8; + + printf("%d %s: %d ticks, %d KiB/s %d.%03d Mbps\n", stage, + stage_name[stage], test->time_ms[stage], + (int)speed, bps / 1000, bps % 1000); +} + +static void spi_test_next_stage(struct test_info *test) +{ + test->time_ms[test->stage] = get_timer(test->base_ms); + show_time(test, test->stage); + test->base_ms = get_timer(0); + test->stage++; +} + +/** + * Run a test on the SPI flash + * + * @param flash SPI flash to use + * @param buf Source buffer for data to write + * @param len Size of data to read/write + * @param offset Offset within flash to check + * @param vbuf Verification buffer + * @return 0 if ok, -1 on error + */ +static int spi_flash_test(struct spi_flash *flash, char *buf, ulong len, + ulong offset, char *vbuf) +{ + struct test_info test; + int i; + + printf("SPI flash test:\n"); + memset(&test, '\0', sizeof(test)); + test.base_ms = get_timer(0); + test.bytes = len; + if (spi_flash_erase(flash, offset, len)) { + printf("Erase failed\n"); + return -1; + } + spi_test_next_stage(&test); + + if (spi_flash_read(flash, offset, len, vbuf)) { + printf("Check read failed\n"); + return -1; + } + for (i = 0; i < len; i++) { + if (vbuf[i] != 0xff) { + printf("Check failed at %d\n", i); + print_buffer(i, vbuf + i, 1, min(len - i, 0x40), 0); + return -1; + } + } + spi_test_next_stage(&test); + + if (spi_flash_write(flash, offset, len, buf)) { + printf("Write failed\n"); + return -1; + } + memset(vbuf, '\0', len); + spi_test_next_stage(&test); + + if (spi_flash_read(flash, offset, len, vbuf)) { + printf("Read failed\n"); + return -1; + } + spi_test_next_stage(&test); + + for (i = 0; i < len; i++) { + if (buf[i] != vbuf[i]) { + printf("Verify failed at %d, good data:\n", i); + print_buffer(i, buf + i, 1, min(len - i, 0x40), 0); + printf("Bad data:\n"); + print_buffer(i, vbuf + i, 1, min(len - i, 0x40), 0); + return -1; + } + } + printf("Test passed\n"); + for (i = 0; i < STAGE_COUNT; i++) + show_time(&test, i); + + return 0; +} + +static int do_spi_flash_test(int argc, char * const argv[]) +{ + unsigned long offset; + unsigned long len; + char *buf = (char *)CONFIG_SYS_TEXT_BASE; + char *endp; + char *vbuf; + int ret; + + offset = simple_strtoul(argv[1], &endp, 16); + if (*argv[1] == 0 || *endp != 0) + return -1; + len = simple_strtoul(argv[2], &endp, 16); + if (*argv[2] == 0 || *endp != 0) + return -1; + + vbuf = malloc(len); + if (!vbuf) { + printf("Cannot allocate memory\n"); + return 1; + } + buf = malloc(len); + if (!buf) { + free(vbuf); + printf("Cannot allocate memory\n"); + return 1; + } + + memcpy(buf, (char *)CONFIG_SYS_TEXT_BASE, len); + ret = spi_flash_test(flash, buf, len, offset, vbuf); + free(vbuf); + free(buf); + if (ret) { + printf("Test failed\n"); + return 1; + } + + return 0; +} +#endif /* CONFIG_CMD_SF_TEST */ + static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { const char *cmd; @@ -304,6 +497,10 @@ static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[ ret = do_spi_flash_read_write(argc, argv); else if (strcmp(cmd, "erase") == 0) ret = do_spi_flash_erase(argc, argv); +#ifdef CONFIG_CMD_SF_TEST + else if (!strcmp(cmd, "test")) + ret = do_spi_flash_test(argc, argv); +#endif else ret = -1; @@ -315,6 +512,13 @@ usage: return CMD_RET_USAGE; } +#ifdef CONFIG_CMD_SF_TEST +#define SF_TEST_HELP "\nsf test offset len " \ + "- run a very basic destructive test" +#else +#define SF_TEST_HELP +#endif + U_BOOT_CMD( sf, 5, 1, do_spi_flash, "SPI flash sub-system", @@ -328,4 +532,5 @@ U_BOOT_CMD( " `+len' round up `len' to block size\n" "sf update addr offset len - erase and write `len' bytes from memory\n" " at `addr' to flash at `offset'" + SF_TEST_HELP ); diff --git a/common/cmd_version.c b/common/cmd_version.c index ab4c560ae..e8f40d3ed 100644 --- a/common/cmd_version.c +++ b/common/cmd_version.c @@ -25,6 +25,9 @@ #include <command.h> #include <version.h> #include <linux/compiler.h> +#ifdef CONFIG_SYS_COREBOOT +#include <asm/arch/sysinfo.h> +#endif const char __weak version_string[] = U_BOOT_VERSION_STRING; @@ -37,7 +40,9 @@ static int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef LD_VERSION_STRING puts(LD_VERSION_STRING "\n"); #endif - +#ifdef CONFIG_SYS_COREBOOT + printf("coreboot-%s (%s)\n", lib_sysinfo.version, lib_sysinfo.build); +#endif return 0; } diff --git a/common/usb.c b/common/usb.c index ac9b4ca8d..6fc0fc1c0 100644 --- a/common/usb.c +++ b/common/usb.c @@ -805,6 +805,18 @@ struct usb_device *usb_alloc_new_device(void *controller) return &usb_dev[dev_index - 1]; } +/* + * Free the newly created device node. + * Called in error cases where configuring a newly attached + * device fails for some reason. + */ +void usb_free_device(void) +{ + dev_index--; + USB_PRINTF("Freeing device node: %d\n", dev_index); + memset(&usb_dev[dev_index], 0, sizeof(struct usb_device)); + usb_dev[dev_index].devnum = -1; +} /* * By the time we get here, the device has gotten a new device ID diff --git a/common/usb_hub.c b/common/usb_hub.c index e4a120120..b5eeb62fb 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -259,6 +259,8 @@ void usb_hub_port_connect_change(struct usb_device *dev, int port) /* Run it through the hoops (find a driver, etc) */ if (usb_new_device(usb)) { /* Woops, disable the port */ + usb_free_device(); + dev->children[port] = NULL; USB_HUB_PRINTF("hub: disabling port %d\n", port + 1); usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_ENABLE); } @@ -396,14 +398,37 @@ static int usb_hub_configure(struct usb_device *dev) for (i = 0; i < dev->maxchild; i++) { ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1); unsigned short portstatus, portchange; + int ret; + ulong start = get_timer(0); - if (usb_get_port_status(dev, i + 1, portsts) < 0) { - USB_HUB_PRINTF("get_port_status failed\n"); + /* + * Wait for (whichever finishes first) + * - A maximum of 10 seconds + * This is a purely observational value driven by connecting + * a few broken pen drives and taking the max * 1.5 approach + * - connection_change and connection state to report same + * state + */ + do { + ret = usb_get_port_status(dev, i + 1, portsts); + if (ret < 0) { + USB_HUB_PRINTF("get_port_status failed\n"); + break; + } + + portstatus = le16_to_cpu(portsts->wPortStatus); + portchange = le16_to_cpu(portsts->wPortChange); + + if ((portchange & USB_PORT_STAT_C_CONNECTION) == + (portstatus & USB_PORT_STAT_CONNECTION)) + break; + + mdelay(100); + } while (get_timer(start) < CONFIG_SYS_HZ * 10); + + if (ret < 0) continue; - } - portstatus = le16_to_cpu(portsts->wPortStatus); - portchange = le16_to_cpu(portsts->wPortChange); USB_HUB_PRINTF("Port %d Status %X Change %X\n", i + 1, portstatus, portchange); diff --git a/common/usb_storage.c b/common/usb_storage.c index 2d92ee1bb..fb322b401 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -970,6 +970,16 @@ static int usb_test_unit_ready(ccb *srb, struct us_data *ss) return 0; } usb_request_sense(srb, ss); + /* + * Check the Key Code Qualifier, if it matches + * "Not Ready - medium not present" + * (the sense Key equals 0x2 and the ASC is 0x3a) + * return immediately as the medium being absent won't change + * unless there is a user action. + */ + if ((srb->sense_buf[2] == 0x02) && + (srb->sense_buf[12] == 0x3a)) + return -1; mdelay(100); } while (retries--); diff --git a/doc/README.sh7752evb b/doc/README.sh7752evb new file mode 100644 index 000000000..c1fb54cdc --- /dev/null +++ b/doc/README.sh7752evb @@ -0,0 +1,67 @@ +======================================== +Renesas R0P7752C00000RZ board +======================================== + +This board specification: +========================= + +The R0P7752C00000RZ(board config name:sh7752evb) has the following device: + + - SH7752 (SH-4A) + - DDR3-SDRAM 512MB + - SPI ROM 8MB + - Gigabit Ethernet controllers + - eMMC 4GB + + +Configuration for This board: +============================= + +You can select the configuration as follows: + + - make sh7752evb_config + + +This board specific command: +============================ + +This board has the following its specific command: + + - write_mac + + +1. write_mac + +You can write MAC address to SPI ROM. + + Usage 1) Write MAC address + + write_mac [GETHERC ch0] [GETHERC ch1] + + For example) + => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f + *) We have to input the command as a single line + (without carriage return) + *) We have to reset after input the command. + + Usage 2) Show current data + + write_mac + + For example) + => write_mac + GETHERC ch0 = 74:90:50:00:33:9e + GETHERC ch1 = 74:90:50:00:33:9f + + +Update SPI ROM: +============================ + +1. Copy u-boot image to RAM area. +2. Probe SPI device. + => sf probe 0 + SF: Detected MX25L6405D with page size 64KiB, total 8 MiB +3. Erase SPI ROM. + => sf erase 0 80000 +4. Write u-boot image to SPI ROM. + => sf write 0x48000000 0 80000 diff --git a/doc/README.usb b/doc/README.usb index ef1d6ba36..b4c3ef522 100644 --- a/doc/README.usb +++ b/doc/README.usb @@ -63,7 +63,7 @@ Common USB Commands: Storage USB Commands: - usb scan: scans the USB for storage devices.The USB must be running for this command (usb start) -- usb device [dev]: show or set current USB staorage device +- usb device [dev]: show or set current USB storage device - usb part [dev]: print partition table of one or all USB storage devices - usb read addr blk# cnt: diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c index fc89f2a42..a30d7f060 100644 --- a/drivers/gpio/omap_gpio.c +++ b/drivers/gpio/omap_gpio.c @@ -53,18 +53,14 @@ static inline int get_gpio_index(int gpio) return gpio & 0x1f; } -static inline int gpio_valid(int gpio) +int gpio_is_valid(int gpio) { - if (gpio < 0) - return -1; - if (gpio < 192) - return 0; - return -1; + return (gpio >= 0) && (gpio < 192); } static int check_gpio(int gpio) { - if (gpio_valid(gpio) < 0) { + if (!gpio_is_valid(gpio)) { printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); return -1; } diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index af454f901..54e9b1586 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; #define I2C_TIMEOUT 1000 -static void wait_for_bb(void); +static int wait_for_bb(void); static u16 wait_for_pin(void); static void flush_fifo(void); @@ -159,7 +159,8 @@ static int i2c_read_byte(u8 devaddr, u16 regoffset, u8 alen, u8 *value) u16 w; /* wait until bus not busy */ - wait_for_bb(); + if (wait_for_bb()) + return 1; /* one byte only */ writew(alen, &i2c_base->cnt); @@ -263,7 +264,8 @@ int i2c_probe(uchar chip) return res; /* wait until bus not busy */ - wait_for_bb(); + if (wait_for_bb()) + return res; /* try to read one byte */ writew(1, &i2c_base->cnt); @@ -282,7 +284,10 @@ int i2c_probe(uchar chip) res = 1; writew(0xff, &i2c_base->stat); writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); - wait_for_bb (); + + if (wait_for_bb()) + res = 1; + break; } if (status & I2C_STAT_ARDY) { @@ -355,7 +360,8 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) } /* wait until bus not busy */ - wait_for_bb(); + if (wait_for_bb()) + return 1; /* start address phase - will write regoffset + len bytes data */ /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */ @@ -399,7 +405,7 @@ write_exit: return i2c_error; } -static void wait_for_bb(void) +static int wait_for_bb(void) { int timeout = I2C_TIMEOUT; u16 stat; @@ -413,8 +419,10 @@ static void wait_for_bb(void) if (timeout <= 0) { printf("timed out in wait_for_bb: I2C_STAT=%x\n", readw(&i2c_base->stat)); + return 1; } writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ + return 0; } static u16 wait_for_pin(void) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index e93e38ac4..3d5c9c0f7 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -577,7 +577,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) return -1; } - mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; + mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; if (caps & ESDHC_HOSTCAPBLT_HSS) mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index b2dfc5369..60dbb7864 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1128,7 +1128,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) AMD_CMD_ERASE_START); flash_unlock_seq (info, sect); flash_write_cmd (info, sect, 0, - AMD_CMD_ERASE_SECTOR); + info->cmd_erase_sector); break; #ifdef CONFIG_FLASH_CFI_LEGACY case CFI_CMDSET_AMD_LEGACY: @@ -1247,6 +1247,8 @@ void flash_print_info (flash_info_t * info) printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", info->device_id2); } + if ((info->vendor == CFI_CMDSET_AMD_STANDARD) && (info->legacy_unlock)) + printf("\n Advanced Sector Protection (PPB) enabled"); printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n", info->erase_blk_tout, info->write_tout); @@ -1425,13 +1427,18 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) return flash_write_cfiword (info, wp, cword); } +static inline int manufact_match(flash_info_t *info, u32 manu) +{ + return info->manufacturer_id == ((manu & FLASH_VENDMASK) >> 16); +} + /*----------------------------------------------------------------------- */ #ifdef CONFIG_SYS_FLASH_PROTECTION static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot) { - if (info->manufacturer_id == ((INTEL_MANUFACT & FLASH_VENDMASK) >> 16) + if (manufact_match(info, INTEL_MANUFACT) && info->device_id == NUMONYX_256MBIT) { /* * see errata called @@ -1488,8 +1495,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) case CFI_CMDSET_AMD_EXTENDED: case CFI_CMDSET_AMD_STANDARD: /* U-Boot only checks the first byte */ - if (info->manufacturer_id == - ((ATM_MANUFACT & FLASH_VENDMASK) >> 16)) { + if (manufact_match(info, ATM_MANUFACT)) { if (prot) { flash_unlock_seq (info, 0); flash_write_cmd (info, 0, @@ -1507,8 +1513,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) 0, ATM_CMD_UNLOCK_SECT); } } - if (info->manufacturer_id == - ((AMD_MANUFACT & FLASH_VENDMASK) >> 16)) { + if (info->legacy_unlock) { int flag = disable_interrupts(); int lock_flag; @@ -1733,18 +1738,15 @@ static void cmdset_amd_read_jedec_ids(flash_info_t *info) static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) { info->cmd_reset = AMD_CMD_RESET; + info->cmd_erase_sector = AMD_CMD_ERASE_SECTOR; cmdset_amd_read_jedec_ids(info); flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); #ifdef CONFIG_SYS_FLASH_PROTECTION - if (info->ext_addr && info->manufacturer_id == - ((AMD_MANUFACT & FLASH_VENDMASK) >> 16)) { - ushort spus; - - /* read sector protect/unprotect scheme */ - spus = flash_read_uchar(info, info->ext_addr + 9); - if (spus == 0x8) + if (info->ext_addr) { + /* read sector protect/unprotect scheme (at 0x49) */ + if (flash_read_uchar(info, info->ext_addr + 9) == 0x8) info->legacy_unlock = 1; } #endif @@ -2003,6 +2005,25 @@ static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry) } } +static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry) +{ + /* + * SST, for many recent nor parallel flashes, says they are + * CFI-conformant. This is not true, since qry struct. + * reports a std. AMD command set (0x0002), while SST allows to + * erase two different sector sizes for the same memory. + * 64KB sector (SST call it block) needs 0x30 to be erased. + * 4KB sector (SST call it sector) needs 0x50 to be erased. + * Since CFI query detect the 4KB number of sectors, users expects + * a sector granularity of 4KB, and it is here set. + */ + if (info->device_id == 0x5D23 || /* SST39VF3201B */ + info->device_id == 0x5C23) { /* SST39VF3202B */ + /* set sector granularity to 4KB */ + info->cmd_erase_sector=0x50; + } +} + /* * The following code cannot be run from FLASH! * @@ -2081,6 +2102,9 @@ ulong flash_get_size (phys_addr_t base, int banknum) case 0x0020: flash_fixup_stm(info, &qry); break; + case 0x00bf: /* SST */ + flash_fixup_sst(info, &qry); + break; } debug ("manufacturer is %d\n", info->vendor); @@ -2158,6 +2182,27 @@ ulong flash_get_size (phys_addr_t base, int banknum) FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); break; + case CFI_CMDSET_AMD_EXTENDED: + case CFI_CMDSET_AMD_STANDARD: + if (!info->legacy_unlock) { + /* default: not protected */ + info->protect[sect_cnt] = 0; + break; + } + + /* Read protection (PPB) from sector */ + flash_write_cmd(info, 0, 0, + info->cmd_reset); + flash_unlock_seq(info, 0); + flash_write_cmd(info, 0, + info->addr_unlock1, + FLASH_CMD_READ_ID); + info->protect[sect_cnt] = + flash_isset( + info, sect_cnt, + FLASH_OFFSET_PROTECT, + FLASH_STATUS_PROTECT); + break; default: /* default: not protected */ info->protect[sect_cnt] = 0; diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 28e52bd08..c77c0c4f0 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -33,6 +33,7 @@ ifdef CONFIG_SPL_NAND_DRIVERS NORMAL_DRIVERS=y endif +COBJS-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o COBJS-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c new file mode 100644 index 000000000..b84528ba3 --- /dev/null +++ b/drivers/mtd/nand/am335x_spl_bch.c @@ -0,0 +1,238 @@ +/* + * (C) Copyright 2012 + * Konstantin Kozhevnikov, Cogent Embedded + * + * based on nand_spl_simple code + * + * (C) Copyright 2006-2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <common.h> +#include <nand.h> +#include <asm/io.h> +#include <linux/mtd/nand_ecc.h> + +static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; +static nand_info_t mtd; +static struct nand_chip nand_chip; + +#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES) + + +/* + * NAND command for large page NAND devices (2k) + */ +static int nand_command(int block, int page, uint32_t offs, + u8 cmd) +{ + struct nand_chip *this = mtd.priv; + int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + void (*hwctrl)(struct mtd_info *mtd, int cmd, + unsigned int ctrl) = this->cmd_ctrl; + + while (!this->dev_ready(&mtd)) + ; + + /* Emulate NAND_CMD_READOOB */ + if (cmd == NAND_CMD_READOOB) { + offs += CONFIG_SYS_NAND_PAGE_SIZE; + cmd = NAND_CMD_READ0; + } + + /* Begin command latch cycle */ + hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + + if (cmd == NAND_CMD_RESET) { + hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + while (!this->dev_ready(&mtd)) + ; + return 0; + } + + /* Shift the offset from byte addressing to word addressing. */ + if (this->options & NAND_BUSWIDTH_16) + offs >>= 1; + + /* Set ALE and clear CLE to start address cycle */ + /* Column address */ + hwctrl(&mtd, offs & 0xff, + NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ + hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ + /* Row address */ + hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ + hwctrl(&mtd, ((page_addr >> 8) & 0xff), + NAND_CTRL_ALE); /* A[27:20] */ +#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE + /* One more address cycle for devices > 128MiB */ + hwctrl(&mtd, (page_addr >> 16) & 0x0f, + NAND_CTRL_ALE); /* A[31:28] */ +#endif + hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + + if (cmd == NAND_CMD_READ0) { + /* Latch in address */ + hwctrl(&mtd, NAND_CMD_READSTART, + NAND_CTRL_CLE | NAND_CTRL_CHANGE); + hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + + /* + * Wait a while for the data to be ready + */ + while (!this->dev_ready(&mtd)) + ; + } else if (cmd == NAND_CMD_RNDOUT) { + hwctrl(&mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE | + NAND_CTRL_CHANGE); + hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + } + + return 0; +} + +static int nand_is_bad_block(int block) +{ + struct nand_chip *this = mtd.priv; + + nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, + NAND_CMD_READOOB); + + /* + * Read one byte (or two if it's a 16 bit chip). + */ + if (this->options & NAND_BUSWIDTH_16) { + if (readw(this->IO_ADDR_R) != 0xffff) + return 1; + } else { + if (readb(this->IO_ADDR_R) != 0xff) + return 1; + } + + return 0; +} + +static int nand_read_page(int block, int page, void *dst) +{ + struct nand_chip *this = mtd.priv; + u_char ecc_calc[ECCTOTAL]; + u_char ecc_code[ECCTOTAL]; + u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; + int i; + int eccsize = CONFIG_SYS_NAND_ECCSIZE; + int eccbytes = CONFIG_SYS_NAND_ECCBYTES; + int eccsteps = ECCSTEPS; + uint8_t *p = dst; + uint32_t data_pos = 0; + uint8_t *oob = &oob_data[0] + nand_ecc_pos[0]; + uint32_t oob_pos = eccsize * eccsteps + nand_ecc_pos[0]; + + nand_command(block, page, 0, NAND_CMD_READ0); + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + this->ecc.hwctl(&mtd, NAND_ECC_READ); + nand_command(block, page, data_pos, NAND_CMD_RNDOUT); + + this->read_buf(&mtd, p, eccsize); + + nand_command(block, page, oob_pos, NAND_CMD_RNDOUT); + + this->read_buf(&mtd, oob, eccbytes); + this->ecc.calculate(&mtd, p, &ecc_calc[i]); + + data_pos += eccsize; + oob_pos += eccbytes; + oob += eccbytes; + } + + /* Pick the ECC bytes out of the oob data */ + for (i = 0; i < ECCTOTAL; i++) + ecc_code[i] = oob_data[nand_ecc_pos[i]]; + + eccsteps = ECCSTEPS; + p = dst; + + for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + /* No chance to do something with the possible error message + * from correct_data(). We just hope that all possible errors + * are corrected by this routine. + */ + this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]); + } + + return 0; +} + +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) +{ + unsigned int block, lastblock; + unsigned int page; + + /* + * offs has to be aligned to a page address! + */ + block = offs / CONFIG_SYS_NAND_BLOCK_SIZE; + lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE; + page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE; + + while (block <= lastblock) { + if (!nand_is_bad_block(block)) { + /* + * Skip bad blocks + */ + while (page < CONFIG_SYS_NAND_PAGE_COUNT) { + nand_read_page(block, page, dst); + dst += CONFIG_SYS_NAND_PAGE_SIZE; + page++; + } + + page = 0; + } else { + lastblock++; + } + + block++; + } + + return 0; +} + +/* nand_init() - initialize data to make nand usable by SPL */ +void nand_init(void) +{ + /* + * Init board specific nand support + */ + mtd.priv = &nand_chip; + nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = + (void __iomem *)CONFIG_SYS_NAND_BASE; + board_nand_init(&nand_chip); + + if (nand_chip.select_chip) + nand_chip.select_chip(&mtd, 0); + + /* NAND chip may require reset after power-on */ + nand_command(0, 0, 0, NAND_CMD_RESET); +} + +/* Unselect after operation */ +void nand_deselect(void) +{ + if (nand_chip.select_chip) + nand_chip.select_chip(&mtd, -1); +} diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 0878bece6..b13d8a930 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -391,7 +391,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, timing = IFC_FIR_OP_RBCD; out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | (timing << IFC_NAND_FIR0_OP2_SHIFT)); out_be32(&ifc->ifc_nand.nand_fcr0, @@ -758,7 +758,7 @@ static void fsl_ifc_sram_init(void) /* READID */ out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); out_be32(&ifc->ifc_nand.nand_fcr0, diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index f1469d110..cee394ece 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -29,6 +29,9 @@ #include <linux/mtd/nand_ecc.h> #include <linux/compiler.h> #include <nand.h> +#ifdef CONFIG_AM33XX +#include <asm/arch/elm.h> +#endif static uint8_t cs; static __maybe_unused struct nand_ecclayout hw_nand_oob = @@ -234,6 +237,370 @@ static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) } } +/* + * BCH8 support (needs ELM and thus AM33xx-only) + */ +#ifdef CONFIG_AM33XX +struct nand_bch_priv { + uint8_t mode; + uint8_t type; + uint8_t nibbles; +}; + +/* bch types */ +#define ECC_BCH4 0 +#define ECC_BCH8 1 +#define ECC_BCH16 2 + +/* BCH nibbles for diff bch levels */ +#define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1) +#define ECC_BCH4_NIBBLES 13 +#define ECC_BCH8_NIBBLES 26 +#define ECC_BCH16_NIBBLES 52 + +static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT; + +static struct nand_bch_priv bch_priv = { + .mode = NAND_ECC_HW_BCH, + .type = ECC_BCH8, + .nibbles = ECC_BCH8_NIBBLES +}; + +/* + * omap_read_bch8_result - Read BCH result for BCH8 level + * + * @mtd: MTD device structure + * @big_endian: When set read register 3 first + * @ecc_code: Read syndrome from BCH result registers + */ +static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian, + uint8_t *ecc_code) +{ + uint32_t *ptr; + int8_t i = 0, j; + + if (big_endian) { + ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3]; + ecc_code[i++] = readl(ptr) & 0xFF; + ptr--; + for (j = 0; j < 3; j++) { + ecc_code[i++] = (readl(ptr) >> 24) & 0xFF; + ecc_code[i++] = (readl(ptr) >> 16) & 0xFF; + ecc_code[i++] = (readl(ptr) >> 8) & 0xFF; + ecc_code[i++] = readl(ptr) & 0xFF; + ptr--; + } + } else { + ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0]; + for (j = 0; j < 3; j++) { + ecc_code[i++] = readl(ptr) & 0xFF; + ecc_code[i++] = (readl(ptr) >> 8) & 0xFF; + ecc_code[i++] = (readl(ptr) >> 16) & 0xFF; + ecc_code[i++] = (readl(ptr) >> 24) & 0xFF; + ptr++; + } + ecc_code[i++] = readl(ptr) & 0xFF; + ecc_code[i++] = 0; /* 14th byte is always zero */ + } +} + +/* + * omap_ecc_disable - Disable H/W ECC calculation + * + * @mtd: MTD device structure + * + */ +static void omap_ecc_disable(struct mtd_info *mtd) +{ + writel((readl(&gpmc_cfg->ecc_config) & ~0x1), + &gpmc_cfg->ecc_config); +} + +/* + * omap_rotate_ecc_bch - Rotate the syndrome bytes + * + * @mtd: MTD device structure + * @calc_ecc: ECC read from ECC registers + * @syndrome: Rotated syndrome will be retuned in this array + * + */ +static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc, + uint8_t *syndrome) +{ + struct nand_chip *chip = mtd->priv; + struct nand_bch_priv *bch = chip->priv; + uint8_t n_bytes = 0; + int8_t i, j; + + switch (bch->type) { + case ECC_BCH4: + n_bytes = 8; + break; + + case ECC_BCH16: + n_bytes = 28; + break; + + case ECC_BCH8: + default: + n_bytes = 13; + break; + } + + for (i = 0, j = (n_bytes-1); i < n_bytes; i++, j--) + syndrome[i] = calc_ecc[j]; +} + +/* + * omap_calculate_ecc_bch - Read BCH ECC result + * + * @mtd: MTD structure + * @dat: unused + * @ecc_code: ecc_code buffer + */ +static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, + uint8_t *ecc_code) +{ + struct nand_chip *chip = mtd->priv; + struct nand_bch_priv *bch = chip->priv; + uint8_t big_endian = 1; + int8_t ret = 0; + + if (bch->type == ECC_BCH8) + omap_read_bch8_result(mtd, big_endian, ecc_code); + else /* BCH4 and BCH16 currently not supported */ + ret = -1; + + /* + * Stop reading anymore ECC vals and clear old results + * enable will be called if more reads are required + */ + omap_ecc_disable(mtd); + + return ret; +} + +/* + * omap_fix_errors_bch - Correct bch error in the data + * + * @mtd: MTD device structure + * @data: Data read from flash + * @error_count:Number of errors in data + * @error_loc: Locations of errors in the data + * + */ +static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data, + uint32_t error_count, uint32_t *error_loc) +{ + struct nand_chip *chip = mtd->priv; + struct nand_bch_priv *bch = chip->priv; + uint8_t count = 0; + uint32_t error_byte_pos; + uint32_t error_bit_mask; + uint32_t last_bit = (bch->nibbles * 4) - 1; + + /* Flip all bits as specified by the error location array. */ + /* FOR( each found error location flip the bit ) */ + for (count = 0; count < error_count; count++) { + if (error_loc[count] > last_bit) { + /* Remove the ECC spare bits from correction. */ + error_loc[count] -= (last_bit + 1); + /* Offset bit in data region */ + error_byte_pos = ((512 * 8) - + (error_loc[count]) - 1) / 8; + /* Error Bit mask */ + error_bit_mask = 0x1 << (error_loc[count] % 8); + /* Toggle the error bit to make the correction. */ + data[error_byte_pos] ^= error_bit_mask; + } + } +} + +/* + * omap_correct_data_bch - Compares the ecc read from nand spare area + * with ECC registers values and corrects one bit error if it has occured + * + * @mtd: MTD device structure + * @dat: page data + * @read_ecc: ecc read from nand flash (ignored) + * @calc_ecc: ecc read from ECC registers + * + * @return 0 if data is OK or corrected, else returns -1 + */ +static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, + uint8_t *read_ecc, uint8_t *calc_ecc) +{ + struct nand_chip *chip = mtd->priv; + struct nand_bch_priv *bch = chip->priv; + uint8_t syndrome[28]; + uint32_t error_count = 0; + uint32_t error_loc[8]; + uint32_t i, ecc_flag; + + ecc_flag = 0; + for (i = 0; i < chip->ecc.bytes; i++) + if (read_ecc[i] != 0xff) + ecc_flag = 1; + + if (!ecc_flag) + return 0; + + elm_reset(); + elm_config((enum bch_level)(bch->type)); + + /* + * while reading ECC result we read it in big endian. + * Hence while loading to ELM we have rotate to get the right endian. + */ + omap_rotate_ecc_bch(mtd, calc_ecc, syndrome); + + /* use elm module to check for errors */ + if (elm_check_error(syndrome, bch->nibbles, &error_count, + error_loc) != 0) { + printf("ECC: uncorrectable.\n"); + return -1; + } + + /* correct bch error */ + if (error_count > 0) + omap_fix_errors_bch(mtd, dat, error_count, error_loc); + + return 0; +} +/* + * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in + * GPMC controller + * @mtd: MTD device structure + * @mode: Read/Write mode + */ +static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) +{ + uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; + uint32_t unused_length = 0; + struct nand_bch_priv *bch = chip->priv; + + switch (bch->nibbles) { + case ECC_BCH4_NIBBLES: + unused_length = 3; + break; + case ECC_BCH8_NIBBLES: + unused_length = 2; + break; + case ECC_BCH16_NIBBLES: + unused_length = 0; + break; + } + + /* Clear the ecc result registers, select ecc reg as 1 */ + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); + + switch (mode) { + case NAND_ECC_WRITE: + /* eccsize1 config */ + val = ((unused_length + bch->nibbles) << 22); + break; + + case NAND_ECC_READ: + default: + /* by default eccsize0 selected for ecc1resultsize */ + /* eccsize0 config */ + val = (bch->nibbles << 12); + /* eccsize1 config */ + val |= (unused_length << 22); + break; + } + /* ecc size configuration */ + writel(val, &gpmc_cfg->ecc_size_config); + /* by default 512bytes sector page is selected */ + /* set bch mode */ + val = (1 << 16); + /* bch4 / bch8 / bch16 */ + val |= (bch->type << 12); + /* set wrap mode to 1 */ + val |= (1 << 8); + val |= (dev_width << 7); + val |= (cs << 1); + writel(val, &gpmc_cfg->ecc_config); +} + +/* + * omap_enable_ecc_bch- This function enables the bch h/w ecc functionality + * @mtd: MTD device structure + * @mode: Read/Write mode + * + */ +static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode) +{ + struct nand_chip *chip = mtd->priv; + + omap_hwecc_init_bch(chip, mode); + /* enable ecc */ + writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config); +} + +/** + * omap_read_page_bch - hardware ecc based page read function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @page: page number to read + * + */ +static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page) +{ + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + uint8_t *p = buf; + uint8_t *ecc_calc = chip->buffers->ecccalc; + uint8_t *ecc_code = chip->buffers->ecccode; + uint32_t *eccpos = chip->ecc.layout->eccpos; + uint8_t *oob = chip->oob_poi; + uint32_t data_pos; + uint32_t oob_pos; + + data_pos = 0; + /* oob area start */ + oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0]; + oob += chip->ecc.layout->eccpos[0]; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize, + oob += eccbytes) { + chip->ecc.hwctl(mtd, NAND_ECC_READ); + /* read data */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page); + chip->read_buf(mtd, p, eccsize); + + /* read respective ecc from oob area */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page); + chip->read_buf(mtd, oob, eccbytes); + /* read syndrome */ + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + data_pos += eccsize; + oob_pos += eccbytes; + } + + for (i = 0; i < chip->ecc.total; i++) + ecc_code[i] = chip->oob_poi[eccpos[i]]; + + eccsteps = chip->ecc.steps; + p = buf; + + for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + int stat; + + stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + return 0; +} +#endif /* CONFIG_AM33XX */ + #ifndef CONFIG_SPL_BUILD /* * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc. @@ -269,7 +636,7 @@ void omap_nand_switch_ecc(int32_t hardware) nand->ecc.calculate = NULL; /* Setup the ecc configurations again */ - if (hardware) { + if (hardware == 1) { nand->ecc.mode = NAND_ECC_HW; nand->ecc.layout = &hw_nand_oob; nand->ecc.size = 512; @@ -279,6 +646,19 @@ void omap_nand_switch_ecc(int32_t hardware) nand->ecc.calculate = omap_calculate_ecc; omap_hwecc_init(nand); printf("HW ECC selected\n"); +#ifdef CONFIG_AM33XX + } else if (hardware == 2) { + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &hw_bch8_nand_oob; + nand->ecc.size = 512; + nand->ecc.bytes = 14; + nand->ecc.read_page = omap_read_page_bch; + nand->ecc.hwctl = omap_enable_ecc_bch; + nand->ecc.correct = omap_correct_data_bch; + nand->ecc.calculate = omap_calculate_ecc_bch; + omap_hwecc_init_bch(nand, NAND_ECC_READ); + printf("HW BCH8 selected\n"); +#endif } else { nand->ecc.mode = NAND_ECC_SOFT; /* Use mtd default settings */ @@ -350,7 +730,27 @@ int board_nand_init(struct nand_chip *nand) nand->options |= NAND_BUSWIDTH_16; nand->chip_delay = 100; + +#ifdef CONFIG_AM33XX + /* required in case of BCH */ + elm_init(); + + /* BCH info that will be correct for SPL or overridden otherwise. */ + nand->priv = &bch_priv; +#endif + /* Default ECC mode */ +#ifdef CONFIG_AM33XX + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &hw_bch8_nand_oob; + nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; + nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; + nand->ecc.hwctl = omap_enable_ecc_bch; + nand->ecc.correct = omap_correct_data_bch; + nand->ecc.calculate = omap_calculate_ecc_bch; + nand->ecc.read_page = omap_read_page_bch; + omap_hwecc_init_bch(nand, NAND_ECC_READ); +#else #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC) nand->ecc.mode = NAND_ECC_SOFT; #else @@ -363,6 +763,7 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.calculate = omap_calculate_ecc; omap_hwecc_init(nand); #endif +#endif #ifdef CONFIG_SPL_BUILD if (nand->options & NAND_BUSWIDTH_16) diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index af3d8593e..db04795df 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -920,7 +920,10 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave) SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full); - phydev = phy_connect(priv->bus, 0, dev, slave->data->phy_if); + phydev = phy_connect(priv->bus, + CONFIG_PHY_ADDR, + dev, + slave->data->phy_if); phydev->supported &= supported; phydev->advertising = phydev->supported; diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 483a920fc..e8da66d63 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -26,6 +26,14 @@ #include <netdev.h> #include "mv88e61xx.h" +/* + * Uncomment either of the following line for local debug control; + * otherwise global debug control will apply. + */ + +/* #undef DEBUG */ +/* #define DEBUG */ + #ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE /* Chip Address mode * The Switch support two modes of operation @@ -52,7 +60,8 @@ static int mv88e61xx_busychk_multic(char *name, u32 devaddr) return 0; } -static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) +static void mv88e61xx_switch_write(char *name, u32 phy_adr, + u32 reg_ofs, u16 data) { u16 mii_dev_addr; @@ -70,7 +79,8 @@ static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) 15)); } -static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) +static void mv88e61xx_switch_read(char *name, u32 phy_adr, + u32 reg_ofs, u16 *data) { u16 mii_dev_addr; @@ -90,110 +100,51 @@ static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) } #endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ -static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig, - u32 max_prtnum, u32 ports_ofs) -{ - u32 prt; - u16 reg; - char *name = swconfig->name; - u32 cpu_port = swconfig->cpuport; - u32 port_mask = swconfig->ports_enabled; - enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg; - - /* be sure all ports are disabled */ - for (prt = 0; prt < max_prtnum; prt++) { - RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, ®); - reg &= ~0x3; - WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg); - - if (!(cpu_port & (1 << prt))) - continue; - /* Set CPU port VID to 0x1 */ - RD_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, ®); - reg &= ~0xfff; - reg |= 0x1; - WR_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, reg); - } - - /* Setting Port default priority for all ports to zero */ - for (prt = 0; prt < max_prtnum; prt++) { - RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, ®); - reg &= ~0xc000; - WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg); - } - /* Setting VID and VID map for all ports except CPU port */ - for (prt = 0; prt < max_prtnum; prt++) { - /* only for enabled ports */ - if ((1 << prt) & port_mask) { - /* skip CPU port */ - if ((1 << prt) & cpu_port) { - /* - * Set Vlan map table for cpu_port to see - * all ports - */ - RD_PHY(name, (ports_ofs + prt), - MV88E61XX_PRT_VMAP_REG, ®); - reg &= ~((1 << max_prtnum) - 1); - reg |= port_mask & ~(1 << prt); - WR_PHY(name, (ports_ofs + prt), - MV88E61XX_PRT_VMAP_REG, reg); - } else { - - /* - * set Ports VLAN Mapping. - * port prt <--> cpu_port VLAN #prt+1. - */ - RD_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_VID_REG, ®); - reg &= ~0x0fff; - reg |= (prt + 1); - WR_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_VID_REG, reg); - - RD_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_VMAP_REG, ®); - if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) { - /* - * all any port can send frames to all other ports - * ref: sec 3.2.1.1 of datasheet - */ - reg |= 0x03f; - reg &= ~(1 << prt); - } else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) { - /* - * all other ports can send frames to CPU port only - * ref: sec 3.2.1.2 of datasheet - */ - reg &= ~((1 << max_prtnum) - 1); - reg |= cpu_port; - } - WR_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_VMAP_REG, reg); - } - } - } +/* + * Convenience macros for switch device/port reads/writes + * These macros output valid 'mv88e61xx' U_BOOT_CMDs + */ - /* - * enable only appropriate ports to forwarding mode - * and disable the others - */ - for (prt = 0; prt < max_prtnum; prt++) { - if ((1 << prt) & port_mask) { - RD_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_CTRL_REG, ®); - reg |= 0x3; - WR_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_CTRL_REG, reg); - } else { - /* Disable port */ - RD_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_CTRL_REG, ®); - reg &= ~0x3; - WR_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_CTRL_REG, reg); - } - } +#ifndef DEBUG +#define WR_SWITCH_REG wr_switch_reg +#define RD_SWITCH_REG rd_switch_reg +#define WR_SWITCH_PORT_REG(n, p, r, d) \ + WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d) +#define RD_SWITCH_PORT_REG(n, p, r, d) \ + RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d) +#else +static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data) +{ + printf("mv88e61xx %s dev %02x reg %02x write %04x\n", + name, dev_adr, reg_ofs, data); + wr_switch_reg(name, dev_adr, reg_ofs, data); } +static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data) +{ + rd_switch_reg(name, dev_adr, reg_ofs, data); + printf("mv88e61xx %s dev %02x reg %02x read %04x\n", + name, dev_adr, reg_ofs, *data); +} +static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs, + u16 data) +{ + printf("mv88e61xx %s port %02x reg %02x write %04x\n", + name, prt_adr, reg_ofs, data); + wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data); +} +static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs, + u16 *data) +{ + rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data); + printf("mv88e61xx %s port %02x reg %02x read %04x\n", + name, prt_adr, reg_ofs, *data); +} +#endif + +/* + * Local functions to read/write registers on the switch PHYs. + * NOTE! This goes through switch, not direct miiphy, writes and reads! + */ /* * Make sure SMIBusy bit cleared before another @@ -204,7 +155,7 @@ static int mv88e61xx_busychk(char *name) u16 reg = 0; u32 timeout = MV88E61XX_PHY_TIMEOUT; do { - RD_PHY(name, MV88E61XX_GLB2REG_DEVADR, + rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, ®); if (timeout-- == 0) { printf("SMI busy timeout\n"); @@ -214,34 +165,110 @@ static int mv88e61xx_busychk(char *name) return 0; } +static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy, + u32 reg, u16 data) +{ + /* write switch data reg then cmd reg then check completion */ + wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, + data); + wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, + (MV88E61XX_PHY_WRITE_CMD | (phy << 5) | reg)); + return mv88e61xx_busychk(name); +} + +static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy, + u32 reg, u16 *data) +{ + /* write switch cmd reg, check for completion */ + wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, + (MV88E61XX_PHY_READ_CMD | (phy << 5) | reg)); + if (mv88e61xx_busychk(name)) + return -1; + /* read switch data reg and return success */ + rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data); + return 0; +} + +/* + * Convenience macros for switch PHY reads/writes + */ + +#ifndef DEBUG +#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write +#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read +#else +static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr, + u32 reg_ofs, u16 data) +{ + int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data); + if (r) + printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n", + name, phy_adr, reg_ofs); + else + printf("mv88e61xx %s phy %02x reg %02x write %04x\n", + name, phy_adr, reg_ofs, data); + return r; +} +static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr, + u32 reg_ofs, u16 *data) +{ + int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data); + if (r) + printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n", + name, phy_adr, reg_ofs); + else + printf("mv88e61xx %s phy %02x reg %02x read %04x\n", + name, phy_adr, reg_ofs, *data); + return r; +} +#endif + +static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig) +{ + u32 prt; + u16 reg; + char *name = swconfig->name; + u32 port_mask = swconfig->ports_enabled; + + /* apply internal vlan config */ + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + /* only for enabled ports */ + if ((1 << prt) & port_mask) { + /* take vlan map from swconfig */ + u8 vlanmap = swconfig->vlancfg[prt]; + /* remove disabled ports from vlan map */ + vlanmap &= swconfig->ports_enabled; + /* apply vlan map to port */ + RD_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_VMAP_REG, ®); + reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1); + reg |= vlanmap; + WR_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_VMAP_REG, reg); + } + } +} + /* * Power up the specified port and reset PHY */ -static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt) +static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy) { char *name = swconfig->name; - /* Write Copper Specific control reg1 (0x14) for- + /* Write Copper Specific control reg1 (0x10) for- * Enable Phy power up * Energy Detect on (sense&Xmit NLP Periodically * reset other settings default */ - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x3360); - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, (0x9410 | (prt << 5))); - - if (mv88e61xx_busychk(name)) + if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360)) return -1; /* Write PHY ctrl reg (0x0) to apply * Phy reset (set bit 15 low) * reset other default values */ - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x1140); - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, (0x9400 | (prt << 5))); - - if (mv88e61xx_busychk(name)) + if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140)) return -1; return 0; @@ -256,48 +283,26 @@ static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt) * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s * Link status */ -static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt) +static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy) { char *name = swconfig->name; - u16 reg; if (swconfig->led_init != MV88E61XX_LED_INIT_EN) return 0; /* set page address to 3 */ - reg = 3; - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | - 1 << MV88E61XX_MODE_OFST | - 1 << MV88E61XX_OP_OFST | - prt << MV88E61XX_ADDR_OFST | 22)); - - if (mv88e61xx_busychk(name)) + if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003)) return -1; - /* set LED Func Ctrl reg */ - reg = 1; /* LED[0] On-Link, Blink-Activity, Off-NoLink */ - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | - 1 << MV88E61XX_MODE_OFST | - 1 << MV88E61XX_OP_OFST | - prt << MV88E61XX_ADDR_OFST | 16)); - - if (mv88e61xx_busychk(name)) + /* + * set LED Func Ctrl reg + * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink + */ + if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001)) return -1; /* set page address to 0 */ - reg = 0; - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | - 1 << MV88E61XX_MODE_OFST | - 1 << MV88E61XX_OP_OFST | - prt << MV88E61XX_ADDR_OFST | 22)); - - if (mv88e61xx_busychk(name)) + if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000)) return -1; return 0; @@ -312,23 +317,15 @@ static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt) * This is optional settings may be needed on some boards * for PHY<->magnetics h/w tuning */ -static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 prt) +static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy) { char *name = swconfig->name; - u16 reg; if (swconfig->mdip != MV88E61XX_MDIP_REVERSE) return 0; - reg = 0x0f; /*Reverse MDIP/N[3:0] bits */ - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | - 1 << MV88E61XX_MODE_OFST | - 1 << MV88E61XX_OP_OFST | - prt << MV88E61XX_ADDR_OFST | 20)); - - if (mv88e61xx_busychk(name)) + /*Reverse MDIP/N[3:0] bits */ + if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f)) return -1; return 0; @@ -343,6 +340,7 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) u16 reg; char *idstr; char *name = swconfig->name; + int time; if (miiphy_set_current_dev(name)) { printf("%s failed\n", __FUNCTION__); @@ -354,7 +352,7 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) printf("Invalid cpu port config, using default port5\n"); } - RD_PHY(name, MV88E61XX_PRT_OFST, MII_PHYSID2, ®); + RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, ®); switch (reg &= 0xfff0) { case 0x1610: idstr = "88E6161"; @@ -373,46 +371,183 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) break; } - /* Port based VLANs configuration */ - if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT) - || (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER)) - mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM, - MV88E61XX_PRT_OFST); - else { - printf("Unsupported mode %s failed\n", __FUNCTION__); - return -1; + /* be sure all ports are disabled */ + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, ®); + reg &= ~0x3; + WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg); } + /* wait 2 ms for queues to drain */ + udelay(2000); + + /* reset switch */ + RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, ®); + reg |= 0x8000; + WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg); + + /* wait up to 1 second for switch reset complete */ + for (time = 1000; time; time--) { + RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR, + ®); + if ((reg & 0xc800) == 0xc800) + break; + udelay(1000); + } + if (!time) + return -1; + + /* Port based VLANs configuration */ + mv88e61xx_port_vlan_config(swconfig); + if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) { /* * Enable RGMII delay on Tx and Rx for CPU port * Ref: sec 9.5 of chip datasheet-02 */ - WR_PHY(name, MV88E61XX_PRT_OFST + 5, - MV88E61XX_RGMII_TIMECTRL_REG, 0x18); - WR_PHY(name, MV88E61XX_PRT_OFST + 4, - MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + /*Force port link down */ + WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10); + /* configure port RGMII delay */ + WR_SWITCH_PORT_REG(name, 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7); + RD_SWITCH_PORT_REG(name, 5, + MV88E61XX_RGMII_TIMECTRL_REG, ®); + WR_SWITCH_PORT_REG(name, 5, + MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18); + WR_SWITCH_PORT_REG(name, 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + /* Force port to RGMII FDX 1000Base then up */ + WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e); + WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e); } for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { - if (!((1 << prt) & swconfig->cpuport)) { - if (mv88361xx_led_init(swconfig, prt)) + /* configure port's PHY */ + if (!((1 << prt) & swconfig->cpuport)) { + /* port 4 has phy 6, not 4 */ + int phy = (prt == 4) ? 6 : prt; + if (mv88361xx_powerup(swconfig, phy)) return -1; - if (mv88361xx_reverse_mdipn(swconfig, prt)) + if (mv88361xx_reverse_mdipn(swconfig, phy)) return -1; - if (mv88361xx_powerup(swconfig, prt)) + if (mv88361xx_led_init(swconfig, phy)) return -1; } + /* set port VID to port+1 except for cpu port */ + if (!((1 << prt) & swconfig->cpuport)) { + RD_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_VID_REG, ®); + WR_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_VID_REG, + (reg & ~1023) | (prt+1)); + } + /*Program port state */ - RD_PHY(name, MV88E61XX_PRT_OFST + prt, - MV88E61XX_PRT_CTRL_REG, ®); - WR_PHY(name, MV88E61XX_PRT_OFST + prt, - MV88E61XX_PRT_CTRL_REG, - reg | (swconfig->portstate & 0x03)); + RD_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_CTRL_REG, ®); + WR_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_CTRL_REG, + reg | (swconfig->portstate & 0x03)); + } printf("%s Initialized on %s\n", idstr, name); return 0; } + +#ifdef CONFIG_MV88E61XX_CMD +static int +do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *name, *endp; + int write = 0; + enum { dev, prt, phy } target = dev; + u32 addrlo, addrhi, addr; + u32 reglo, reghi, reg; + u16 data, rdata; + + if (argc < 7) + return -1; + + name = argv[1]; + + if (strcmp(argv[2], "phy") == 0) + target = phy; + else if (strcmp(argv[2], "port") == 0) + target = prt; + else if (strcmp(argv[2], "dev") != 0) + return 1; + + addrlo = simple_strtoul(argv[3], &endp, 16); + + if (!*endp) { + addrhi = addrlo; + } else { + while (*endp < '0' || *endp > '9') + endp++; + addrhi = simple_strtoul(endp, NULL, 16); + } + + reglo = simple_strtoul(argv[5], &endp, 16); + if (!*endp) { + reghi = reglo; + } else { + while (*endp < '0' || *endp > '9') + endp++; + reghi = simple_strtoul(endp, NULL, 16); + } + + if (strcmp(argv[6], "write") == 0) + write = 1; + else if (strcmp(argv[6], "read") != 0) + return 1; + + data = simple_strtoul(argv[7], NULL, 16); + + for (addr = addrlo; addr <= addrhi; addr++) { + for (reg = reglo; reg <= reghi; reg++) { + if (write) { + if (target == phy) + mv88e61xx_switch_miiphy_write( + name, addr, reg, data); + else if (target == prt) + wr_switch_reg(name, + addr+MV88E61XX_PRT_OFST, + reg, data); + else + wr_switch_reg(name, addr, reg, data); + } else { + if (target == phy) + mv88e61xx_switch_miiphy_read( + name, addr, reg, &rdata); + else if (target == prt) + rd_switch_reg(name, + addr+MV88E61XX_PRT_OFST, + reg, &rdata); + else + rd_switch_reg(name, addr, reg, &rdata); + printf("%s %s %s %02x %s %02x %s %04x\n", + argv[0], argv[1], argv[2], addr, + argv[4], reg, argv[6], rdata); + if (write && argc == 7 && rdata != data) + return 1; + } + } + } + return 0; +} + +U_BOOT_CMD(mv88e61xx, 8, 0, do_switch, + "Read or write mv88e61xx switch registers", + "<ethdevice> dev|port|phy <addr> reg <reg> write <data>\n" + "<ethdevice> dev|port|phy <addr> reg <reg> read [<data>]\n" + " - read/write switch device, port or phy at (addr,reg)\n" + " addr=0..0x1C for dev, 0..5 for port or phy.\n" + " reg=0..0x1F.\n" + " data=0..0xFFFF (tested if present against actual read).\n" + " All numeric parameters are assumed to be hex.\n" + " <addr> and <<reg> arguments can be ranges (x..y)" +); +#endif /* CONFIG_MV88E61XX_CMD */ diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h index 57762b686..55ded7e03 100644 --- a/drivers/net/phy/mv88e61xx.h +++ b/drivers/net/phy/mv88e61xx.h @@ -28,35 +28,50 @@ #include <miiphy.h> #define MV88E61XX_CPU_PORT 0x5 -#define MV88E61XX_MAX_PORTS_NUM 0x6 #define MV88E61XX_PHY_TIMEOUT 100000 -#define MV88E61XX_PRT_STS_REG 0x1 +/* port dev-addr (= port + 0x10) */ +#define MV88E61XX_PRT_OFST 0x10 +/* port registers */ +#define MV88E61XX_PCS_CTRL_REG 0x1 #define MV88E61XX_PRT_CTRL_REG 0x4 #define MV88E61XX_PRT_VMAP_REG 0x6 #define MV88E61XX_PRT_VID_REG 0x7 +#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A -#define MV88E61XX_PRT_OFST 0x10 +/* global registers dev-addr */ +#define MV88E61XX_GLBREG_DEVADR 0x1B +/* global registers */ +#define MV88E61XX_SGSR 0x00 +#define MV88E61XX_SGCR 0x04 + +/* global 2 registers dev-addr */ +#define MV88E61XX_GLB2REG_DEVADR 0x1C +/* global 2 registers */ #define MV88E61XX_PHY_CMD 0x18 #define MV88E61XX_PHY_DATA 0x19 -#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A -#define MV88E61XX_GLB2REG_DEVADR 0x1C +/* global 2 phy commands */ +#define MV88E61XX_PHY_WRITE_CMD 0x9400 +#define MV88E61XX_PHY_READ_CMD 0x9800 #define MV88E61XX_BUSY_OFST 15 #define MV88E61XX_MODE_OFST 12 -#define MV88E61XX_OP_OFST 10 +#define MV88E61XX_OP_OFST 10 #define MV88E61XX_ADDR_OFST 5 #ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE static int mv88e61xx_busychk_multic(char *name, u32 devaddr); -static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data); -static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data); -#define WR_PHY mv88e61xx_wr_phy -#define RD_PHY mv88e61xx_rd_phy +static void mv88e61xx_switch_write(char *name, u32 phy_adr, + u32 reg_ofs, u16 data); +static void mv88e61xx_switch_read(char *name, u32 phy_adr, + u32 reg_ofs, u16 *data); +#define wr_switch_reg mv88e61xx_switch_write +#define rd_switch_reg mv88e61xx_switch_read #else -#define WR_PHY miiphy_write -#define RD_PHY miiphy_read +/* switch appears a s simple PHY and can thus use miiphy */ +#define wr_switch_reg miiphy_write +#define rd_switch_reg miiphy_read #endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ #endif /* _MV88E61XX_H */ diff --git a/drivers/power/twl6035.c b/drivers/power/twl6035.c index 624c09e85..d3de698cd 100644 --- a/drivers/power/twl6035.c +++ b/drivers/power/twl6035.c @@ -50,16 +50,25 @@ void twl6035_init_settings(void) return; } -void twl6035_mmc1_poweron_ldo(void) +int twl6035_mmc1_poweron_ldo(void) { u8 val = 0; /* set LDO9 TWL6035 to 3V */ val = 0x2b; /* (3 -.9)*28 +1 */ - palmas_write_u8(0x48, LDO9_VOLTAGE, val); + + if (palmas_write_u8(0x48, LDO9_VOLTAGE, val)) { + printf("twl6035: could not set LDO9 voltage.\n"); + return 1; + } /* TURN ON LDO9 */ val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE; - palmas_write_u8(0x48, LDO9_CTRL, val); - return; + + if (palmas_write_u8(0x48, LDO9_CTRL, val)) { + printf("twl6035: could not turn on LDO9.\n"); + return 1; + } + + return 0; } diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index bbd91ca24..87a091708 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -36,8 +36,10 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) { +#if (!defined(CONFIG_SYS_NS16550_BROKEN_TEMT)) while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT)) ; +#endif serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index a33334eac..7e38a3fd5 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -143,7 +143,7 @@ struct uart_port { #elif defined(CONFIG_H8S2678) # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) -#elif defined(CONFIG_CPU_SH7757) +#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) # define SCSPTR0 0xfe4b0020 # define SCSPTR1 0xfe4b0020 # define SCSPTR2 0xfe4b0020 diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index c7a51f7f3..ce7d46085 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -92,7 +92,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, as->slave.cs = cs; as->regs = regs; as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS -#if defined(CONFIG_AT91SAM9X5) +#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9M10G45) | ATMEL_SPI_MR_WDRBT #endif | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf); diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index a7cda751b..de81064b9 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -41,7 +41,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, { struct spi_slave *slave; u32 data; - u32 kwspi_mpp_config[] = { 0, 0 }; + static const u32 kwspi_mpp_config[2][2] = { + { MPP0_SPI_SCn, 0 }, /* if cs == 0 */ + { MPP7_SPI_SCn, 0 } /* if cs != 0 */ + }; if (!spi_cs_is_valid(bus, cs)) return NULL; @@ -68,12 +71,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, writel(KWSPI_IRQMASK, &spireg->irq_mask); /* program mpp registers to select SPI_CSn */ - if (cs) { - kwspi_mpp_config[0] = MPP7_SPI_SCn; - } else { - kwspi_mpp_config[0] = MPP0_SPI_SCn; - } - kirkwood_mpp_conf(kwspi_mpp_config, cs_spi_mpp_back); + kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back); return slave; } diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 6791a7e0e..344d5b8a7 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -57,6 +57,20 @@ static void spi_reset(struct omap3_spi_slave *ds) writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &ds->regs->wakeupenable); } +static void omap3_spi_write_chconf(struct omap3_spi_slave *ds, int val) +{ + writel(val, &ds->regs->channel[ds->slave.cs].chconf); + /* Flash post writes to make immediate effect */ + readl(&ds->regs->channel[ds->slave.cs].chconf); +} + +static void omap3_spi_set_enable(struct omap3_spi_slave *ds, int enable) +{ + writel(enable, &ds->regs->channel[ds->slave.cs].chctrl); + /* Flash post writes to make immediate effect */ + readl(&ds->regs->channel[ds->slave.cs].chctrl); +} + void spi_init() { /* do nothing */ @@ -212,7 +226,7 @@ int spi_claim_bus(struct spi_slave *slave) /* Transmit & receive mode */ conf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; - writel(conf, &ds->regs->channel[ds->slave.cs].chconf); + omap3_spi_write_chconf(ds,conf); return 0; } @@ -233,14 +247,13 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp, int timeout = SPI_WAIT_TIMEOUT; int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf); - if (flags & SPI_XFER_BEGIN) - writel(OMAP3_MCSPI_CHCTRL_EN, - &ds->regs->channel[ds->slave.cs].chctrl); + /* Enable the channel */ + omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN); chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY; chconf |= OMAP3_MCSPI_CHCONF_FORCE; - writel(chconf, &ds->regs->channel[ds->slave.cs].chconf); + omap3_spi_write_chconf(ds,chconf); for (i = 0; i < len; i++) { /* wait till TX register is empty (TXS == 1) */ @@ -256,15 +269,17 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp, writel(txp[i], &ds->regs->channel[ds->slave.cs].tx); } + /* wait to finish of transfer */ + while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) & + OMAP3_MCSPI_CHSTAT_EOT)); + + /* Disable the channel otherwise the next immediate RX will get affected */ + omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS); + if (flags & SPI_XFER_END) { - /* wait to finish of transfer */ - while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) & - OMAP3_MCSPI_CHSTAT_EOT)); chconf &= ~OMAP3_MCSPI_CHCONF_FORCE; - writel(chconf, &ds->regs->channel[ds->slave.cs].chconf); - - writel(0, &ds->regs->channel[ds->slave.cs].chctrl); + omap3_spi_write_chconf(ds,chconf); } return 0; } @@ -277,14 +292,13 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp, int timeout = SPI_WAIT_TIMEOUT; int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf); - if (flags & SPI_XFER_BEGIN) - writel(OMAP3_MCSPI_CHCTRL_EN, - &ds->regs->channel[ds->slave.cs].chctrl); + /* Enable the channel */ + omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN); chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY; chconf |= OMAP3_MCSPI_CHCONF_FORCE; - writel(chconf, &ds->regs->channel[ds->slave.cs].chconf); + omap3_spi_write_chconf(ds,chconf); writel(0, &ds->regs->channel[ds->slave.cs].tx); @@ -298,15 +312,18 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp, return -1; } } + + /* Disable the channel to prevent furher receiving */ + if(i == (len - 1)) + omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS); + /* Read the data */ rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx); } if (flags & SPI_XFER_END) { chconf &= ~OMAP3_MCSPI_CHCONF_FORCE; - writel(chconf, &ds->regs->channel[ds->slave.cs].chconf); - - writel(0, &ds->regs->channel[ds->slave.cs].chctrl); + omap3_spi_write_chconf(ds,chconf); } return 0; @@ -323,14 +340,12 @@ int omap3_spi_txrx(struct spi_slave *slave, int i=0; /*Enable SPI channel*/ - if (flags & SPI_XFER_BEGIN) - writel(OMAP3_MCSPI_CHCTRL_EN, - &ds->regs->channel[ds->slave.cs].chctrl); + omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN); /*set TRANSMIT-RECEIVE Mode*/ chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; chconf |= OMAP3_MCSPI_CHCONF_FORCE; - writel(chconf, &ds->regs->channel[ds->slave.cs].chconf); + omap3_spi_write_chconf(ds,chconf); /*Shift in and out 1 byte at time*/ for (i=0; i < len; i++){ @@ -359,13 +374,13 @@ int omap3_spi_txrx(struct spi_slave *slave, /* Read the data */ rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx); } + /* Disable the channel */ + omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS); /*if transfer must be terminated disable the channel*/ if (flags & SPI_XFER_END) { chconf &= ~OMAP3_MCSPI_CHCONF_FORCE; - writel(chconf, &ds->regs->channel[ds->slave.cs].chconf); - - writel(0, &ds->regs->channel[ds->slave.cs].chctrl); + omap3_spi_write_chconf(ds,chconf); } return 0; @@ -389,17 +404,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf); if (flags & SPI_XFER_BEGIN) { - writel(OMAP3_MCSPI_CHCTRL_EN, - &ds->regs->channel[ds->slave.cs].chctrl); + omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN); chconf |= OMAP3_MCSPI_CHCONF_FORCE; - writel(chconf, - &ds->regs->channel[ds->slave.cs].chconf); + omap3_spi_write_chconf(ds,chconf); } if (flags & SPI_XFER_END) { chconf &= ~OMAP3_MCSPI_CHCONF_FORCE; - writel(chconf, - &ds->regs->channel[ds->slave.cs].chconf); - writel(0, &ds->regs->channel[ds->slave.cs].chctrl); + omap3_spi_write_chconf(ds,chconf); + omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS); } ret = 0; } else { diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h index bffa43cb6..5e00208c5 100644 --- a/drivers/spi/omap3_spi.h +++ b/drivers/spi/omap3_spi.h @@ -99,6 +99,7 @@ struct mcspi { #define OMAP3_MCSPI_CHSTAT_EOT (1 << 2) #define OMAP3_MCSPI_CHCTRL_EN (1 << 0) +#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0) #define OMAP3_MCSPI_WAKEUPENABLE_WKEN (1 << 0) diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index 7d87050df..a5a4c1fe6 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -69,6 +69,7 @@ static struct usb_device_descriptor device_desc = { static struct usb_string g_dnl_string_defs[] = { { 0, manufacturer, }, { 1, product, }, + { } /* end of list */ }; static struct usb_gadget_strings g_dnl_string_tab = { @@ -83,7 +84,12 @@ static struct usb_gadget_strings *g_dnl_composite_strings[] = { static int g_dnl_unbind(struct usb_composite_dev *cdev) { - debug("%s\n", __func__); + struct usb_gadget *gadget = cdev->gadget; + + debug("%s: calling usb_gadget_disconnect for " + "controller '%s'\n", shortname, gadget->name); + usb_gadget_disconnect(gadget); + return 0; } @@ -153,6 +159,10 @@ static int g_dnl_bind(struct usb_composite_dev *cdev) device_desc.bcdDevice = __constant_cpu_to_le16(0x9999); } + debug("%s: calling usb_gadget_connect for " + "controller '%s'\n", shortname, gadget->name); + usb_gadget_connect(gadget); + return 0; error: diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c index dd741439a..9ce98f076 100644 --- a/drivers/usb/gadget/pxa25x_udc.c +++ b/drivers/usb/gadget/pxa25x_udc.c @@ -40,7 +40,6 @@ #include <asm/io.h> #include <asm/arch/pxa.h> -#include <usbdescriptors.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> #include <usb/lin_gadget_compat.h> diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 9532dd9ef..efd711d48 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -41,7 +41,8 @@ int usb_cpu_init(void) writel(get_pllb_init(), &pmc->pllbr); while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) ; -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ + defined(CONFIG_AT91SAM9X5) /* Enable UPLL */ writel(readl(&pmc->uckr) | AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); @@ -81,7 +82,8 @@ int usb_cpu_stop(void) writel(0, &pmc->pllbr); while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) ; -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ + defined(CONFIG_AT91SAM9X5) /* Disable UPLL */ writel(readl(&pmc->uckr) & (~AT91_PMC_UPLLEN), &pmc->uckr); while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) diff --git a/include/common.h b/include/common.h index d0bf1e8ab..4ad17eafb 100644 --- a/include/common.h +++ b/include/common.h @@ -300,7 +300,7 @@ int abortboot(int bootdelay); extern char console_buffer[]; /* arch/$(ARCH)/lib/board.c */ -void board_init_f (ulong) __attribute__ ((noreturn)); +void board_init_f(ulong); void board_init_r (gd_t *, ulong) __attribute__ ((noreturn)); int checkboard (void); int checkflash (void); @@ -311,6 +311,15 @@ int mac_read_from_eeprom(void); extern u8 _binary_dt_dtb_start[]; /* embedded device tree blob */ int set_cpu_clk_info(void); +/** + * Show the DRAM size in a board-specific way + * + * This is used by boards to display DRAM information in their own way. + * + * @param size Size of DRAM (which should be displayed along with other info) + */ +void board_show_dram(ulong size); + /* common/flash.c */ void flash_perror (int); diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index e82f6421c..2a82e19c7 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -56,6 +56,7 @@ #define CONFIG_CMD_LICENSE /* console license display */ #define CONFIG_CMD_LOADB /* loadb */ #define CONFIG_CMD_LOADS /* loads */ +#define CONFIG_CMD_MEMINFO /* meminfo */ #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ #define CONFIG_CMD_MFSL /* FSL support for Microblaze */ #define CONFIG_CMD_MII /* MII support */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ab9549b93..72459d859 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -240,6 +240,38 @@ #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_NAND_AM33XX_BCH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 + +#define CONFIG_SYS_NAND_ECCSTEPS 4 +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM * 64 bytes before this address should be set aside for u-boot.img's @@ -299,6 +331,24 @@ #define CONFIG_NET_MULTI #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC +#define CONFIG_NAND +/* NAND support */ +#ifdef CONFIG_NAND +#define CONFIG_CMD_NAND +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ + /* to access nand at */ + /* CS0 */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND + devices */ +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#endif + #endif /* ! __CONFIG_AM335X_EVM_H */ diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 131758279..6fac5ac4e 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -90,6 +90,14 @@ #define CONFIG_CMD_NAND #define CONFIG_CMD_SF #define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +/* + * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0) + * NB: in this case, USB 1.1 devices won't be recognized. + */ + /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 @@ -142,9 +150,12 @@ /* MMC */ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC -#define CONFIG_CMD_FAT #define CONFIG_GENERIC_MMC #define CONFIG_GENERIC_ATMEL_MCI +#endif + +/* FAT */ +#ifdef CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION #endif @@ -154,6 +165,22 @@ #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_MACB_SEARCH_PHY +/* USB */ +#ifdef CONFIG_CMD_USB +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 +#else +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#endif +#define CONFIG_USB_ATMEL +#define CONFIG_USB_STORAGE +#endif + #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE @@ -178,6 +205,16 @@ #define CONFIG_BOOTCOMMAND "sf probe 0; " \ "sf read 0x22000000 0x100000 0x300000; " \ "bootm 0x22000000" +#elif defined(CONFIG_SYS_USE_DATAFLASH) +/* bootstrap + u-boot + env + linux in data flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x4200 +#define CONFIG_ENV_SIZE 0x4200 +#define CONFIG_ENV_SECT_SIZE 0x210 +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x22000000 0x84000 0x294000; " \ + "bootm 0x22000000" #else /* CONFIG_SYS_USE_MMC */ /* bootstrap + u-boot + env + linux in mmc */ #define CONFIG_ENV_IS_IN_MMC diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 568ae8e09..7d072153e 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -114,9 +114,15 @@ #define CONFIG_DOS_PARTITION /* USB */ -#define CONFIG_MUSB_UDC #define CONFIG_USB_OMAP3 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_MUSB_UDC #define CONFIG_TWL4030_USB +#define CONFIG_CMD_USB /* USB device configuration */ #define CONFIG_USB_DEVICE @@ -188,6 +194,7 @@ /* Environment information */ #define CONFIG_BOOTDELAY 10 +#define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ @@ -282,7 +289,6 @@ */ #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ /*----------------------------------------------------------------------- * FLASH and environment organization diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index adeace0cf..d8aabd4cc 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -159,6 +159,7 @@ #define CONFIG_CMD_GPIO #define CONFIG_CMD_IMI #undef CONFIG_CMD_IMLS +#define CONFIG_CMD_IO #define CONFIG_CMD_IRQ #define CONFIG_CMD_ITEST #define CONFIG_CMD_LOADB diff --git a/include/configs/dig297.h b/include/configs/dig297.h index dda758269..721b91c4d 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -263,7 +263,6 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /*----------------------------------------------------------------------- diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 5a0d321f7..459f56878 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -168,14 +168,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 -/* If M5282 port is fully implemented the monitor base will be behind - * the vector table. */ -#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) -#else -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ -#endif - #define CONFIG_SYS_MONITOR_LEN 0x20000 #define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 diff --git a/include/configs/h2200.h b/include/configs/h2200.h index ef14dd38c..516a26e9f 100644 --- a/include/configs/h2200.h +++ b/include/configs/h2200.h @@ -154,4 +154,29 @@ #define CONFIG_BOOTARGS "root=/dev/ram0 ro console=ttyS0,115200n8" +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_USB_DEV_PULLUP_GPIO 33 +/* USB VBUS GPIO 3 */ + +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING + +#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTCOMMAND \ + "setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \ + "if bootp ; then setenv downloaded 1 ; fi ; done ; " \ + "source :script ; " \ + "bootm ; " + +#define CONFIG_USB_GADGET_PXA2XX +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_SUBSET + +#define CONFIG_USBNET_DEV_ADDR "de:ad:be:ef:00:01" +#define CONFIG_USBNET_HOST_ADDR "de:ad:be:ef:00:02" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + #endif /* __CONFIG_H */ diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index be7937d70..f8131b1ba 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -67,6 +67,9 @@ #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +/* define to avoid U-Boot to hang while waiting for TEMT */ +#define CONFIG_SYS_NS16550_BROKEN_TEMT + /* select serial console configuration */ #define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 @@ -236,7 +239,6 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* @@ -313,6 +315,7 @@ #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_I2C_SUPPORT diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 05480d48a..f64748e34 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -253,9 +253,6 @@ "load=tftpboot ${load_addr_r} ${u-boot}\0" \ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "stderr=serial\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ "" #endif /* CONFIG_KM_DEF_ENV */ diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 8097f28cc..59f151a37 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -146,7 +146,7 @@ "config_nc_dhcp=setenv autoload_old ${autoload}; " \ "setenv autoload no " \ "&& bootp " \ - "&& setenv ncip ${serverip} " \ + "&& setenv ncip " \ "&& setenv autoload ${autoload_old}; " \ "setenv autoload_old\0" \ "standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \ diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 3f37e8430..688717158 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -178,6 +178,8 @@ "512k(environment)," \ "512k(redundant-environment)," \ "4m(kernel)," \ + "128k(fdt)," \ + "8m(ramdisk)," \ "-(filesystem)" #else #define CONFIG_ENV_IS_NOWHERE diff --git a/include/configs/mcx.h b/include/configs/mcx.h index e304c9941..185faa7ef 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -322,7 +322,6 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 7086d1d0e..405a842f7 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -92,7 +92,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 * 4) /* 4MiB for malloc() */ /* * Other required minimal configurations diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 88b2bd6ed..0db92a780 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -95,6 +95,7 @@ #include <config_cmd_default.h> +#define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index fa0db3824..cb3d93890 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -34,10 +34,6 @@ #define CONFIG_SYS_TEXT_BASE 0x97800000 #include <asm/arch/imx-regs.h> -/* - * Disabled for now due to build problems under Debian and a significant - * increase in the final file size: 144260 vs. 109536 Bytes. - */ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index e30502b4e..996396b99 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -39,6 +39,7 @@ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_GPIO #define CONFIG_REVISION_TAG @@ -112,7 +113,7 @@ #define CONFIG_ETHPRIME "FEC0" -#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ #define CONFIG_SYS_TEXT_BASE 0x77800000 #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -120,11 +121,8 @@ "uimage=uImage\0" \ "mmcdev=0\0" \ "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ + "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \ + "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot} " \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h index 0f226f790..bd2fb108f 100644 --- a/include/configs/mx6qsabre_common.h +++ b/include/configs/mx6qsabre_common.h @@ -41,7 +41,6 @@ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_MMC #define CONFIG_CMD_MMC @@ -78,7 +77,7 @@ #define CONFIG_BOOTDELAY 1 -#define CONFIG_LOADADDR 0x10800000 +#define CONFIG_LOADADDR 0x12000000 #define CONFIG_SYS_TEXT_BASE 0x17800000 #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -166,7 +165,6 @@ #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 #endif #define CONFIG_OF_LIBFDT diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 760f3ce0c..f1ff20169 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -20,4 +20,9 @@ #include "mx6qsabre_common.h" +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + #endif /* __MX6QSABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 4ce4d4c08..0f6bbb4be 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -148,7 +148,7 @@ #define CONFIG_PREBOOT "" -#define CONFIG_LOADADDR 0x10800000 +#define CONFIG_LOADADDR 0x12000000 #define CONFIG_SYS_TEXT_BASE 0x17800000 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/mx6qsabresd.h b/include/configs/mx6qsabresd.h index 771d1297f..a1d92850c 100644 --- a/include/configs/mx6qsabresd.h +++ b/include/configs/mx6qsabresd.h @@ -25,4 +25,10 @@ #include "mx6qsabre_common.h" +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 2 /* eMMC/uSDHC4 */ +#define CONFIG_SYS_MMC_ENV_PART 1 /* Boot partition 1 */ +#endif + #endif /* __MX6QSABRESD_CONFIG_H */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 12d65f2c4..d0daa455e 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -285,7 +285,7 @@ "else run userbutton_nonxm; fi;\0" \ "userbutton_xm=gpio input 4;\0" \ "userbutton_nonxm=gpio input 7;\0" -/* "run userbutton" will return 1 (false) if is pressed and 0 (false) if not */ +/* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run userbutton; then " \ diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 67af31465..09a0b2f71 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -251,7 +251,6 @@ */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 #define CONFIG_ENV_IS_NOWHERE 1 diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 8a8a5d1cc..217f306c0 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -221,7 +221,6 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 #define CONFIG_SYS_TEXT_BASE 0x80008000 diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 2a890c9c7..b02ec850b 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -303,7 +303,6 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /*--------------------------------------------------------------------------*/ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index e152055a6..ee4cbd75c 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -252,7 +252,6 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /*----------------------------------------------------------------------- diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index d6814248e..a6b48a80c 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -221,7 +221,6 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /*----------------------------------------------------------------------- diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h new file mode 100644 index 000000000..bf6bd4d8c --- /dev/null +++ b/include/configs/sh7752evb.h @@ -0,0 +1,153 @@ +/* + * Configuation settings for the sh7752evb board + * + * Copyright (C) 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SH7752EVB_H +#define __SH7752EVB_H + +#undef DEBUG +#define CONFIG_SH 1 +#define CONFIG_SH4A 1 +#define CONFIG_SH_32BIT 1 +#define CONFIG_CPU_SH7752 1 +#define CONFIG_SH7752EVB 1 + +#define CONFIG_SYS_TEXT_BASE 0x5ff80000 +#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7752evb/u-boot.lds" + +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_NFS +#define CONFIG_CMD_DFL +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SF +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_MD5SUM +#define CONFIG_MD5 +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* MEMORY */ +#define SH7752EVB_SDRAM_BASE (0x40000000) +#define SH7752EVB_SDRAM_SIZE (512 * 1024 * 1024) + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE 512 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE 1 +#define CONFIG_CONS_SCIF2 1 +#undef CONFIG_SYS_CONSOLE_INFO_QUIET +#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +#define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + 480 * 1024 * 1024) +#undef CONFIG_SYS_ALT_MEMTEST +#undef CONFIG_SYS_MEMTEST_SCRATCH +#undef CONFIG_SYS_LOADS_BAUD_CHANGE + +#define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE) +#define CONFIG_SYS_SDRAM_SIZE (SH7752EVB_SDRAM_SIZE) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ + 128 * 1024 * 1024) + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + +/* FLASH */ +#define CONFIG_SYS_NO_FLASH + +/* Ether */ +#define CONFIG_SH_ETHER 1 +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 18 +#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 +#define CONFIG_SH_ETHER_USE_GETHER 1 +#define CONFIG_PHYLIB +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII +#define CONFIG_PHY_VITESSE + +#define SH7752EVB_ETHERNET_MAC_BASE_SPI 0x00090000 +#define SH7752EVB_SPI_SECTOR_SIZE (64 * 1024) +#define SH7752EVB_ETHERNET_MAC_BASE SH7752EVB_ETHERNET_MAC_BASE_SPI +#define SH7752EVB_ETHERNET_MAC_SIZE 17 +#define SH7752EVB_ETHERNET_NUM_CH 2 +#define CONFIG_BOARD_LATE_INIT + +/* SPI */ +#define CONFIG_SH_SPI 1 +#define CONFIG_SH_SPI_BASE 0xfe002000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO 1 +#define CONFIG_SPI_FLASH_MACRONIX 1 + +/* MMCIF */ +#define CONFIG_MMC 1 +#define CONFIG_GENERIC_MMC 1 +#define CONFIG_SH_MMCIF 1 +#define CONFIG_SH_MMCIF_ADDR 0xffcb0000 +#define CONFIG_SH_MMCIF_CLK 48000000 + +/* ENV setting */ +#define CONFIG_ENV_IS_EMBEDDED +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_ADDR (0x00080000) +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netboot=bootp; bootm\0" + +/* Board Clock */ +#define CONFIG_SYS_CLK_FREQ 48000000 +#define CONFIG_SYS_TMU_CLK_DIV 4 +#define CONFIG_SYS_HZ 1000 +#endif /* __SH7752EVB_H */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 42077bd6f..5633d2a42 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -65,7 +65,7 @@ #define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) #define CONFIG_SPL_RAM_DEVICE -#define CONFIG_SPL_STACK (&__stack_start) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index ee73c277b..9f1fb9fee 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -189,7 +189,6 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* @@ -358,7 +357,6 @@ * I2C EEPROM */ #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) - /* * The I2C EEPROM on the TAM3517 contains * mac address and production data @@ -384,24 +382,29 @@ struct tam3517_module_info { unsigned char _rev[100]; }; -#define TAM3517_READ_MAC_FROM_EEPROM \ -do { \ - struct tam3517_module_info info;\ - char buf[80], ethname[20]; \ - int i; \ +#define TAM3517_READ_EEPROM(info, ret) \ +do { \ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \ if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ - (void *)&info, sizeof(info))) \ - break; \ + (void *)info, sizeof(*info))) \ + ret = 1; \ + else \ + ret = 0; \ +} while (0) + +#define TAM3517_READ_MAC_FROM_EEPROM(info) \ +do { \ + char buf[80], ethname[20]; \ + int i; \ memset(buf, 0, sizeof(buf)); \ - for (i = 0 ; i < ARRAY_SIZE(info.eth_addr); i++) { \ + for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ - info.eth_addr[i][5], \ - info.eth_addr[i][4], \ - info.eth_addr[i][3], \ - info.eth_addr[i][2], \ - info.eth_addr[i][1], \ - info.eth_addr[i][0]); \ + (info)->eth_addr[i][5], \ + (info)->eth_addr[i][4], \ + (info)->eth_addr[i][3], \ + (info)->eth_addr[i][2], \ + (info)->eth_addr[i][1], \ + (info)->eth_addr[i][0]); \ \ if (i) \ sprintf(ethname, "eth%daddr", i); \ @@ -411,6 +414,30 @@ do { \ setenv(ethname, buf); \ } \ } while (0) + +/* The following macros are taken from Technexion's documentation */ +#define TAM3517_sequence_number(info) \ + ((info)->sequence_number % 0x1000000000000LL) +#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) +#define TAM3517_year(info) ((info)->sequence_number >> 56) +#define TAM3517_revision_fixed(info) ((info)->revision % 0x100) +#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) +#define TAM3517_revision_tn(info) ((info)->revision >> 16) + +#define TAM3517_PRINT_SOM_INFO(info) \ +do { \ + printf("Vendor:%s\n", (info)->customer); \ + printf("SOM: %s\n", (info)->product); \ + printf("SeqNr: %02llu%02llu%012llu\n", \ + TAM3517_year(info), \ + TAM3517_week_of_year(info), \ + TAM3517_sequence_number(info)); \ + printf("Rev: TN%u %u.%u\n", \ + TAM3517_revision_tn(info), \ + TAM3517_revision_major(info), \ + TAM3517_revision_fixed(info)); \ +} while (0) + #endif #endif /* __TAM3517_H */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index be0d2ec3c..bcb0350b8 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -247,7 +247,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* NAND and environment organization */ diff --git a/include/configs/wireless_space.h b/include/configs/wireless_space.h new file mode 100644 index 000000000..eb2049289 --- /dev/null +++ b/include/configs/wireless_space.h @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2011 Albert ARIBAUD <albert.u.boot@aribaud.net> + * + * Based on the netspace_v2 code which is + * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CONFIG_WIRELESS_SPACE_H +#define _CONFIG_WIRELESS_SPACE_H + +/* + * Machine number definition + */ +#define MACH_TYPE_WIRELESS_SPACE 2500 /* is missing in mach-types.h */ +#define CONFIG_MACH_TYPE MACH_TYPE_WIRELESS_SPACE +#define CONFIG_IDENT_STRING " Wireless Space" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SoC Family Name */ +/* SoC name */ +#define CONFIG_KW88F6281 +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */ +#include <config_cmd_default.h> +#define CONFIG_CMD_ENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_NAND +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_USB + +/* + * Core clock definition + */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +/* + * SDRAM configuration + */ +#define CONFIG_NR_DRAM_BANKS 1 + +/* + * Different SDRAM configuration and size for some of the boards derived + * from the Network Space v2 + */ + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_RBTREE +#undef CONFIG_SYS_IDE_MAXBUS +#undef CONFIG_SYS_IDE_MAXDEVICE +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "ws> " + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable only egiga0... */ +#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */ +#define CONFIG_PHY_BASE_ADR 0xa /* ... through a 'fake' PHY */ +#define CONFIG_MII +#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_NETCONSOLE +#define CONFIG_MV88E61XX_SWITCH +#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE +#define CONFIG_MV88E61XX_CMD +#define CONFIG_CMD_TFTPPUT +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif /* CONFIG_MVSATA_IDE */ + +/* + * Enable GPI0 support + */ +#define CONFIG_KIRKWOOD_GPIO + +/* + * Enable I2C support + */ +#ifdef CONFIG_CMD_I2C +/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ +#endif /* CONFIG_CMD_I2C */ + +/* + * Partition support + */ +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION + +/* + * File systems support + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER + +/* + * Console configuration + */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + +/* + * Environment variables configurations + */ + +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */ +#define CONFIG_ENV_SIZE 0x20000 /* 128KB */ +#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ + +/* + * Board-specific command to make using buttons etc easier + */ + +#define CONFIG_WIRELESS_SPACE_CMD + +/* + * Default environment variables + */ +#define CONFIG_PREBOOT + +#define CONFIG_BOOTARGS "console=ttyS0,115200" + +#define CONFIG_BOOTCOMMAND \ + "if run usbload || run diskload; then bootm; fi" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "bootfile=uImage\0" \ + "loadaddr=0x800000\0" \ + "autoload=no\0" \ + "netconsole=" \ + "set stdin $stdin,nc; " \ + "set stdout $stdout,nc; " \ + "set stderr $stderr,nc;\0" \ + "diskload=ide reset && " \ + "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ + "usbload=usb start && " \ + "fatload usb 0:1 $loadaddr /boot/$bootfile\0" \ + "preboot=" \ + "dhcp && run netconsole\0" + +#endif /* _CONFIG_WIRELESS_SPACE_H */ diff --git a/include/env_callback.h b/include/env_callback.h index 47fdc6fa9..c583120c1 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -68,8 +68,16 @@ void env_callback_init(ENTRY *var_entry); * when associated through the ".callbacks" environment variable, the callback * will be executed any time the variable is inserted, overwritten, or deleted. */ +#ifdef CONFIG_SPL_BUILD +#define U_BOOT_ENV_CALLBACK(name, callback) \ + static inline void _u_boot_env_noop_##name(void) \ + { \ + (void)callback; \ + } +#else #define U_BOOT_ENV_CALLBACK(name, callback) \ ll_entry_declare(struct env_clbk_tbl, name, env_clbk, env_clbk) = \ {#name, callback} +#endif #endif /* __ENV_CALLBACK_H__ */ diff --git a/include/flash.h b/include/flash.h index 7db599e78..c7acc977e 100644 --- a/include/flash.h +++ b/include/flash.h @@ -44,6 +44,7 @@ typedef struct { ulong buffer_write_tout; /* maximum buffer write timeout */ ushort vendor; /* the primary vendor id */ ushort cmd_reset; /* vendor specific reset command */ + uchar cmd_erase_sector; /* vendor specific erase sect. command */ ushort interface; /* used for x8/x16 adjustments */ ushort legacy_unlock; /* support Intel legacy (un)locking */ ushort manufacturer_id; /* manufacturer id */ diff --git a/include/image.h b/include/image.h index b958b18a4..f5adc5035 100644 --- a/include/image.h +++ b/include/image.h @@ -179,6 +179,9 @@ #define IH_MAGIC 0x27051956 /* Image Magic Number */ #define IH_NMLEN 32 /* Image Name Length */ +/* Reused from common.h */ +#define ROUND(a, b) (((a) + (b) - 1) & ~((b) - 1)) + /* * Legacy format image header, * all data in network byte order (aka natural aka bigendian). diff --git a/include/netdev.h b/include/netdev.h index b8d303d08..7f158d433 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -163,10 +163,9 @@ static inline int pci_eth_init(bd_t *bis) * the stuct and enums here are used to specify switch configuration params */ #if defined(CONFIG_MV88E61XX_SWITCH) -enum mv88e61xx_cfg_vlan { - MV88E61XX_VLANCFG_DEFAULT, - MV88E61XX_VLANCFG_ROUTER -}; + +/* constants for any 88E61xx switch */ +#define MV88E61XX_MAX_PORTS_NUM 6 enum mv88e61xx_cfg_mdip { MV88E61XX_MDIP_NOCHANGE, @@ -192,7 +191,7 @@ enum mv88e61xx_cfg_prtstt { struct mv88e61xx_config { char *name; - enum mv88e61xx_cfg_vlan vlancfg; + u8 vlancfg[MV88E61XX_MAX_PORTS_NUM]; enum mv88e61xx_cfg_rgmiid rgmii_delay; enum mv88e61xx_cfg_prtstt portstate; enum mv88e61xx_cfg_ledinit led_init; @@ -201,6 +200,18 @@ struct mv88e61xx_config { u8 cpuport; }; +/* + * Common mappings for Internal VLANs + * These mappings consider that all ports are useable; the driver + * will mask inexistent/unused ports. + */ + +/* Switch mode : routes any port to any port */ +#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F } + +/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */ +#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F } + int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); #endif /* CONFIG_MV88E61XX_SWITCH */ diff --git a/include/twl4030.h b/include/twl4030.h index 0c17f5929..5aa184183 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -580,6 +580,50 @@ #define TWL4030_USB_PHY_CLK_CTRL 0xFE #define TWL4030_USB_PHY_CLK_CTRL_STS 0xFF +/* GPIO */ +#define TWL4030_GPIO_GPIODATAIN1 0x00 +#define TWL4030_GPIO_GPIODATAIN2 0x01 +#define TWL4030_GPIO_GPIODATAIN3 0x02 +#define TWL4030_GPIO_GPIODATADIR1 0x03 +#define TWL4030_GPIO_GPIODATADIR2 0x04 +#define TWL4030_GPIO_GPIODATADIR3 0x05 +#define TWL4030_GPIO_GPIODATAOUT1 0x06 +#define TWL4030_GPIO_GPIODATAOUT2 0x07 +#define TWL4030_GPIO_GPIODATAOUT3 0x08 +#define TWL4030_GPIO_CLEARGPIODATAOUT1 0x09 +#define TWL4030_GPIO_CLEARGPIODATAOUT2 0x0A +#define TWL4030_GPIO_CLEARGPIODATAOUT3 0x0B +#define TWL4030_GPIO_SETGPIODATAOUT1 0x0C +#define TWL4030_GPIO_SETGPIODATAOUT2 0x0D +#define TWL4030_GPIO_SETGPIODATAOUT3 0x0E +#define TWL4030_GPIO_GPIO_DEBEN1 0x0F +#define TWL4030_GPIO_GPIO_DEBEN2 0x10 +#define TWL4030_GPIO_GPIO_DEBEN3 0x11 +#define TWL4030_GPIO_GPIO_CTRL 0x12 +#define TWL4030_GPIO_GPIOPUPDCTR1 0x13 +#define TWL4030_GPIO_GPIOPUPDCTR2 0x14 +#define TWL4030_GPIO_GPIOPUPDCTR3 0x15 +#define TWL4030_GPIO_GPIOPUPDCTR4 0x16 +#define TWL4030_GPIO_GPIOPUPDCTR5 0x17 +#define TWL4030_GPIO_GPIO_ISR1A 0x19 +#define TWL4030_GPIO_GPIO_ISR2A 0x1A +#define TWL4030_GPIO_GPIO_ISR3A 0x1B +#define TWL4030_GPIO_GPIO_IMR1A 0x1C +#define TWL4030_GPIO_GPIO_IMR2A 0x1D +#define TWL4030_GPIO_GPIO_IMR3A 0x1E +#define TWL4030_GPIO_GPIO_ISR1B 0x1F +#define TWL4030_GPIO_GPIO_ISR2B 0x20 +#define TWL4030_GPIO_GPIO_ISR3B 0x21 +#define TWL4030_GPIO_GPIO_IMR1B 0x22 +#define TWL4030_GPIO_GPIO_IMR2B 0x23 +#define TWL4030_GPIO_GPIO_IMR3B 0x24 +#define TWL4030_GPIO_GPIO_EDR1 0x28 +#define TWL4030_GPIO_GPIO_EDR2 0x29 +#define TWL4030_GPIO_GPIO_EDR3 0x2A +#define TWL4030_GPIO_GPIO_EDR4 0x2B +#define TWL4030_GPIO_GPIO_EDR5 0x2C +#define TWL4030_GPIO_GPIO_SIH_CTRL 0x2D + /* * Convience functions to read and write from TWL4030 * diff --git a/include/twl6035.h b/include/twl6035.h index e21ddbaf2..ce74348d4 100644 --- a/include/twl6035.h +++ b/include/twl6035.h @@ -39,4 +39,4 @@ int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg); int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg); void twl6035_init_settings(void); -void twl6035_mmc1_poweron_ldo(void); +int twl6035_mmc1_poweron_ldo(void); diff --git a/include/usb.h b/include/usb.h index 8d8a2c9b9..d79c86588 100644 --- a/include/usb.h +++ b/include/usb.h @@ -392,5 +392,6 @@ int hub_port_reset(struct usb_device *dev, int port, struct usb_device *usb_alloc_new_device(void *controller); int usb_new_device(struct usb_device *dev); +void usb_free_device(void); #endif /*_USB_H_ */ diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c index c88f5d445..8546a52f4 100644 --- a/lib/asm-offsets.c +++ b/lib/asm-offsets.c @@ -28,5 +28,19 @@ int main(void) DEFINE(GENERATED_BD_INFO_SIZE, (sizeof(struct bd_info) + 15) & ~15); + DEFINE(GD_SIZE, sizeof(struct global_data)); + + DEFINE(GD_BD, offsetof(struct global_data, bd)); + +#if defined(CONFIG_ARM) + + DEFINE(GD_RELOCADDR, offsetof(struct global_data, relocaddr)); + + DEFINE(GD_RELOC_OFF, offsetof(struct global_data, reloc_off)); + + DEFINE(GD_START_ADDR_SP, offsetof(struct global_data, start_addr_sp)); + +#endif + return 0; } diff --git a/nand_spl/board/freescale/mx31pdk/Makefile b/nand_spl/board/freescale/mx31pdk/Makefile index f67ed09d0..fd0dfc19d 100644 --- a/nand_spl/board/freescale/mx31pdk/Makefile +++ b/nand_spl/board/freescale/mx31pdk/Makefile @@ -12,11 +12,12 @@ LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL -SOBJS = start.o lowlevel_init.o +SOBJS = start.o crt0.o lowlevel_init.o COBJS = nand_boot_fsl_nfc.o SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c SRCS += $(SRCTREE)/arch/arm/cpu/arm1136/start.S +SRCS += $(SRCTREE)/arch/arm/lib/crt0.S SRCS += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) @@ -50,6 +51,9 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT) $(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm1136/%.S $(CC) $(AFLAGS) -c -o $@ $< +$(obj)%.o: $(SRCTREE)/arch/arm/lib/%.S + $(CC) $(AFLAGS) -c -o $@ $< + $(obj)%.o: $(SRCTREE)/board/freescale/mx31pdk/%.S $(CC) $(AFLAGS) -c -o $@ $< diff --git a/nand_spl/board/karo/tx25/Makefile b/nand_spl/board/karo/tx25/Makefile index b27189d9b..82489d240 100644 --- a/nand_spl/board/karo/tx25/Makefile +++ b/nand_spl/board/karo/tx25/Makefile @@ -33,11 +33,12 @@ LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL -SOBJS = start.o lowlevel_init.o +SOBJS = start.o crt0.o lowlevel_init.o COBJS = nand_boot_fsl_nfc.o SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c SRCS += $(SRCTREE)/arch/arm/cpu/arm926ejs/start.S +SRCS += $(SRCTREE)/arch/arm/lib/crt0.S SRCS += $(SRCTREE)/board/karo/tx25/lowlevel_init.S OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) @@ -71,6 +72,9 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT) $(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm926ejs/%.S $(CC) $(AFLAGS) -c -o $@ $< +$(obj)%.o: $(SRCTREE)/arch/arm/lib/%.S + $(CC) $(AFLAGS) -c -o $@ $< + $(obj)%.o: $(SRCTREE)/board/karo/tx25/%.S $(CC) $(AFLAGS) -c -o $@ $< diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 90c7a5d3f..37b60b80a 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -429,7 +429,8 @@ int fw_env_write(char *name, char *value) */ int fw_setenv(int argc, char *argv[]) { - int i, len; + int i; + size_t len; char *name; char *value = NULL; diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c index c855f4c17..40ea3f62a 100644 --- a/tools/env/fw_env_main.c +++ b/tools/env/fw_env_main.c @@ -94,7 +94,7 @@ int main(int argc, char *argv[]) int lockfd = -1; int retval = EXIT_SUCCESS; - lockfd = open(lockname, O_WRONLY | O_CREAT | O_TRUNC); + lockfd = open(lockname, O_WRONLY | O_CREAT | O_TRUNC, 0666); if (-1 == lockfd) { fprintf(stderr, "Error opening lock file %s\n", lockname); return EXIT_FAILURE; diff --git a/tools/imximage.c b/tools/imximage.c index 63f88b6c4..a93d7eb54 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -515,7 +515,14 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, /* Set the imx header */ (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset); - *header_size_ptr = sbuf->st_size + imxhdr->flash_offset; + + /* + * ROM bug alert + * mx53 only loads 512 byte multiples. + * The remaining fraction of a block bytes would + * not be loaded. + */ + *header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 512); } int imximage_check_params(struct mkimage_params *params) |