diff options
| -rw-r--r-- | boards.cfg | 3 | ||||
| -rw-r--r-- | include/configs/t4qds.h | 15 | 
2 files changed, 17 insertions, 1 deletions
| diff --git a/boards.cfg b/boards.cfg index 27815c67a..34fc20f89 100644 --- a/boards.cfg +++ b/boards.cfg @@ -896,6 +896,9 @@ stxssa_4M                    powerpc     mpc85xx     stxssa              stx  T4240QDS                     powerpc     mpc85xx     t4qds               freescale      -           T4240QDS:PPC_T4240  T4240QDS_SDCARD              powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000  T4240QDS_SPIFLASH            powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +T4160QDS                     powerpc     mpc85xx     t4qds               freescale      -           T4240QDS:PPC_T4160 +T4160QDS_SDCARD              powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 +T4160QDS_SPIFLASH            powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000  B4860QDS                     powerpc     mpc85xx     b4860qds            freescale      -           B4860QDS:PPC_B4860  B4860QDS_NAND		     powerpc     mpc85xx     b4860qds            freescale      -           B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000  B4860QDS_SPIFLASH            powerpc     mpc85xx     b4860qds            freescale	-           B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index dbaa7ea9d..a8346f080 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -791,8 +791,21 @@ unsigned long get_board_ddr_clk(void);  #define __USB_PHY_TYPE	utmi +/* + * T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be + * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to + * cacheline interleaving. It can be cacheline, page, bank, superbank. + * See doc/README.fsl-ddr for details. + */ +#ifdef CONFIG_PPC_T4240 +#define CTRL_INTLV_PREFERED 3way_4KB +#else +#define CTRL_INTLV_PREFERED cacheline +#endif +  #define	CONFIG_EXTRA_ENV_SETTINGS				\ -	"hwconfig=fsl_ddr:ctlr_intlv=3way_4KB,"		\ +	"hwconfig=fsl_ddr:"					\ +	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\  	"bank_intlv=auto;"					\  	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\  	"netdev=eth0\0"						\ |