diff options
27 files changed, 118 insertions, 1022 deletions
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 313f9f36a..3ffdac8bd 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -522,67 +522,6 @@ int pci_pre_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ /************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Set up Direct MMIO registers - *--------------------------------------------------------------------------*/ - /*--------------------------------------------------------------------------+ - | PowerPC440 EP PCI Master configuration. - | Map one 1Gig range of PLB/processor addresses to PCI memory space. - | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +--------------------------------------------------------------------------*/ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /*--------------------------------------------------------------------------+ - * Set up Configuration registers - *--------------------------------------------------------------------------*/ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/************************************************************************* * pci_master_init * ************************************************************************/ diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 9a8ca8ece..13a0daced 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -326,43 +326,6 @@ phys_size_t initdram(int board_type) } #endif -/* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /* - * Disable everything - */ - out_le32((void *)PCIL0_PIM0SA, 0); /* disable */ - out_le32((void *)PCIL0_PIM1SA, 0); /* disable */ - out_le32((void *)PCIL0_PIM2SA, 0); /* disable */ - out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */ - - /* - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 - * strapping options to not support sizes such as 128/256 MB. - */ - out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out_le32((void *)PCIL0_PIM0LAH, 0); - out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); - out_le32((void *)PCIL0_BAR0, 0); - - /* - * Program the board's subsystem id/vendor id - */ - out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - - out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - #if defined(CONFIG_PCI) int board_pcie_first(void) { diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index 1524b5333..e4d168f9d 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -195,42 +195,3 @@ int pci_pre_init(struct pci_controller *hose) return 1; } #endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r(PCIL0_PIM0SA, 0); /* disable */ - out32r(PCIL0_PIM1SA, 0); /* disable */ - out32r(PCIL0_PIM2SA, 0); /* disable */ - out32r(PCIL0_EROMBA, 0); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out32r(PCIL0_PIM0LAH, 0); - out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); - - out32r(PCIL0_BAR0, 0); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - - out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index f43e76448..f0b48c0d3 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2008 + * (C) Copyright 2007-2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -291,44 +291,6 @@ int pci_pre_init(struct pci_controller * hose ) } #endif /* defined(CONFIG_PCI) */ -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*-------------------------------------------------------------------+ - * Disable everything - *-------------------------------------------------------------------*/ - out32r( PCIL0_PIM0SA, 0 ); /* disable */ - out32r( PCIL0_PIM1SA, 0 ); /* disable */ - out32r( PCIL0_PIM2SA, 0 ); /* disable */ - out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ - - /*-------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 - * strapping options to not support sizes such as 128/256 MB. - *-------------------------------------------------------------------*/ - out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIL0_PIM0LAH, 0 ); - out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIL0_BAR0, 0 ); - - /*-------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *-------------------------------------------------------------------*/ - out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - - out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - #if defined(CONFIG_PCI) int board_pcie_card_present(int port) { diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 94ba6437f..e0b297e70 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -160,46 +160,6 @@ int pci_pre_init( struct pci_controller *hose ) /************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0SA, 0 ); /* disable */ - out32r( PCIL0_PIM1SA, 0 ); /* disable */ - out32r( PCIL0_PIM2SA, 0 ); /* disable */ - out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIL0_PIM0LAH, 0 ); - out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIL0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - - out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - - -/************************************************************************* * hw_watchdog_reset * * This routine is called to reset (keep alive) the watchdog timer diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 2f64764ee..b38f3cc40 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -307,46 +307,6 @@ int pci_pre_init(struct pci_controller * hose ) } #endif /* defined(CONFIG_PCI) */ -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0SA, 0 ); /* disable */ - out32r( PCIL0_PIM1SA, 0 ); /* disable */ - out32r( PCIL0_PIM2SA, 0 ); /* disable */ - out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIL0_PIM0LAH, 0 ); - out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIL0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - - out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - - void fpga_init(void) { unsigned long group; diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 439382006..b8ef4e763 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -427,71 +427,6 @@ int pci_pre_init(struct pci_controller *hose) } #endif /* defined(CONFIG_PCI) */ -/* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /* - * Set up Direct MMIO registers - */ - /* - * PowerPC440EPX PCI Master configuration. - * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0xA0000000-0xDFFFFFFF - * ==> PCI address 0xA0000000-0xDFFFFFFF - * Use byte reversed out routines to handle endianess. - * Make this region non-prefetchable. - */ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ - /* and enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ - /* and enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /* - * Set up Configuration registers - */ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index 81e8fe14a..574ff1a7b 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -240,45 +240,6 @@ int pci_pre_init(struct pci_controller * hose ) } #endif /* defined(CONFIG_PCI) */ -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0SA, 0 ); /* disable */ - out32r( PCIL0_PIM1SA, 0 ); /* disable */ - out32r( PCIL0_PIM2SA, 0 ); /* disable */ - out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIL0_PIM0LAH, 0 ); - out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIL0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - - out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - #ifdef CONFIG_POST /* * Returns 1 if keys pressed to start the power-on long-running tests diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index e416eeb16..cd14a6a48 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -408,67 +408,6 @@ int pci_pre_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ /************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Set up Direct MMIO registers - *--------------------------------------------------------------------------*/ - /*--------------------------------------------------------------------------+ - | PowerPC440 EP PCI Master configuration. - | Map one 1Gig range of PLB/processor addresses to PCI memory space. - | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +--------------------------------------------------------------------------*/ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /*--------------------------------------------------------------------------+ - * Set up Configuration registers - *--------------------------------------------------------------------------*/ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/************************************************************************* * pci_master_init * ************************************************************************/ diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 7315033dc..0ec26f14d 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -619,44 +619,6 @@ int pci_pre_init(struct pci_controller * hose ) } #endif /* defined(CONFIG_PCI) */ -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*-------------------------------------------------------------------+ - * Disable everything - *-------------------------------------------------------------------*/ - out32r( PCIL0_PIM0SA, 0 ); /* disable */ - out32r( PCIL0_PIM1SA, 0 ); /* disable */ - out32r( PCIL0_PIM2SA, 0 ); /* disable */ - out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ - - /*-------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 - * strapping options to not support sizes such as 128/256 MB. - *-------------------------------------------------------------------*/ - out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIL0_PIM0LAH, 0 ); - out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIL0_BAR0, 0 ); - - /*-------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *-------------------------------------------------------------------*/ - out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - - out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - #if defined(CONFIG_PCI) int board_pcie_card_present(int port) { diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 8f9f9500e..866dcafcf 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -414,73 +414,6 @@ int pci_pre_init(struct pci_controller *hose) } #endif /* defined(CONFIG_PCI) */ -/* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /* - * Set up Direct MMIO registers - */ - /* - * PowerPC440EPX PCI Master configuration. - * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0xA0000000-0xDFFFFFFF - * ==> PCI address 0xA0000000-0xDFFFFFFF - * Use byte reversed out routines to handle endianess. - * Make this region non-prefetchable. - */ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ - /* and enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ - /* and enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /* - * Set up Configuration registers - */ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - PCI_VENDOR_ID_ESDGMBH); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440); - - pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h index a124a7ee9..37697ec85 100644 --- a/board/esd/du440/du440.h +++ b/board/esd/du440/du440.h @@ -38,6 +38,3 @@ #define PWR_RDY 0x10 #define CPLD_IRQ (32+30) - -#define PCI_VENDOR_ID_ESDGMBH 0x12fe -#define PCI_DEVICE_ID_DU440 0x0444 diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c index 92f5d822f..b93a42015 100644 --- a/board/gdsys/gdppc440etx/gdppc440etx.c +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -217,69 +217,6 @@ int pci_pre_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ /* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /* - * Set up Direct MMIO registers - */ - - /* - * PowerPC440 EP PCI Master configuration. - * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0xA0000000-0xDFFFFFFF - * ==> PCI address 0xA0000000-0xDFFFFFFF - * Use byte reversed out routines to handle endianess. - * Make this region non-prefetchable. - */ - out32r(PCIL0_PMM0MA, 0x00000000); /* disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); - out32r(PCIL0_PMM0PCIHA, 0x00000000); - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* disabled b4 setting */ - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); - out32r(PCIL0_PMM1PCIHA, 0x00000000); - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); - out32r(PCIL0_PTM1LA, 0); - out32r(PCIL0_PTM2MS, 0); - out32r(PCIL0_PTM2LA, 0); - - /* - * Set up Configuration registers - */ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/* * pci_master_init * */ diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c index 49d245135..23a10c41f 100644 --- a/board/gdsys/intip/intip.c +++ b/board/gdsys/intip/intip.c @@ -141,43 +141,6 @@ int checkboard(void) return 0; } -/* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /* - * Disable everything - */ - out_le32((void *)PCIL0_PIM0SA, 0); /* disable */ - out_le32((void *)PCIL0_PIM1SA, 0); /* disable */ - out_le32((void *)PCIL0_PIM2SA, 0); /* disable */ - out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */ - - /* - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 - * strapping options to not support sizes such as 128/256 MB. - */ - out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out_le32((void *)PCIL0_PIM0LAH, 0); - out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); - out_le32((void *)PCIL0_BAR0, 0); - - /* - * Program the board's subsystem id/vendor id - */ - out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - - out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - int board_early_init_r(void) { /* diff --git a/board/korat/korat.c b/board/korat/korat.c index b0e6a56a6..02ebfdf37 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -35,6 +35,7 @@ #include <asm/io.h> #include <asm/ppc4xx-uic.h> #include <asm/processor.h> +#include <asm/4xx_pci.h> DECLARE_GLOBAL_DATA_PTR; @@ -668,60 +669,8 @@ int pci_pre_init(struct pci_controller *hose) #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { - /* - * Set up Direct MMIO registers - */ - /* - * PowerPC440EPX PCI Master configuration. - * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0x80000000-0xBFFFFFFF - * ==> PCI address 0x80000000-0xBFFFFFFF - * Use byte reversed out routines to handle endianess. - * Make this region non-prefetchable. - */ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, - CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ - /* and enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIL0_PMM1LA, - CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */ - out32r(PCIL0_PMM1PCILA, - CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ - /* and enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /* - * Set up Configuration registers - */ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + /* First do 440EP(x) common setup */ + __pci_target_init(hose); /* * Set up Configuration registers for on-board NEC uPD720101 USB diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 09ba2b933..77f2d7f68 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -331,67 +331,6 @@ int pci_pre_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ /************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Set up Direct MMIO registers - *--------------------------------------------------------------------------*/ - /*--------------------------------------------------------------------------+ - | PowerPC440EPX PCI Master configuration. - | Map one 1Gig range of PLB/processor addresses to PCI memory space. - | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +--------------------------------------------------------------------------*/ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /*--------------------------------------------------------------------------+ - * Set up Configuration registers - *--------------------------------------------------------------------------*/ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/************************************************************************* * pci_master_init * ************************************************************************/ diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 7ffc26202..144fdd970 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -377,71 +377,6 @@ int pci_pre_init(struct pci_controller *hose) } /* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - */ -void pci_target_init(struct pci_controller *hose) -{ - if (!board_with_pci()) { return; } - /* - * Set up Direct MMIO registers - * - * PowerPC440EPX PCI Master configuration. - * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address - * 0xA0000000-0xDFFFFFFF - * Use byte reversed out routines to handle endianess. - * Make this region non-prefetchable. - */ - /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM0MA, 0x00000000); - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - /* 512M + No prefetching, and enable region */ - out32r(PCIL0_PMM0MA, 0xE0000001); - - /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM1MA, 0x00000000); - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - /* 512M + No prefetching, and enable region */ - out32r(PCIL0_PMM1MA, 0xE0000001); - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /* - * Set up Configuration registers - */ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); -} - -/* * pci_master_init * */ diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 2155711d6..929375987 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -606,67 +606,6 @@ int pci_pre_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ /************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Set up Direct MMIO registers - *--------------------------------------------------------------------------*/ - /*--------------------------------------------------------------------------+ - | PowerPC440 EP PCI Master configuration. - | Map one 1Gig range of PLB/processor addresses to PCI memory space. - | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +--------------------------------------------------------------------------*/ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /*--------------------------------------------------------------------------+ - * Set up Configuration registers - *--------------------------------------------------------------------------*/ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/************************************************************************* * pci_master_init * ************************************************************************/ diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index e9e2bf3e0..c06aadb41 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -179,45 +179,6 @@ int pci_pre_init(struct pci_controller * hose ) #endif /* defined(CONFIG_PCI) */ /************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0SA, 0 ); /* disable */ - out32r( PCIL0_PIM1SA, 0 ); /* disable */ - out32r( PCIL0_PIM2SA, 0 ); /* disable */ - out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIL0_PIM0LAH, 0 ); - out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIL0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - - out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/************************************************************************* * Override weak is_pci_host() * * This routine is called to determine if a pci scan should be diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index e07400794..5761e7084 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -196,45 +196,6 @@ int pci_pre_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ /************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r(PCIL0_PIM0SA, 0); /* disable */ - out32r(PCIL0_PIM1SA, 0); /* disable */ - out32r(PCIL0_PIM2SA, 0); /* disable */ - out32r(PCIL0_EROMBA, 0); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out32r(PCIL0_PIM0LAH, 0); - out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); - - out32r(PCIL0_BAR0, 0); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - - out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/************************************************************************* * Override weak is_pci_host() * * This routine is called to determine if a pci scan should be diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index 574908458..45e904385 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -333,46 +333,6 @@ int pci_pre_init(struct pci_controller * hose ) #endif /* defined(CONFIG_PCI) */ /************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0SA, 0 ); /* disable */ - out32r( PCIL0_PIM1SA, 0 ); /* disable */ - out32r( PCIL0_PIM2SA, 0 ); /* disable */ - out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIL0_PIM0LAH, 0 ); - out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIL0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - - out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - - -/************************************************************************* * board_get_enetaddr * * Get the ethernet MAC address for the management ethernet from the diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c index 0c4cf9463..db37ca051 100644 --- a/board/xes/xpedite1000/xpedite1000.c +++ b/board/xes/xpedite1000/xpedite1000.c @@ -166,38 +166,6 @@ int pci_pre_init(struct pci_controller * hose) } #endif /* defined(CONFIG_PCI) */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -/* - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - */ -void pci_target_init(struct pci_controller * hose) -{ - /* Disable everything */ - out32r(PCIL0_PIM0SA, 0); - out32r(PCIL0_PIM1SA, 0); - out32r(PCIL0_PIM2SA, 0); - out32r(PCIL0_EROMBA, 0); /* disable expansion rom */ - - /* - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - */ - out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out32r(PCIL0_PIM0LAH, 0); - out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); - - out32r(PCIL0_BAR0, 0); - - /* Program the board's subsystem id/vendor id */ - out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - - out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - #if defined(CONFIG_PCI) /* * Override weak is_pci_host() diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index 40017f4d6..20e134b63 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -77,6 +77,7 @@ #include <asm/4xx_pci.h> #endif #include <asm/processor.h> +#include <asm/io.h> #include <pci.h> #ifdef CONFIG_PCI @@ -499,6 +500,111 @@ int __is_pci_host(struct pci_controller *hose) int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host"))); +/* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + */ +#if defined(CONFIG_SYS_PCI_TARGET_INIT) +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX) +void __pci_target_init(struct pci_controller *hose) +{ + /* + * Set up Direct MMIO registers + */ + + /* + * PowerPC440 EP PCI Master configuration. + * Map one 1Gig range of PLB/processor addresses to PCI memory space. + * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF + * Use byte reversed out routines to handle endianess. + * Make this region non-prefetchable. + */ + /* PMM0 Mask/Attribute - disabled b4 setting */ + out_le32((void *)PCIL0_PMM0MA, 0x00000000); + /* PMM0 Local Address */ + out_le32((void *)PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); + /* PMM0 PCI Low Address */ + out_le32((void *)PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); + /* PMM0 PCI High Address */ + out_le32((void *)PCIL0_PMM0PCIHA, 0x00000000); + /* 512M + No prefetching, and enable region */ + out_le32((void *)PCIL0_PMM0MA, 0xE0000001); + + /* PMM1 Mask/Attribute - disabled b4 setting */ + out_le32((void *)PCIL0_PMM1MA, 0x00000000); + /* PMM1 Local Address */ + out_le32((void *)PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); + /* PMM1 PCI Low Address */ + out_le32((void *)PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); + /* PMM1 PCI High Address */ + out_le32((void *)PCIL0_PMM1PCIHA, 0x00000000); + /* 512M + No prefetching, and enable region */ + out_le32((void *)PCIL0_PMM1MA, 0xE0000001); + + out_le32((void *)PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out_le32((void *)PCIL0_PTM1LA, 0); /* Local Addr. Reg */ + out_le32((void *)PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ + out_le32((void *)PCIL0_PTM2LA, 0); /* Local Addr. Reg */ + + /* + * Set up Configuration registers + */ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); +} +#else /* defined(CONFIG_440EP) ... */ +void __pci_target_init(struct pci_controller * hose) +{ + /* + * Disable everything + */ + out_le32((void *)PCIL0_PIM0SA, 0); /* disable */ + out_le32((void *)PCIL0_PIM1SA, 0); /* disable */ + out_le32((void *)PCIL0_PIM2SA, 0); /* disable */ + out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */ + + /* + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 + * strapping options do not support sizes such as 128/256 MB. + */ + out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); + out_le32((void *)PCIL0_PIM0LAH, 0); + out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); + out_le32((void *)PCIL0_BAR0, 0); + + /* + * Program the board's subsystem id/vendor id + */ + out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); + out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); + + out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_440EP) ... */ +void pci_target_init(struct pci_controller * hose) + __attribute__((weak, alias("__pci_target_init"))); + +#endif /* defined(CONFIG_SYS_PCI_TARGET_INIT) */ + int pci_440_init (struct pci_controller *hose) { int reg_num = 0; diff --git a/include/asm-ppc/4xx_pci.h b/include/asm-ppc/4xx_pci.h index 30125a19e..5400a035e 100644 --- a/include/asm-ppc/4xx_pci.h +++ b/include/asm-ppc/4xx_pci.h @@ -49,4 +49,6 @@ #define PCIDEVID_405GP 0x0 +void __pci_target_init(struct pci_controller *hose); + #endif diff --git a/include/configs/DU440.h b/include/configs/DU440.h index e9ea1bf7d..65dc2359d 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -60,8 +60,9 @@ #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 -#define CONFIG_SYS_PCI_IOBASE 0xe8000000 - +#define CONFIG_SYS_PCI_IOBASE 0xe8000000 +#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH +#define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */ /* Don't change either of these */ #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index d6e2f6bc5..d2c5188a6 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -440,6 +440,8 @@ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ #define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */ #define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */ +/* for weak __pci_target_init() */ +#define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH #define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC #define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST diff --git a/include/configs/korat.h b/include/configs/korat.h index ea6ba8938..7e74ef705 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -69,6 +69,7 @@ #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000) /* Don't change either of these */ #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ |