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| author | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 | 
|---|---|---|
| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 | 
| commit | cb5473205206c7f14cbb1e747f28ec75b48826e2 (patch) | |
| tree | 8f4808d60917100b18a10b05230f7638a0a9bbcc /lib_ppc/cache.c | |
| parent | baf449fc5ff96f071bb0e3789fd3265f6d4fd9a0 (diff) | |
| parent | 92c78a3bbcb2ce508b4bf1c4a1e0940406a024bb (diff) | |
| download | olio-uboot-2014.01-cb5473205206c7f14cbb1e747f28ec75b48826e2.tar.xz olio-uboot-2014.01-cb5473205206c7f14cbb1e747f28ec75b48826e2.zip | |
Merge branch 'fixes' into cleanups
Conflicts:
	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h
Diffstat (limited to 'lib_ppc/cache.c')
| -rw-r--r-- | lib_ppc/cache.c | 36 | 
1 files changed, 17 insertions, 19 deletions
| diff --git a/lib_ppc/cache.c b/lib_ppc/cache.c index 5bfb22070..1292b71e6 100644 --- a/lib_ppc/cache.c +++ b/lib_ppc/cache.c @@ -25,29 +25,27 @@  #include <asm/cache.h>  #include <watchdog.h> -void flush_cache (ulong start_addr, ulong size) +void flush_cache(ulong start_addr, ulong size)  {  #ifndef CONFIG_5xx -	ulong addr, end_addr = start_addr + size; +	ulong addr, start, end; -	if (CFG_CACHELINE_SIZE) { -		addr = start_addr & (CFG_CACHELINE_SIZE - 1); -		for (addr = start_addr; -		     addr < end_addr; -		     addr += CFG_CACHELINE_SIZE) { -			asm ("dcbst 0,%0": :"r" (addr)); -			WATCHDOG_RESET(); -		} -		asm ("sync");	/* Wait for all dcbst to complete on bus */ +	start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); +	end = start_addr + size - 1; -		for (addr = start_addr; -		     addr < end_addr; -		     addr += CFG_CACHELINE_SIZE) { -			asm ("icbi 0,%0": :"r" (addr)); -			WATCHDOG_RESET(); -		} +	for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) { +		asm volatile("dcbst 0,%0" : : "r" (addr) : "memory"); +		WATCHDOG_RESET();  	} -	asm ("sync");		/* Always flush prefetch queue in any case */ -	asm ("isync"); +	/* wait for all dcbst to complete on bus */ +	asm volatile("sync" : : : "memory"); + +	for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) { +		asm volatile("icbi 0,%0" : : "r" (addr) : "memory"); +		WATCHDOG_RESET(); +	} +	asm volatile("sync" : : : "memory"); +	/* flush prefetch queue */ +	asm volatile("isync" : : : "memory");  #endif  } |