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authorStefan Roese <sr@denx.de>2008-10-21 11:43:08 +0200
committerStefan Roese <sr@denx.de>2008-10-21 11:43:08 +0200
commitf61f1e150c84f5b9347fca79a4bc5f2286c545d2 (patch)
treeab90f076f18e56b2b3e8c9375b95917daa78c1d9 /include/asm-ppc/cache.h
parentec081c2c190148b374e86a795fb6b1c49caeb549 (diff)
parentf82642e33899766892499b163e60560fbbf87773 (diff)
downloadolio-uboot-2014.01-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.tar.xz
olio-uboot-2014.01-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.zip
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'include/asm-ppc/cache.h')
-rw-r--r--include/asm-ppc/cache.h11
1 files changed, 6 insertions, 5 deletions
diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h
index 9d9b9717d..7252be7db 100644
--- a/include/asm-ppc/cache.h
+++ b/include/asm-ppc/cache.h
@@ -19,10 +19,10 @@
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/*
- * For compatibility reasons support the CFG_CACHELINE_SIZE too
+ * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
*/
-#ifndef CFG_CACHELINE_SIZE
-#define CFG_CACHELINE_SIZE L1_CACHE_BYTES
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
#endif
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
@@ -44,9 +44,10 @@ extern void clean_dcache_range(unsigned long start, unsigned long stop);
extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
extern void flush_dcache(void);
extern void invalidate_dcache(void);
-#ifdef CFG_INIT_RAM_LOCK
+extern void invalidate_icache(void);
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
extern void unlock_ram_in_cache(void);
-#endif /* CFG_INIT_RAM_LOCK */
+#endif /* CONFIG_SYS_INIT_RAM_LOCK */
#endif /* __ASSEMBLY__ */
/* prep registers for L2 */