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| author | wdenk <wdenk> | 2002-04-01 14:29:03 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2002-04-01 14:29:03 +0000 |
| commit | e85390dc1d9c3c942c11bbf003e6c10a73e25ed6 (patch) | |
| tree | 83d81d12872d2e8f9eff4e5098c21411193368ca /include/405gp_pci.h | |
| parent | a6b6b68640e4cfa2159e1f0709932c23f4974c6b (diff) | |
| download | olio-uboot-2014.01-e85390dc1d9c3c942c11bbf003e6c10a73e25ed6.tar.xz olio-uboot-2014.01-e85390dc1d9c3c942c11bbf003e6c10a73e25ed6.zip | |
Initial revision
Diffstat (limited to 'include/405gp_pci.h')
| -rw-r--r-- | include/405gp_pci.h | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/include/405gp_pci.h b/include/405gp_pci.h new file mode 100644 index 000000000..3c1adec19 --- /dev/null +++ b/include/405gp_pci.h @@ -0,0 +1,52 @@ +#ifndef _405GP_PCI_H +#define _405GP_PCI_H + +/*----------------------------------------------------------------------------+ +| 405GP PCI core memory map defines. ++----------------------------------------------------------------------------*/ +#define MIN_PCI_MEMADDR1 0x80000000 +#define MIN_PCI_MEMADDR2 0x00000000 +#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */ +#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */ +#define MAX_PCI_DEVICES 32 + +/*----------------------------------------------------------------------------+ +| Defines for the 405GP PCI Config address and data registers followed by +| defines for the standard PCI device configuration header. ++----------------------------------------------------------------------------*/ +#define PCICFGADR 0xEEC00000 +#define PCICFGDATA 0xEEC00004 + +#define PCIBUSNUM 0x40 /* 405GP specific parameters */ +#define PCISUBBUSNUM 0x41 +#define PCIDISCOUNT 0x42 +#define PCIBRDGOPT1 0x4A +#define PCIBRDGOPT2 0x60 + +/*----------------------------------------------------------------------------+ +| Defines for 405GP PCI Master local configuration regs. ++----------------------------------------------------------------------------*/ +#define PMM0LA 0xEF400000 +#define PMM0MA 0xEF400004 +#define PMM0PCILA 0xEF400008 +#define PMM0PCIHA 0xEF40000C +#define PMM1LA 0xEF400010 +#define PMM1MA 0xEF400014 +#define PMM1PCILA 0xEF400018 +#define PMM1PCIHA 0xEF40001C +#define PMM2LA 0xEF400020 +#define PMM2MA 0xEF400024 +#define PMM2PCILA 0xEF400028 +#define PMM2PCIHA 0xEF40002C + +/*----------------------------------------------------------------------------+ +| Defines for 405GP PCI Target local configuration regs. ++----------------------------------------------------------------------------*/ +#define PTM1MS 0xEF400030 +#define PTM1LA 0xEF400034 +#define PTM2MS 0xEF400038 +#define PTM2LA 0xEF40003C + +#define PCIDEVID_405GP 0x0 + +#endif |