Cleanup: fix "MHz" spelling

Signed-off-by: Wolfgang Denk <wd@denx.de>

8 files changed, 9 insertions, 9 deletions

diff --git a/drivers/block/sym53c8xx.c b/drivers/block/sym53c8xx.c
index 0c60bf80e..8094b415a 100644
--- a/drivers/block/sym53c8xx.c
+++ b/drivers/block/sym53c8xx.c
@@ -836,10 +836,10 @@ void scsi_chip_init(void)
 	scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */
 	scsi_write_byte(SCNTL1,0x00);
 	scsi_write_byte(SCNTL2,0x00);
-#ifndef CONFIG_SYS_SCSI_SYM53C8XX_CCF    /* config value for none 40 mhz clocks */
+#ifndef CONFIG_SYS_SCSI_SYM53C8XX_CCF    /* config value for none 40 MHz clocks */
 	scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */
 #else
-	scsi_write_byte(SCNTL3,CONFIG_SYS_SCSI_SYM53C8XX_CCF); /* config value for none 40 mhz clocks */
+	scsi_write_byte(SCNTL3,CONFIG_SYS_SCSI_SYM53C8XX_CCF); /* config value for none 40 MHz clocks */
 #endif
 	scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */
 	scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */
diff --git a/drivers/i2c/omap1510_i2c.c b/drivers/i2c/omap1510_i2c.c
index a4e6227c5..f91ee8884 100644
--- a/drivers/i2c/omap1510_i2c.c
+++ b/drivers/i2c/omap1510_i2c.c
@@ -32,7 +32,7 @@ void i2c_init (int speed, int slaveadd)
 		udelay (5000);
 	}
 
-	/* 12Mhz I2C module clock */
+	/* 12MHz I2C module clock */
 	outw (0, I2C_PSC);
 	outw (I2C_CON_EN, I2C_CON);
 	outw (0, I2C_SYSTEST);
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 134dccb61..d2e8207c5 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -45,7 +45,7 @@ void i2c_init (int speed, int slaveadd)
 		udelay (50000);
 	}
 
-	/* 12Mhz I2C module clock */
+	/* 12MHz I2C module clock */
 	outw (0, I2C_PSC);
 	speed = speed/1000;		    /* 100 or 400 */
 	scl = ((12000/(speed*2)) - 7);	/* use 7 when PSC = 0 */
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c
index ff8d2d7c0..ce12c3b62 100644
--- a/drivers/net/natsemi.c
+++ b/drivers/net/natsemi.c
@@ -409,7 +409,7 @@ natsemi_initialize(bd_t * bis)
    The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses.  */
 
 /* Delay between EEPROM clock transitions.
-   No extra delay is needed with 33Mhz PCI, but future 66Mhz
+   No extra delay is needed with 33MHz PCI, but future 66MHz
    access may need a delay. */
 #define eeprom_delay(ee_addr)	INL(dev, ee_addr)
 
diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c
index a2d61afec..198f73dee 100644
--- a/drivers/net/ns8382x.c
+++ b/drivers/net/ns8382x.c
@@ -445,7 +445,7 @@ ns8382x_initialize(bd_t * bis)
 	Read and write MII registers using software-generated serial MDIO
 	protocol.  See the MII specifications or DP83840A data sheet for details.
 
-	The maximum data clock rate is 2.5 Mhz.  To meet minimum timing we
+	The maximum data clock rate is 2.5 MHz.  To meet minimum timing we
 	must flush writes to the PCI bus with a PCI read. */
 #define mdio_delay(mdio_addr) INL(dev, mdio_addr)
 
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index d378ce39b..db8a727c8 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -287,7 +287,7 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
 
 /*
 	Delay between EEPROM clock transitions.
-	No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
+	No extra delay is needed with 33MHz PCI, but 66MHz may change this.
 */
 
 #define eeprom_delay()	inl(ee_addr)
diff --git a/drivers/net/tigon3.c b/drivers/net/tigon3.c
index ab448b0f8..e4e004eed 100644
--- a/drivers/net/tigon3.c
+++ b/drivers/net/tigon3.c
@@ -2247,7 +2247,7 @@ LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice)
 	REG_WR (pDevice, Grc.Mode, Value32);
 
 	/* Setup the timer prescalar register. */
-	REG_WR (pDevice, Grc.MiscCfg, 65 << 1);	/* Clock is alwasy 66Mhz. */
+	REG_WR (pDevice, Grc.MiscCfg, 65 << 1);	/* Clock is alwasy 66MHz. */
 
 	/* Set up the MBUF pool base address and size. */
 	REG_WR (pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
diff --git a/drivers/usb/usbdcore_mpc8xx.c b/drivers/usb/usbdcore_mpc8xx.c
index fa02003d1..53bde0dca 100644
--- a/drivers/usb/usbdcore_mpc8xx.c
+++ b/drivers/usb/usbdcore_mpc8xx.c
@@ -1227,7 +1227,7 @@ static void mpc8xx_udc_clock_init (volatile immap_t * immr,
 		return;
 	}
 
-	/* Assume the brgclk is 'good enough', we want !(gd->cpu_clk%48Mhz)
+	/* Assume the brgclk is 'good enough', we want !(gd->cpu_clk%48MHz)
 	 * but, can /probably/ live with close-ish alternative rates.
 	 */
 	divisor = (gd->cpu_clk / 48000000L) - 1;