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| author | Armando Visconti <armando.visconti@st.com> | 2012-03-26 00:09:55 +0000 |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2012-04-04 10:47:09 -0500 |
| commit | aa51005c3f7e517164fa000d68672041f6c4191f (patch) | |
| tree | 83108435981ec813e9f8bcb007237021bd8245f5 /drivers/net/designware.c | |
| parent | 024333c96fecb698efe703e01f2326c1256114a4 (diff) | |
| download | olio-uboot-2014.01-aa51005c3f7e517164fa000d68672041f6c4191f.tar.xz olio-uboot-2014.01-aa51005c3f7e517164fa000d68672041f6c4191f.zip | |
net/designware: Consecutive writes must have delay
This patch solves a TX/RX problem which happens at 10Mbps, due to the
fact that we are not respecting 4 cyles of the phy_clk (2.5MHz) between
two consecutive writes on the same register.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Diffstat (limited to 'drivers/net/designware.c')
| -rw-r--r-- | drivers/net/designware.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index fc14b7042..933032cfd 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -175,8 +175,7 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); - writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf); - writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf); + writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); return 0; } |