Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm: (212 commits)
  ARM: cache: Move the cp15 CR register read before flushing the cache.
  ARM: introduce arch_early_init_r()
  PXA: Enable CONFIG_PREBOOT on zipitz2
  ARM: mx28: Remove CONFIG_ARCH_CPU_INIT
  No need to define CONFIG_ARCH_CPU_INIT.
  add new board vl_ma2sc
  MTD: SPEAr SMI: Add write support for length < 4 bytes
  i2c: designware_i2c.c: Add support for the "i2c probe" command
  rtc/m41t62: Add support for M41T82 with HT (Halt Update)
  SPL: ARM: spear: Add SPL support for SPEAr600 platform
  Makefile: Add u-boot.spr build target (SPEAr)
  SPL: ARM: spear: Remove some objects from SPL build
  SPL: lib/Makefile: Add crc32.c to SPL build
  SPL: common/Makefile: Add image.c to SPL build
  arm: Don't use printf() in SPL builds
  GPIO: Add SPEAr GPIO driver
  net: Multiple updates/enhancements to designware.c
  cleanup/SPEAr: Define configuration flags more elegantly
  cleanup/SPEAr: Remove unnecessary parenthesis
  SPEAr: Correct SoC ID offset in misc configuration space
  SPEAr: explicitly select clk src for UART
  SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access
  SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb
  SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro
  SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE
  SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION
  SPEAr: Enable dcache for fast file transfer
  SPEAr: Enable autoneg for ethernet
  SPEAr: Enable udc and usb-console support only for usbtty configuration
  SPEAr: Enable usb device high speed support
  SPEAr: Initialize SNOR in early_board_init_f
  SPEAr: Change the default environment variables
  SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK)
  SPEAr: Add configuration options for spear3xx and spear6xx boards
  SPEAr: Add basic arch related support for SPEAr SoCs
  SPEAr: Add interface information in initialization
  SPEAr: Add macb driver support for spear310 and spear320
  SPEAr: Configure network support for spear SoCs
  SPEAr: Place ethaddr write and read within CONFIG_CMD_NET
  SPEAr: Eliminate dependency on Xloader table
  SPEAr: Fix ARM relocation support
  st_smi: Fixed page size for Winbond W25Q128FV flash
  st_smi: Change timeout loop implementation
  st_smi: Fix bug in flash_print_info()
  st_smi: Change the flash probing method
  st_smi: Removed no needed dependency on ST_M25Pxx_ID
  st_smi: Fix smi read status
  st_smi: Move status register read before modifying ctrl register
  st_smi: Read status until timeout happens
  st_smi: Enhance the error handling
  st_smi: Change SMI timeout values
  st_smi: Return error in case TFF is not set
  st_smi: Add support for SPEAr SMI driver
  mtd/NAND: Remove obsolete SPEAr specific NAND drivers
  SPEAr: Configure FSMC driver for NAND interface
  mtd/NAND: Add FSMC driver support
  arm/km: remove calls to kw_gpio_* in board_early_init_f
  arm/km: add implementation for read_dip_switch
  arm/km: support the 2 PCIe fpga resets
  arm/km: skip FPGA config when already configured
  arm/km: redefine piggy 4 reg names to avoid conflicts
  arm/km: cleanup km_kirkwood boards
  arm/km: enable BOCO2 FPGA download support
  arm/km: remove portl2.h and use km_kirkwood instead
  arm/km: convert mgcoge3un target to km_kirkwood
  arm/km: add kmcoge5un board support
  arm/km: add kmnusa board support
  arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
  cm-t35: fix incorrect NAND_ECC layout selection
  ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls.
  ARM: OMAP4/5: Move USB pads to essential list.
  ARM: OMAP4/5: Move USB clocks to essential group.
  ARM: OMAP4/5: Move gpmc clocks to essential group.
  ARM: OMAP4+: Move external phy initialisations to arch specific place.
  omap4: Use a smaller M,N couple for IVA DPLL
  da850/omap-l138: Enable auto negotiation in RMII mode
  omap: am33xx: accomodate input clocks other than 24 Mhz
  omap: emif: fix bug in manufacturer code test
  omap: emif: deal with rams that return duplicate mr data on all byte lanes
  OMAP4+: Force DDR in self-refresh after warm reset
  OMAP4+: Handle sdram init after warm reset
  ARM: OMAP3+: Detect reset type
  arm: bugfix: Move vector table before jumping relocated code
  Kirkwood: Add support for Ka-Ro TK71
  arm/km: use spi claim bus to switch between SPI and NAND
  arm/kirkwood: protect the ENV_SPI #defines
  ARM: don't probe PHY address for LaCie boards
  lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2
  lacie_kw: fix SDRAM banks number for net2big_v2
  Kirkwood: add lschlv2 and lsxhl board support
  net: add helper to generate random mac address
  net: use common rand()/srand() functions
  lib: add rand() function
  kwboot: boot kirkwood SoCs over a serial link
  kw_spi: add weak functions board_spi_claim/release_bus
  kw_spi: support spi_claim/release_bus functions
  kw_spi: backup and reset the MPP of the chosen CS pin
  kirkwood: fix calls to kirkwood_mpp_conf
  kirkwood: add save functionality kirkwood_mpp_conf function
  km_arm: use filesize for erase in update command
  arm/km: enable mii cmd
  arm/km: remove CONFIG_RESET_PHY_R
  arm/km: change maintainer for mgcoge3un
  arm/km: fix wrong comment in SDRAM config for mgcoge3un
  arm/km: use ARRAY_SIZE macro
  arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE
  arm/km: add piggy mac adress offset for mgcoge3un
  arm/km: add board type to boards.cfg
  AT91SAM9*: Change kernel address in dataflash to match u-boot's size
  ATMEL/PIO: Enable new feature of PIO on Atmel device
  ehci-atmel: fix compiler warning
  AT91: at91sam9m10g45ek : Enable EHCI instead OHCI
  Atmel : usb : add EHCI driver for Atmel SoC
  Fix: AT91SAM9263 nor flash usage
  Fix: broken boot message at serial line on AT91SAM9263-EK board
  i.MX6 USDHC: Use the ESDHC clock
  mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
  i.MX28: Add function to adjust memory parameters
  mx28evk: Fix PSWITCH key position
  mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition
  mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition
  imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53ard: Remove unused CONFIG_MII_GASKET
  mx6: Avoid writing to read-only bits in imximage.cfg
  m28evk: use same notation to alloc the 128kB stack
  ...

Signed-off-by: Wolfgang Denk <wd@denx.de>

1 files changed, 262 insertions, 0 deletions

diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c
new file mode 100644
index 000000000..60ec6e3d7
--- /dev/null
+++ b/drivers/gpio/tegra_gpio.c
@@ -0,0 +1,262 @@
+/*
+ * NVIDIA Tegra2 GPIO handling.
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
+ * Tom Warren (twarren@nvidia.com)
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <asm/arch/tegra2.h>
+#include <asm/gpio.h>
+
+enum {
+	TEGRA2_CMD_INFO,
+	TEGRA2_CMD_PORT,
+	TEGRA2_CMD_OUTPUT,
+	TEGRA2_CMD_INPUT,
+};
+
+static struct gpio_names {
+	char name[GPIO_NAME_SIZE];
+} gpio_names[MAX_NUM_GPIOS];
+
+static char *get_name(int i)
+{
+	return *gpio_names[i].name ? gpio_names[i].name : "UNKNOWN";
+}
+
+/* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */
+static int get_config(unsigned gpio)
+{
+	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+	u32 u;
+	int type;
+
+	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
+	type =  (u >> GPIO_BIT(gpio)) & 1;
+
+	debug("get_config: port = %d, bit = %d is %s\n",
+		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
+
+	return type;
+}
+
+/* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */
+static void set_config(unsigned gpio, int type)
+{
+	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+	u32 u;
+
+	debug("set_config: port = %d, bit = %d, %s\n",
+		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
+
+	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
+	if (type)				/* GPIO */
+		u |= 1 << GPIO_BIT(gpio);
+	else
+		u &= ~(1 << GPIO_BIT(gpio));
+	writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
+}
+
+/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
+static int get_direction(unsigned gpio)
+{
+	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+	u32 u;
+	int dir;
+
+	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
+	dir =  (u >> GPIO_BIT(gpio)) & 1;
+
+	debug("get_direction: port = %d, bit = %d, %s\n",
+		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
+
+	return dir;
+}
+
+/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
+static void set_direction(unsigned gpio, int output)
+{
+	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+	u32 u;
+
+	debug("set_direction: port = %d, bit = %d, %s\n",
+		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
+
+	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
+	if (output)
+		u |= 1 << GPIO_BIT(gpio);
+	else
+		u &= ~(1 << GPIO_BIT(gpio));
+	writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
+}
+
+/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
+static void set_level(unsigned gpio, int high)
+{
+	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+	u32 u;
+
+	debug("set_level: port = %d, bit %d == %d\n",
+		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
+
+	u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
+	if (high)
+		u |= 1 << GPIO_BIT(gpio);
+	else
+		u &= ~(1 << GPIO_BIT(gpio));
+	writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
+}
+
+/*
+ * Generic_GPIO primitives.
+ */
+
+int gpio_request(unsigned gpio, const char *label)
+{
+	if (gpio >= MAX_NUM_GPIOS)
+		return -1;
+
+	if (label != NULL) {
+		strncpy(gpio_names[gpio].name, label, GPIO_NAME_SIZE);
+		gpio_names[gpio].name[GPIO_NAME_SIZE - 1] = '\0';
+	}
+
+	/* Configure as a GPIO */
+	set_config(gpio, 1);
+
+	return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+	if (gpio >= MAX_NUM_GPIOS)
+		return -1;
+
+	gpio_names[gpio].name[0] = '\0';
+	/* Do not configure as input or change pin mux here */
+	return 0;
+}
+
+/* read GPIO OUT value of pin 'gpio' */
+static int gpio_get_output_value(unsigned gpio)
+{
+	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+	int val;
+
+	debug("gpio_get_output_value: pin = %d (port %d:bit %d)\n",
+		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
+
+	val = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
+
+	return (val >> GPIO_BIT(gpio)) & 1;
+}
+
+/* set GPIO pin 'gpio' as an input */
+int gpio_direction_input(unsigned gpio)
+{
+	debug("gpio_direction_input: pin = %d (port %d:bit %d)\n",
+		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
+
+	/* Configure GPIO direction as input. */
+	set_direction(gpio, 0);
+
+	return 0;
+}
+
+/* set GPIO pin 'gpio' as an output, with polarity 'value' */
+int gpio_direction_output(unsigned gpio, int value)
+{
+	debug("gpio_direction_output: pin = %d (port %d:bit %d) = %s\n",
+		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio),
+		value ? "HIGH" : "LOW");
+
+	/* Configure GPIO output value. */
+	set_level(gpio, value);
+
+	/* Configure GPIO direction as output. */
+	set_direction(gpio, 1);
+
+	return 0;
+}
+
+/* read GPIO IN value of pin 'gpio' */
+int gpio_get_value(unsigned gpio)
+{
+	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+	int val;
+
+	debug("gpio_get_value: pin = %d (port %d:bit %d)\n",
+		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
+
+	val = readl(&bank->gpio_in[GPIO_PORT(gpio)]);
+
+	return (val >> GPIO_BIT(gpio)) & 1;
+}
+
+/* write GPIO OUT value to pin 'gpio' */
+int gpio_set_value(unsigned gpio, int value)
+{
+	debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
+		gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
+
+	/* Configure GPIO output value. */
+	set_level(gpio, value);
+
+	return 0;
+}
+
+/*
+ * Display Tegra GPIO information
+ */
+void gpio_info(void)
+{
+	unsigned c;
+	int type;
+
+	for (c = 0; c < MAX_NUM_GPIOS; c++) {
+		type = get_config(c);		/* GPIO, not SFPIO */
+		if (type) {
+			printf("GPIO_%d:\t%s is an %s, ", c,
+				get_name(c),
+				get_direction(c) ? "OUTPUT" : "INPUT");
+			if (get_direction(c))
+				printf("value = %d", gpio_get_output_value(c));
+			else
+				printf("value = %d", gpio_get_value(c));
+			printf("\n");
+		} else
+			continue;
+	}
+}