diff options
| author | Michal Simek <monstr@monstr.eu> | 2007-05-08 00:32:35 +0200 | 
|---|---|---|
| committer | Michal Simek <monstr@monstr.eu> | 2007-05-08 00:32:35 +0200 | 
| commit | 3c4bd60de15d79ddfc0cf3170a55847b2025d93f (patch) | |
| tree | 891b84b58f13a5f45536a243585b9d94c253a410 /cpu/mpc86xx/interrupts.c | |
| parent | fb05f6da35ea1c15c553abe6f23f656bf18dc5db (diff) | |
| parent | ac4cd59d59c9bf3f89cb7a344abf8184d678f562 (diff) | |
| download | olio-uboot-2014.01-3c4bd60de15d79ddfc0cf3170a55847b2025d93f.tar.xz olio-uboot-2014.01-3c4bd60de15d79ddfc0cf3170a55847b2025d93f.zip  | |
Merge git://www.denx.de/git/u-boot
Conflicts:
	include/asm-microblaze/microblaze_intc.h
	include/linux/stat.h
Diffstat (limited to 'cpu/mpc86xx/interrupts.c')
| -rw-r--r-- | cpu/mpc86xx/interrupts.c | 20 | 
1 files changed, 20 insertions, 0 deletions
diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 1df6cdc5b..49820bbd8 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -80,6 +80,26 @@ int interrupt_init(void)  {  	int ret; +	/* +	 * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to +	 * implement PEX10 errata.  As INT is active high, it +	 * will cause core to take 0x500 interrupt. +	 * +	 * Due to the PIC's default pass through mode, as soon +	 * as interrupts are enabled (MSR[EE] = 1), an interrupt +	 * will be taken and u-boot will hang.  This is due to a +	 * hardware change (per an errata fix) on new revisions +	 * of the board with Rev 2.x parts. +	 * +	 * Setting the PIC to mixed mode prevents the hang. +	 */ +	if ((get_svr() & 0xf0) == 0x20) { +		volatile immap_t *immr = (immap_t *)CFG_IMMR; +		immr->im_pic.gcr = MPC86xx_PICGCR_RST; +		while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); +		immr->im_pic.gcr = MPC86xx_PICGCR_MODE; +	} +  	/* call cpu specific function from $(CPU)/interrupts.c */  	ret = interrupt_init_cpu(&decrementer_count);  |