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| author | Jon Loeliger <jdl@freescale.com> | 2005-07-25 14:05:07 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2005-07-25 14:05:07 -0500 |
| commit | d9b94f28a442b0013caef99de084d7b72e2d4607 (patch) | |
| tree | 1b293a551e021a4a696717231ec03206d9f172de /cpu/mpc85xx/tsec.h | |
| parent | 288693abe1f7c23e69479fd85c2c0d8d7fdbf8f2 (diff) | |
| download | olio-uboot-2014.01-d9b94f28a442b0013caef99de084d7b72e2d4607.tar.xz olio-uboot-2014.01-d9b94f28a442b0013caef99de084d7b72e2d4607.zip | |
* Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board.
Added DDR II support based on SPD values for MPC85xx boards.
This roll-up patch also includes bugfies for the previously
published patches:
DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
Diffstat (limited to 'cpu/mpc85xx/tsec.h')
| -rw-r--r-- | cpu/mpc85xx/tsec.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/cpu/mpc85xx/tsec.h b/cpu/mpc85xx/tsec.h index e24351a2e..d1c70aa89 100644 --- a/cpu/mpc85xx/tsec.h +++ b/cpu/mpc85xx/tsec.h @@ -51,6 +51,7 @@ #define ECNTRL_INIT_SETTINGS 0x00001000 #define ECNTRL_TBI_MODE 0x00000020 +#define ECNTRL_R100 0x00000008 #define miim_end -2 #define miim_read -1 @@ -107,6 +108,7 @@ /* Cicada 8204 Extended PHY Control Register 1 */ #define MIIM_CIS8204_EPHY_CON 0x17 #define MIIM_CIS8204_EPHYCON_INIT 0x0006 +#define MIIM_CIS8204_EPHYCON_RGMII 0x1000 /* Cicada 8204 Serial LED Control Register */ #define MIIM_CIS8204_SLED_CON 0x1b @@ -424,12 +426,18 @@ typedef struct tsec uint resc00[256]; } tsec_t; +#define TSEC_GIGABIT (1) + +/* This flag currently only has + * meaning if we're using the eTSEC */ +#define TSEC_REDUCED (1 << 1) + struct tsec_private { volatile tsec_t *regs; volatile tsec_t *phyregs; struct phy_info *phyinfo; uint phyaddr; - uint gigabit; + u32 flags; uint link; uint duplexity; uint speed; |