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| author | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
|---|---|---|
| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
| commit | cb5473205206c7f14cbb1e747f28ec75b48826e2 (patch) | |
| tree | 8f4808d60917100b18a10b05230f7638a0a9bbcc /cpu/mcf547x_8x/slicetimer.c | |
| parent | baf449fc5ff96f071bb0e3789fd3265f6d4fd9a0 (diff) | |
| parent | 92c78a3bbcb2ce508b4bf1c4a1e0940406a024bb (diff) | |
| download | olio-uboot-2014.01-cb5473205206c7f14cbb1e747f28ec75b48826e2.tar.xz olio-uboot-2014.01-cb5473205206c7f14cbb1e747f28ec75b48826e2.zip | |
Merge branch 'fixes' into cleanups
Conflicts:
board/atmel/atngw100/atngw100.c
board/atmel/atstk1000/atstk1000.c
cpu/at32ap/at32ap700x/gpio.c
include/asm-avr32/arch-at32ap700x/clk.h
include/configs/atngw100.h
include/configs/atstk1002.h
include/configs/atstk1003.h
include/configs/atstk1004.h
include/configs/atstk1006.h
include/configs/favr-32-ezkit.h
include/configs/hammerhead.h
include/configs/mimc200.h
Diffstat (limited to 'cpu/mcf547x_8x/slicetimer.c')
| -rw-r--r-- | cpu/mcf547x_8x/slicetimer.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/cpu/mcf547x_8x/slicetimer.c b/cpu/mcf547x_8x/slicetimer.c index 494f98f66..67e81894a 100644 --- a/cpu/mcf547x_8x/slicetimer.c +++ b/cpu/mcf547x_8x/slicetimer.c @@ -31,22 +31,22 @@ DECLARE_GLOBAL_DATA_PTR; static ulong timestamp; #if defined(CONFIG_SLTTMR) -#ifndef CFG_UDELAY_BASE +#ifndef CONFIG_SYS_UDELAY_BASE # error "uDelay base not defined!" #endif -#if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK) +#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK) # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!" #endif extern void dtimer_intr_setup(void); void udelay(unsigned long usec) { - volatile slt_t *timerp = (slt_t *) (CFG_UDELAY_BASE); + volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE); u32 now, freq; /* 1 us period */ - freq = CFG_TIMER_PRESCALER; + freq = CONFIG_SYS_TIMER_PRESCALER; timerp->cr = 0; /* Disable */ timerp->tcnt = usec * freq; @@ -62,10 +62,10 @@ void udelay(unsigned long usec) void dtimer_interrupt(void *not_used) { - volatile slt_t *timerp = (slt_t *) (CFG_TMR_BASE); + volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); /* check for timer interrupt asserted */ - if ((CFG_TMRPND_REG & CFG_TMRINTR_MASK) == CFG_TMRINTR_PEND) { + if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) { timerp->sr |= SLT_SR_ST; timestamp++; return; @@ -74,7 +74,7 @@ void dtimer_interrupt(void *not_used) void timer_init(void) { - volatile slt_t *timerp = (slt_t *) (CFG_TMR_BASE); + volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); timestamp = 0; @@ -83,10 +83,10 @@ void timer_init(void) timerp->sr = SLT_SR_BE | SLT_SR_ST; /* clear status */ /* initialize and enable timer interrupt */ - irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0); + irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0); /* Interrupt every ms */ - timerp->tcnt = 1000 * CFG_TIMER_PRESCALER; + timerp->tcnt = 1000 * CONFIG_SYS_TIMER_PRESCALER; dtimer_intr_setup(); |