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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-10-16 15:01:15 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:03 +0200 |
| commit | 6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch) | |
| tree | ae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /cpu/leon3/cpu_init.c | |
| parent | 71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff) | |
| download | olio-uboot-2014.01-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.xz olio-uboot-2014.01-6d0f6bcf337c5261c08fabe12982178c2c489d76.zip | |
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'cpu/leon3/cpu_init.c')
| -rw-r--r-- | cpu/leon3/cpu_init.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/cpu/leon3/cpu_init.c b/cpu/leon3/cpu_init.c index 4fe7d4b8d..be22ec26a 100644 --- a/cpu/leon3/cpu_init.c +++ b/cpu/leon3/cpu_init.c @@ -159,9 +159,9 @@ int init_memory_ctrl() mctrl = (ambapp_dev_mctrl *) base; /* config MCTRL memory controller */ - mctrl->mcfg1 = CFG_GRLIB_MEMCFG1 | (mctrl->mcfg1 & 0x300); - mctrl->mcfg2 = CFG_GRLIB_MEMCFG2; - mctrl->mcfg3 = CFG_GRLIB_MEMCFG3; + mctrl->mcfg1 = CONFIG_SYS_GRLIB_MEMCFG1 | (mctrl->mcfg1 & 0x300); + mctrl->mcfg2 = CONFIG_SYS_GRLIB_MEMCFG2; + mctrl->mcfg3 = CONFIG_SYS_GRLIB_MEMCFG3; not_found_mctrl = 0; } @@ -171,9 +171,9 @@ int init_memory_ctrl() mctrl = (ambapp_dev_mctrl *) base; /* config MCTRL memory controller */ - mctrl->mcfg1 = CFG_GRLIB_FT_MEMCFG1 | (mctrl->mcfg1 & 0x300); - mctrl->mcfg2 = CFG_GRLIB_FT_MEMCFG2; - mctrl->mcfg3 = CFG_GRLIB_FT_MEMCFG3; + mctrl->mcfg1 = CONFIG_SYS_GRLIB_FT_MEMCFG1 | (mctrl->mcfg1 & 0x300); + mctrl->mcfg2 = CONFIG_SYS_GRLIB_FT_MEMCFG2; + mctrl->mcfg3 = CONFIG_SYS_GRLIB_FT_MEMCFG3; not_found_mctrl = 0; } @@ -183,7 +183,7 @@ int init_memory_ctrl() sdctrl = (ambapp_dev_sdctrl *) base; /* config memory controller */ - sdctrl->sdcfg = CFG_GRLIB_SDRAM; + sdctrl->sdcfg = CONFIG_SYS_GRLIB_SDRAM; not_found_mctrl = 0; } @@ -192,8 +192,8 @@ int init_memory_ctrl() ddr2spa = (ambapp_dev_ddr2spa *) ambapp_ahb_get_info(ahb, 1); /* Config DDR2 memory controller */ - ddr2spa->cfg1 = CFG_GRLIB_DDR2_CFG1; - ddr2spa->cfg3 = CFG_GRLIB_DDR2_CFG3; + ddr2spa->cfg1 = CONFIG_SYS_GRLIB_DDR2_CFG1; + ddr2spa->cfg3 = CONFIG_SYS_GRLIB_DDR2_CFG3; not_found_mctrl = 0; } @@ -202,7 +202,7 @@ int init_memory_ctrl() ddrspa = (ambapp_dev_ddrspa *) ambapp_ahb_get_info(ahb, 1); /* Config DDR memory controller */ - ddrspa->ctrl = CFG_GRLIB_DDR_CFG; + ddrspa->ctrl = CONFIG_SYS_GRLIB_DDR_CFG; not_found_mctrl = 0; } |