Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
  ARM: Add Calxeda Highbank platform
  dkb: make mmc command as default enabled
  Marvell: dkb: add mmc support
  ARM: pantheon: add mmc definition
  davinci: remove config.mk file from the sources
  ARM:AM33XX: Add support for TI AM335X EVM
  ARM:AM33XX: Added timer support
  ARM:AM33XX: Add emif/ddr support
  ARM:AM33XX: Add clock definitions
  ARM:AM33XX: Added support for AM33xx
  omap3/emif4: fix registers definition
  davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM
  davinci: emac: add support for more than 1 PHYs
  davinci: emac: add new features to autonegotiate for EMAC
  da850evm: Move LPSC configuration to board_early_init_f()
  omap4_panda: Build in cmd_gpio support on panda
  omap: Don't use gpio_free to change direction to input
  mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset
  OMAP3: overo : Add environment variable optargs to bootargs
  OMAP3: overo: Move ethernet CS4 configuration to execute based on board id
  OMAP3: overo : Use ttyO2 instead of ttyS2.
  da830: add support for NAND boot mode
  dm36x: revert cache disable patch
  dm644X: revert cache disable patch
  devkit8000: Add malloc space
  omap: spl: fix build break due to changes in FAT
  OMAP3 SPL: Provide weak omap_rev_string
  omap: beagle: Use ubifs instead of jffs2 for nand boot
  omap: overo: Disable pull-ups on camera PCLK, HS and VS signals
  omap: overo: Configure mux for gpio10
  SPL: Add DMA library
  omap3: Add interface for omap3 DMA
  omap3: Add DMA register accessors
  omap3: Add Base register for DMA
  arm, davinci: add missing LSPC define for MMC/SD1
  U-Boot/SPL: omap4: Make ddr pre-calculated timings as default.
  DaVinci: correct MDSTAT.STATE mask
  omap4: splitting padconfs into common, 4430 and 4460
  omap4: adding revision detection for 4460 ES1.1
  omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL
  gplug: fixed build error as a result of code cleanup patch
  kirkwood_spi: add dummy spi_init()
  gpio: mvmfp: reduce include platform file
  ARM: orion5x: reduce dependence of including platform file
  serial: reduce include platform file for marvell chip
  ARM: kirkwood: reduce dependence of including platform file
  ARM: armada100: reduce dependence of including platform file
  ARM: pantheon: reduce dependence of including platform file
  Armada100: Add env storage support for Marvell gplugD
  Armada100: Add SPI flash support for Marvell gplugD
  Armada100: Add SPI support for Marvell gplugD
  SPI: Add SPI driver support for Marvell Armada100
  dreamplug: initial board support.
  imx: fix coding style
  misc: pmic: drop old Freescale's pmic driver
  MX31: mx31pdk: use new pmic driver
  MX31: mx31ads: use new pmic driver
  MX31: mx31_litekit: use new pmic driver
  MX5: mx53evk: use new pmic driver
  MX5: mx51evk: use new pmic driver
  MX35: mx35pdk: use new pmic driver
  misc: pmic: addI2C  support to pmic_fsl driver
  misc: pmic: use I2C_SET_BUS in pmic I2C
  MX5: efikamx/efikasb: use new pmic driver
  MX3: qong: use new pmic driver
  RTC: Switch mc13783 to generic pmic code
  MX5: vision2: use new pmic driver
  misc: pmic: Freescale PMIC switches to generic PMIC driver
  misc:pmic:samsung Enable PMIC driver at GONI target
  misc:pmic:max8998 MAX8998 support at a new PMIC driver.
  misc:pmic:core New generic PMIC driver
  mx31pdk: Remove unneeded config
  mx31: provide readable WEIM CS accessor
  MX51: vision2: Set global macros
  I2C: Add i2c_get/set_speed() to mxc_i2c.c
  ARM: Update mach-types
  devkit8000: Add config to enable SPL MMC boot
  devkit8000: protect board_mmc_init
  arm, post: add missing post_time_ms for arm
  cosmetic, post: Codingstyle cleanup
  arm, logbuffer: make it compileclean
  tegra2: Enable MMC for Seaboard
  tegra2: Add more pinmux functions
  tegra2: Rename PIN_ to PINGRP_
  tegra2: Add more clock functions
  tegra2: Clean up board code a little
  tegra2: Rename CLOCK_PLL_ID to CLOCK_ID

1 files changed, 62 insertions, 175 deletions

diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 160dac8e1..d13537d16 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -43,24 +43,6 @@ const struct tegra2_sysinfo sysinfo = {
 	CONFIG_TEGRA2_BOARD_STRING
 };
 
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
-{
-	/* Initialize periph clocks */
-	clock_init();
-
-	/* Initialize periph pinmuxes */
-	pinmux_init();
-
-	/* Initialize periph GPIOs */
-	gpio_init();
-
-	/* Init UART, scratch regs, and start CPU */
-	tegra2_start();
-	return 0;
-}
-#endif	/* EARLY_INIT */
-
 /*
  * Routine: timer_init
  * Description: init the timestamp and lastinc value
@@ -70,62 +52,31 @@ int timer_init(void)
 	return 0;
 }
 
-/*
- * Routine: clock_init_uart
- * Description: init the PLL and clock for the UART(s)
- */
-static void clock_init_uart(void)
+static void enable_uart(enum periph_id pid)
 {
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_PERIPH];
-	u32 reg;
-
-	reg = readl(&pll->pll_base);
-	if (!(reg & PLL_BASE_OVRRIDE_MASK)) {
-		/* Override pllp setup for 216MHz operation. */
-		reg = PLL_BYPASS_MASK | PLL_BASE_OVRRIDE_MASK |
-			(1 << PLL_DIVP_SHIFT) | (0xc << PLL_DIVM_SHIFT);
-		reg |= (NVRM_PLLP_FIXED_FREQ_KHZ / 500) << PLL_DIVN_SHIFT;
-		writel(reg, &pll->pll_base);
-
-		reg |= PLL_ENABLE_MASK;
-		writel(reg, &pll->pll_base);
-
-		reg &= ~PLL_BYPASS_MASK;
-		writel(reg, &pll->pll_base);
-	}
-
-#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
 	/* Assert UART reset and enable clock */
-	reset_set_enable(PERIPH_ID_UART1, 1);
-	clock_enable(PERIPH_ID_UART1);
-
-	/* Enable pllp_out0 to UART */
-	reg = readl(&clkrst->crc_clk_src_uarta);
-	reg &= 0x3FFFFFFF;	/* UARTA_CLK_SRC = 00, PLLP_OUT0 */
-	writel(reg, &clkrst->crc_clk_src_uarta);
+	reset_set_enable(pid, 1);
+	clock_enable(pid);
+	clock_ll_set_source(pid, 0);	/* UARTx_CLK_SRC = 00, PLLP_OUT0 */
 
 	/* wait for 2us */
 	udelay(2);
 
 	/* De-assert reset to UART */
-	reset_set_enable(PERIPH_ID_UART1, 0);
+	reset_set_enable(pid, 0);
+}
+
+/*
+ * Routine: clock_init_uart
+ * Description: init the PLL and clock for the UART(s)
+ */
+static void clock_init_uart(void)
+{
+#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
+	enable_uart(PERIPH_ID_UART1);
 #endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
 #if defined(CONFIG_TEGRA2_ENABLE_UARTD)
-	/* Assert UART reset and enable clock */
-	reset_set_enable(PERIPH_ID_UART4, 1);
-	clock_enable(PERIPH_ID_UART4);
-
-	/* Enable pllp_out0 to UART */
-	reg = readl(&clkrst->crc_clk_src_uartd);
-	reg &= 0x3FFFFFFF;	/* UARTD_CLK_SRC = 00, PLLP_OUT0 */
-	writel(reg, &clkrst->crc_clk_src_uartd);
-
-	/* wait for 2us */
-	udelay(2);
-
-	/* De-assert reset to UART */
-	reset_set_enable(PERIPH_ID_UART4, 0);
+	enable_uart(PERIPH_ID_UART4);
 #endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
 }
 
@@ -135,66 +86,29 @@ static void clock_init_uart(void)
  */
 static void pin_mux_uart(void)
 {
-	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 reg;
-
 #if defined(CONFIG_TEGRA2_ENABLE_UARTA)
-	reg = readl(&pmt->pmt_ctl_c);
-	reg &= 0xFFF0FFFF;	/* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
-	writel(reg, &pmt->pmt_ctl_c);
+	pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
+	pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
 
-	pinmux_tristate_disable(PIN_IRRX);
-	pinmux_tristate_disable(PIN_IRTX);
+	pinmux_tristate_disable(PINGRP_IRRX);
+	pinmux_tristate_disable(PINGRP_IRTX);
 #endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
 #if defined(CONFIG_TEGRA2_ENABLE_UARTD)
-	reg = readl(&pmt->pmt_ctl_b);
-	reg &= 0xFFFFFFF3;	/* GMC_SEL [3:2] = 00, UARTD */
-	writel(reg, &pmt->pmt_ctl_b);
+	pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
 
-	pinmux_tristate_disable(PIN_GMC);
+	pinmux_tristate_disable(PINGRP_GMC);
 #endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
 }
 
+#ifdef CONFIG_TEGRA2_MMC
 /*
  * Routine: clock_init_mmc
  * Description: init the PLL and clocks for the SDMMC controllers
  */
 static void clock_init_mmc(void)
 {
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	u32 reg;
-
-	/* Do the SDMMC resets/clock enables */
-	reset_set_enable(PERIPH_ID_SDMMC4, 1);
-	clock_enable(PERIPH_ID_SDMMC4);
-
-	/* Enable pllp_out0 to SDMMC4 */
-	reg = readl(&clkrst->crc_clk_src_sdmmc4);
-	reg &= 0x3FFFFF00;	/* SDMMC4_CLK_SRC = 00, PLLP_OUT0 */
-	reg |= (10 << 1);	/* n-1, 11-1 shl 1 */
-	writel(reg, &clkrst->crc_clk_src_sdmmc4);
-
-	/*
-	 * As per the Tegra2 TRM, section 5.3.4:
-	 * 'Wait 2 us for the clock to flush through the pipe/logic'
-	 */
-	udelay(2);
-
-	reset_set_enable(PERIPH_ID_SDMMC4, 1);
-
-	reset_set_enable(PERIPH_ID_SDMMC3, 1);
-	clock_enable(PERIPH_ID_SDMMC3);
-
-	/* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */
-	reg = readl(&clkrst->crc_clk_src_sdmmc3);
-	reg &= 0x3FFFFF00;	/* SDMMC3_CLK_SRC = 00, PLLP_OUT0 */
-	reg |= (10 << 1);	/* n-1, 11-1 shl 1 */
-	writel(reg, &clkrst->crc_clk_src_sdmmc3);
-
-	/* wait for 2us */
-	udelay(2);
-
-	reset_set_enable(PERIPH_ID_SDMMC3, 0);
+	clock_start_periph_pll(PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH, 20000000);
+	clock_start_periph_pll(PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH, 20000000);
 }
 
 /*
@@ -203,65 +117,25 @@ static void clock_init_mmc(void)
  */
 static void pin_mux_mmc(void)
 {
-	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 reg;
-
-	/* SDMMC4 */
-	/* config 2, x8 on 2nd set of pins */
-	reg = readl(&pmt->pmt_ctl_a);
-	reg |= (3 << 16);	/* ATB_SEL [17:16] = 11 SDIO4 */
-	writel(reg, &pmt->pmt_ctl_a);
-	reg = readl(&pmt->pmt_ctl_b);
-	reg |= (3 << 0);	/* GMA_SEL [1:0] = 11 SDIO4 */
-	writel(reg, &pmt->pmt_ctl_b);
-	reg = readl(&pmt->pmt_ctl_d);
-	reg |= (3 << 0);	/* GME_SEL [1:0] = 11 SDIO4 */
-	writel(reg, &pmt->pmt_ctl_d);
+	/* SDMMC4: config 3, x8 on 2nd set of pins */
+	pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
+	pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
+	pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
 
-	pinmux_tristate_disable(PIN_ATB);
-	pinmux_tristate_disable(PIN_GMA);
-	pinmux_tristate_disable(PIN_GME);
-
-	/* SDMMC3 */
-	/* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
-	reg = readl(&pmt->pmt_ctl_d);
-	reg &= 0xFFFF03FF;
-	reg |= (2 << 10);	/* SDB_SEL [11:10] = 01 SDIO3 */
-	reg |= (2 << 12);	/* SDC_SEL [13:12] = 01 SDIO3 */
-	reg |= (2 << 14);	/* SDD_SEL [15:14] = 01 SDIO3 */
-	writel(reg, &pmt->pmt_ctl_d);
-
-	pinmux_tristate_disable(PIN_SDC);
-	pinmux_tristate_disable(PIN_SDD);
-	pinmux_tristate_disable(PIN_SDB);
-}
+	pinmux_tristate_disable(PINGRP_ATB);
+	pinmux_tristate_disable(PINGRP_GMA);
+	pinmux_tristate_disable(PINGRP_GME);
 
-/*
- * Routine: clock_init
- * Description: Do individual peripheral clock reset/enables
- */
-void clock_init(void)
-{
-	clock_init_uart();
-}
+	/* SDMMC3: SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
+	pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
+	pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
+	pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
 
-/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
-	pin_mux_uart();
-}
-
-/*
- * Routine: gpio_init
- * Description: Do individual peripheral GPIO configs
- */
-void gpio_init(void)
-{
-	gpio_config_uart();
+	pinmux_tristate_disable(PINGRP_SDC);
+	pinmux_tristate_disable(PINGRP_SDD);
+	pinmux_tristate_disable(PINGRP_SDB);
 }
+#endif
 
 /*
  * Routine: board_init
@@ -269,6 +143,9 @@ void gpio_init(void)
  */
 int board_init(void)
 {
+	clock_init();
+	clock_verify();
+
 	/* boot param addr */
 	gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
 
@@ -283,6 +160,7 @@ int board_mmc_init(bd_t *bd)
 	/* Enable clocks, muxes, etc. for SDMMC controllers */
 	clock_init_mmc();
 	pin_mux_mmc();
+	gpio_config_mmc();
 
 	debug("board_mmc_init: init eMMC\n");
 	/* init dev 0, eMMC chip, with 4-bit bus */
@@ -294,16 +172,25 @@ int board_mmc_init(bd_t *bd)
 
 	return 0;
 }
+#endif
 
-/* this is a weak define that we are overriding */
-int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
 {
-	debug("board_mmc_getcd called\n");
-	/*
-	 * Hard-code CD presence for now. Need to add GPIO inputs
-	 * for Seaboard & Harmony (& Kaen/Aebl/Wario?)
-	 */
-	*cd = 1;
+	/* Initialize essential common plls */
+	clock_early_init();
+
+	/* Initialize UART clocks */
+	clock_init_uart();
+
+	/* Initialize periph pinmuxes */
+	pin_mux_uart();
+
+	/* Initialize periph GPIOs */
+	gpio_config_uart();
+
+	/* Init UART, scratch regs, and start CPU */
+	tegra2_start();
 	return 0;
 }
-#endif
+#endif	/* EARLY_INIT */