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| author | wdenk <wdenk> | 2004-06-10 21:34:36 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-06-10 21:34:36 +0000 |
| commit | b54d32b40d95d399dd1f53f24c93b0cf5c42460d (patch) | |
| tree | dba569eef315497f378c460e0e72ce98df053dd1 /board/mx1ads/syncflash.c | |
| parent | 681334540d109558fe7c382faf9c705439c2dfa3 (diff) | |
| download | olio-uboot-2014.01-b54d32b40d95d399dd1f53f24c93b0cf5c42460d.tar.xz olio-uboot-2014.01-b54d32b40d95d399dd1f53f24c93b0cf5c42460d.zip | |
* Patch by Robert Schwebel, 10 Jun 2004:
Add support for Intel K3 strata flash.
* Some cleanup
* Patch by Thomas Brand, 10 Jun 2004:
Fix "loads" command on DK1S10 board
Diffstat (limited to 'board/mx1ads/syncflash.c')
| -rw-r--r-- | board/mx1ads/syncflash.c | 32 |
1 files changed, 15 insertions, 17 deletions
diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c index afbe78653..fc1d7f6ce 100644 --- a/board/mx1ads/syncflash.c +++ b/board/mx1ads/syncflash.c @@ -33,26 +33,26 @@ typedef unsigned long * p_u32; flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Following Setting is for CSD1 */ -#define SFCTL 0x00221004 -#define reg_SFCTL __REG(SFCTL) +#define SFCTL 0x00221004 +#define reg_SFCTL __REG(SFCTL) -#define SYNCFLASH_A10 (0x00100000) +#define SYNCFLASH_A10 (0x00100000) -#define CMD_NORMAL (0x81020300) /* Normal Mode */ -#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ -#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ -#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ -#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ -#define CMD_PROGRAM (CMD_NORMAL + 0x70000000) +#define CMD_NORMAL (0x81020300) /* Normal Mode */ +#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ +#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ +#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ +#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ +#define CMD_PROGRAM (CMD_NORMAL + 0x70000000) -#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ +#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ /* LCR Command */ -#define LCR_READSTATUS (0x0001C000) /* 0x70 */ -#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */ -#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */ -#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ -#define LCR_SR_CLEAR (0x00014000) /* 0x50 */ +#define LCR_READSTATUS (0x0001C000) /* 0x70 */ +#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */ +#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */ +#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ +#define LCR_SR_CLEAR (0x00014000) /* 0x50 */ /* Get Status register */ @@ -330,5 +330,3 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { return ERR_OK; } - - |