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| author | Stefan Roese <sr@denx.de> | 2008-10-21 11:43:08 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-10-21 11:43:08 +0200 |
| commit | f61f1e150c84f5b9347fca79a4bc5f2286c545d2 (patch) | |
| tree | ab90f076f18e56b2b3e8c9375b95917daa78c1d9 /board/incaip/incaip.c | |
| parent | ec081c2c190148b374e86a795fb6b1c49caeb549 (diff) | |
| parent | f82642e33899766892499b163e60560fbbf87773 (diff) | |
| download | olio-uboot-2014.01-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.tar.xz olio-uboot-2014.01-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.zip | |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'board/incaip/incaip.c')
| -rw-r--r-- | board/incaip/incaip.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c index 6fe852cf9..3b30970b9 100644 --- a/board/incaip/incaip.c +++ b/board/incaip/incaip.c @@ -40,16 +40,16 @@ static ulong max_sdram_size(void) { /* The only supported SDRAM data width is 16bit. */ -#define CFG_DW 2 +#define CONFIG_SYS_DW 2 /* The only supported number of SDRAM banks is 4. */ -#define CFG_NB 4 +#define CONFIG_SYS_NB 4 ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0; int cols = cfgpb0 & 0xF; int rows = (cfgpb0 & 0xF0) >> 4; - ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB; + ulong size = (1 << (rows + cols)) * CONFIG_SYS_DW * CONFIG_SYS_NB; return size; } @@ -75,7 +75,7 @@ phys_size_t initdram(int board_type) { *INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) | (rows << 4) | cols; - size = get_ram_size((long *)CFG_SDRAM_BASE, + size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, max_sdram_size()); if (size > max_size) |