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| author | Guennadi Liakhovetski <lg@denx.de> | 2009-02-24 10:44:02 +0100 |
|---|---|---|
| committer | Anatolij Gustschin <agust@denx.de> | 2009-02-24 10:44:02 +0100 |
| commit | a2bb7105a79af8f2ffa9f87256fce6c1cbcbd8e1 (patch) | |
| tree | f3f8eee4d1566b4e312049e490f2bed00d4fb969 /board/imx31_phycore | |
| parent | 0c99f6ab31c5635874ba7a2e8d37791bfbf02f8f (diff) | |
| download | olio-uboot-2014.01-a2bb7105a79af8f2ffa9f87256fce6c1cbcbd8e1.tar.xz olio-uboot-2014.01-a2bb7105a79af8f2ffa9f87256fce6c1cbcbd8e1.zip | |
ARM: add an "eet" variant of the imx31_phycore board
The "eet" variant of the imx31_phycore board has an OLED display, using a
s6e63d6 display controller on the first SPI interface, using GPIO57 as a
chip-select for it. With this configuration you can display 256 colour BMP
images in 16-bit RGB (RGB565) LCD mode.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/imx31_phycore')
| -rw-r--r-- | board/imx31_phycore/imx31_phycore.c | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c index ae93444a1..93a5c40d7 100644 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@ -23,6 +23,7 @@ #include <common.h> +#include <s6e63d6.h> #include <asm/arch/mx31.h> #include <asm/arch/mx31-regs.h> @@ -66,6 +67,62 @@ int board_init (void) return 0; } +#ifdef BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_S6E63D6 + struct s6e63d6 data = { + /* + * See comment in mxc_spi.c::decode_cs() for .cs field format. + * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect + * 2 of the SPI controller #1, since it is unused. + */ + .cs = 2 | (57 << 8), + .bus = 0, + .id = 0, + }; + int ret; + + /* SPI1 */ + mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK); + mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B); + mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI); + mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO); + mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B); + mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B); + mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B); + + /* start SPI1 clock */ + __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2); + + /* GPIO 57 */ + /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */ + mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO)); + + /* SPI1 CS2 is free */ + ret = s6e63d6_init(&data); + if (ret) + return ret; + + /* + * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC + * OLED display connected to a S6E63D6 SPI display controller in the + * 18 bit RGB mode + */ + s6e63d6_index(&data, 2); + s6e63d6_param(&data, 0x0182); + s6e63d6_index(&data, 3); + s6e63d6_param(&data, 0x8130); + s6e63d6_index(&data, 0x10); + s6e63d6_param(&data, 0x0000); + s6e63d6_index(&data, 5); + s6e63d6_param(&data, 0x0001); + s6e63d6_index(&data, 0x22); +#endif + return 0; +} +#endif + int checkboard (void) { printf("Board: Phytec phyCore i.MX31\n"); |