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| author | Mingkai Hu <Mingkai.hu@freescale.com> | 2011-07-07 12:29:15 +0800 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-07-17 11:03:36 -0500 |
| commit | 4f1d1b7d1e647b4e0ffd9b9feedd02110d078bdb (patch) | |
| tree | cf8a0add8b61e08bcf0d5d5c2d039ed2d9ffb486 /board/gcplus/flash.c | |
| parent | c518fc028189699c1b169f524be60b990b88cb28 (diff) | |
| download | olio-uboot-2014.01-4f1d1b7d1e647b4e0ffd9b9feedd02110d078bdb.tar.xz olio-uboot-2014.01-4f1d1b7d1e647b4e0ffd9b9feedd02110d078bdb.zip | |
powerpc/p2041rdb: Add p2041rdb board support
P2041RDB Specification:
-----------------------
Memory subsystem:
* 4Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
* 128 Mbyte NOR flash single-chip memory
* 256 Kbit M24256 I2C EEPROM
* 16 Mbyte SPI memory
* SD connector to interface with the SD memory card
Ethernet:
* dTSEC1: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC2: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC3: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC4: connected to the Vitesse RGMII PHY (VSC8641)
* dTSEC5: connected to the Vitesse RGMII PHY (VSC8641)
PCIe:
* Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1
* Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2
SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors
USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces
I2C:
* I2C1: Real time clock, Temperature sensor, Memory module
* I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/gcplus/flash.c')
0 files changed, 0 insertions, 0 deletions