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| author | Wolfgang Denk <wd@denx.de> | 2011-10-21 23:48:46 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-10-21 23:48:46 +0200 |
| commit | 02aff558f4b68927c719a33bee8d13d325d105fb (patch) | |
| tree | 215757279d23a8984cad993679c6be20fe0d6831 /board/freescale/p2020ds/ddr.c | |
| parent | f82c087e60fe1c59ace1c6f016eb89c5d3c3ae13 (diff) | |
| parent | 710308ee185b3087e474fb9b205f47613c65dda4 (diff) | |
| download | olio-uboot-2014.01-02aff558f4b68927c719a33bee8d13d325d105fb.tar.xz olio-uboot-2014.01-02aff558f4b68927c719a33bee8d13d325d105fb.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
mpc85xx: Add inline GPIO acessor functions
powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)
powerpc/85xx: Fix P2020DS booting
powerpc/85xx: Update USB device tree status based on pin settings
fdt: Add new fdt_set_node_status & fdt_set_status_by_alias helpers
powerpc/85xx: Add support for RMan LIODN initialization
powerpc/85xx: Update device tree handling for SRIO
powerpc/85xx: Update setting of SRIO LIODNs
fm: Don't allow disabling of FM1-DTSEC1
fm-eth: Don't mark the MAC we use for MDIO as disabled in device tree
Diffstat (limited to 'board/freescale/p2020ds/ddr.c')
| -rw-r--r-- | board/freescale/p2020ds/ddr.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index c43f874c9..59034f9f8 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -57,6 +57,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; + int i; if (ctrl_num) { printf("Wrong parameter for controller number %d", ctrl_num); @@ -65,6 +66,17 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (!pdimm->n_ranks) return; + /* + * set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If + * there are two dimms in the controller, set odt_rd_cfg to 3 and + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. + */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 1; + } + pbsp = dimm0; /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr |