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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-12-02 16:08:38 -0600 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2009-01-23 17:03:13 -0600 |
| commit | a6e04c344ad1eefd47a75484441b385da815b8df (patch) | |
| tree | e26692c23590ac935001374f09adb08b443905cc /board/freescale/mpc8560ads/tlb.c | |
| parent | 5f91ef6acdbadec33e0192049e2b24a1d9692f1d (diff) | |
| download | olio-uboot-2014.01-a6e04c344ad1eefd47a75484441b385da815b8df.tar.xz olio-uboot-2014.01-a6e04c344ad1eefd47a75484441b385da815b8df.zip | |
85xx: Use CONFIG_SYS_{PCI*,RIO*}_MEM_PHYS for physical address on FSL boards
Use the _MEM_PHYS defines instead of _MEM_BUS for LAW and real address fields
of TLBs. This is what we should have always been using from the start.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/mpc8560ads/tlb.c')
| -rw-r--r-- | board/freescale/mpc8560ads/tlb.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index 758bd7006..205c06ada 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_BUS, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), |