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| author | Jon Loeliger <jdl@freescale.com> | 2008-03-17 15:48:18 -0500 | 
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-08-27 11:43:50 -0500 | 
| commit | aa11d85cf318b961e029fe50d68ca47d004bce93 (patch) | |
| tree | 30fb129452749c5a8ea5e817d8fd125986b85dc9 /board/freescale/mpc8541cds/ddr.c | |
| parent | 2b40edb10d81da7bba724edbccd7f53777112579 (diff) | |
| download | olio-uboot-2014.01-aa11d85cf318b961e029fe50d68ca47d004bce93.tar.xz olio-uboot-2014.01-aa11d85cf318b961e029fe50d68ca47d004bce93.zip | |
FSL DDR: Convert MPC8541CDS to new DDR code.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/mpc8541cds/ddr.c')
| -rw-r--r-- | board/freescale/mpc8541cds/ddr.c | 79 | 
1 files changed, 79 insertions, 0 deletions
| diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c new file mode 100644 index 000000000..11ce57d36 --- /dev/null +++ b/board/freescale/mpc8541cds/ddr.c @@ -0,0 +1,79 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> + +static void +get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) +{ +	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ +	return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, +		      unsigned int ctrl_num) +{ +	unsigned int i; +	unsigned int i2c_address = 0; + +	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { +		if (ctrl_num == 0 && i == 0) { +			i2c_address = SPD_EEPROM_ADDRESS; +		} +		get_spd(&(ctrl_dimms_spd[i]), i2c_address); +	} +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ +	/* +	 * Factors to consider for clock adjust: +	 *	- number of chips on bus +	 *	- position of slot +	 *	- DDR1 vs. DDR2? +	 *	- ??? +	 * +	 * This needs to be determined on a board-by-board basis. +	 *	0110	3/4 cycle late +	 *	0111	7/8 cycle late +	 */ +	popts->clk_adjust = 6; + +	/* +	 * Factors to consider for CPO: +	 *	- frequency +	 *	- ddr1 vs. ddr2 +	 */ +	popts->cpo_override = 0; + +	/* +	 * Factors to consider for write data delay: +	 *	- number of DIMMs +	 * +	 * 1 = 1/4 clock delay +	 * 2 = 1/2 clock delay +	 * 3 = 3/4 clock delay +	 * 4 = 1   clock delay +	 * 5 = 5/4 clock delay +	 * 6 = 3/2 clock delay +	 */ +	popts->write_data_delay = 3; + +	/* +	 * Factors to consider for half-strength driver enable: +	 *	- number of DIMMs installed +	 */ +	popts->half_strength_driver_enable = 0; +} |