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| author | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
|---|---|---|
| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
| commit | cb5473205206c7f14cbb1e747f28ec75b48826e2 (patch) | |
| tree | 8f4808d60917100b18a10b05230f7638a0a9bbcc /board/freescale/mpc7448hpc2/asm_init.S | |
| parent | baf449fc5ff96f071bb0e3789fd3265f6d4fd9a0 (diff) | |
| parent | 92c78a3bbcb2ce508b4bf1c4a1e0940406a024bb (diff) | |
| download | olio-uboot-2014.01-cb5473205206c7f14cbb1e747f28ec75b48826e2.tar.xz olio-uboot-2014.01-cb5473205206c7f14cbb1e747f28ec75b48826e2.zip | |
Merge branch 'fixes' into cleanups
Conflicts:
board/atmel/atngw100/atngw100.c
board/atmel/atstk1000/atstk1000.c
cpu/at32ap/at32ap700x/gpio.c
include/asm-avr32/arch-at32ap700x/clk.h
include/configs/atngw100.h
include/configs/atstk1002.h
include/configs/atstk1003.h
include/configs/atstk1004.h
include/configs/atstk1006.h
include/configs/favr-32-ezkit.h
include/configs/hammerhead.h
include/configs/mimc200.h
Diffstat (limited to 'board/freescale/mpc7448hpc2/asm_init.S')
| -rw-r--r-- | board/freescale/mpc7448hpc2/asm_init.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/mpc7448hpc2/asm_init.S b/board/freescale/mpc7448hpc2/asm_init.S index 521301fce..b9495fd34 100644 --- a/board/freescale/mpc7448hpc2/asm_init.S +++ b/board/freescale/mpc7448hpc2/asm_init.S @@ -123,7 +123,7 @@ board_asm_init: /* Initialize pointer to Tsi108 register space */ - LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ + LOAD_PTR(r29,CONFIG_SYS_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ ori r4,r29,TSI108_PB_REG_OFFSET /* Check Processor Version Number */ @@ -214,12 +214,12 @@ do_tsi108_init: ori r4,r29,TSI108_PB_REG_OFFSET -#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE) +#if (CONFIG_SYS_TSI108_CSR_BASE != CONFIG_SYS_TSI108_CSR_RST_BASE) /* Relocate (if required) Tsi108 registers. Set new value for * PB_REG_BAR: * Note we are in the 32-bit address mode. */ - LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */ + LOAD_U32(r5,(CONFIG_SYS_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */ stw r5,PB_REG_BAR(r4) andis. r29,r5,0xFFFF sync |