diff options
| author | Poonam Aggrwal <poonam.aggrwal@freescale.com> | 2012-12-23 19:24:16 +0000 | 
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-01-30 11:25:10 -0600 | 
| commit | e1dbdd81523c7c7de1ac5dee03dd9e4587e808af (patch) | |
| tree | 7271df8bfcc1d40292dc45c9a6fe516077a4bf95 /arch/powerpc/include/asm/config_mpc85xx.h | |
| parent | e394ceb17f93545e6b89b6d04df348dc435e2d4f (diff) | |
| download | olio-uboot-2014.01-e1dbdd81523c7c7de1ac5dee03dd9e4587e808af.tar.xz olio-uboot-2014.01-e1dbdd81523c7c7de1ac5dee03dd9e4587e808af.zip | |
powerpc/mpc85xx:Add support of B4420 SoC
B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900
and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and
reduced target frequencies.
Key differences between B4860 and B4420
----------------------------------------
B4420 has:
1. Fewer e6500 cores: 1 cluster with 2 e6500 cores
2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
3. Single DDRC
4. 2X 4 lane serdes
5. 3 SGMII interfaces
6. no sRIO
7. no 10G
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm/config_mpc85xx.h')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 21 | 
1 files changed, 21 insertions, 0 deletions
| diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 856ae95e6..f957fa375 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -525,6 +525,27 @@  #define CONFIG_SYS_FSL_ERRATUM_A_004934  #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000 +#elif defined(CONFIG_PPC_B4420) +#define CONFIG_SYS_PPC64		/* 64-bit core */ +#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */ +#define CONFIG_MAX_CPUS			2 +#define CONFIG_SYS_FSL_NUM_CC_PLLS	4 +#define CONFIG_SYS_FSL_NUM_LAWS		32 +#define CONFIG_SYS_FSL_SEC_COMPAT	4 +#define CONFIG_SYS_NUM_FMAN		1 +#define CONFIG_SYS_NUM_FM1_DTSEC	4 +#define CONFIG_NUM_DDR_CONTROLLERS	1 +#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7 +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FM_MURAM_SIZE	0x60000 +#define CONFIG_SYS_FSL_TBCLK_DIV	16 +#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4" +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_A_004934 +#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000 +  #elif defined(CONFIG_PPC_B4860)  #define CONFIG_SYS_PPC64		/* 64-bit core */  #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */ |