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| author | York Sun <yorksun@freescale.com> | 2013-09-16 12:49:31 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-10-16 16:15:17 -0700 |
| commit | 133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a (patch) | |
| tree | 8310923265a2fd56d900bc4b973cfbb2f95dfc75 /arch/powerpc/include/asm/config_mpc85xx.h | |
| parent | e512c50bc9e3ef0bcf209620cabfc6ef35f22ff3 (diff) | |
| download | olio-uboot-2014.01-133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a.tar.xz olio-uboot-2014.01-133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a.zip | |
powerpc/mpc85xx: Add workaround for erratum A006379
Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to 0x1e.
Erratum A006379 applies to
T4240 rev 1.0
B4860 rev 1.0, 2.0
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm/config_mpc85xx.h')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index b51d38379..946ea975b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -599,6 +599,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004468 #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_PCI_VER_3_X @@ -624,6 +625,7 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |