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| author | Shruti Kanetkar <Shruti@Freescale.com> | 2013-08-15 11:25:38 -0500 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-20 10:38:12 -0700 |
| commit | 6b44d9e5b79948a73f9fae4b84c21f62224fa46b (patch) | |
| tree | 7cc38f702d5b496d993ad4f7428f7888379e9c62 /arch/powerpc/cpu/mpc85xx | |
| parent | 2f848f97d7b27a88135de98aae76531a6fdd44e6 (diff) | |
| download | olio-uboot-2014.01-6b44d9e5b79948a73f9fae4b84c21f62224fa46b.tar.xz olio-uboot-2014.01-6b44d9e5b79948a73f9fae4b84c21f62224fa46b.zip | |
powerpcv2: Print hardcoded size like print_size() does
Makes the startup output more consistent
Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 14 |
2 files changed, 8 insertions, 8 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index b77964a4c..1a0196c7c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -210,7 +210,7 @@ int checkcpu (void) printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme)); #endif - puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); + puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n"); #ifdef CONFIG_FSL_CORENET /* Display the RCW, so that no one gets confused as to what RCW diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 565c28159..c6e09ca90 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -458,28 +458,28 @@ int cpu_init_r(void) case 0x1: if (ver == SVR_8540 || ver == SVR_8560 || ver == SVR_8541 || ver == SVR_8555) { - puts("128 KB "); - /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ + puts("128 KiB "); + /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ cache_ctl = 0xc4000000; } else { - puts("256 KB "); + puts("256 KiB "); cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ } break; case 0x2: if (ver == SVR_8540 || ver == SVR_8560 || ver == SVR_8541 || ver == SVR_8555) { - puts("256 KB "); - /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ + puts("256 KiB "); + /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ cache_ctl = 0xc8000000; } else { - puts ("512 KB "); + puts("512 KiB "); /* set L2E=1, L2I=1, & L2SRAM=0 */ cache_ctl = 0xc0000000; } break; case 0x3: - puts("1024 KB "); + puts("1024 KiB "); /* set L2E=1, L2I=1, & L2SRAM=0 */ cache_ctl = 0xc0000000; break; |