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| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:30 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:32 -0500 |
| commit | ffd06e0231ac3fd0c5810f39f6e23527948df1c7 (patch) | |
| tree | 7d648c2c312b9cc7a75c0350101aacc67afca399 /arch/powerpc/cpu/mpc85xx/mp.h | |
| parent | 3f0997b3255c1498ac92453aa3a7a1cc95914dfd (diff) | |
| download | olio-uboot-2014.01-ffd06e0231ac3fd0c5810f39f6e23527948df1c7.tar.xz olio-uboot-2014.01-ffd06e0231ac3fd0c5810f39f6e23527948df1c7.zip | |
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
'M' bit is set for DDR TLB to maintain cache coherence.
See details in doc/README.mpc85xx-spin-table.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/mp.h')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/mp.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/mp.h b/arch/powerpc/cpu/mpc85xx/mp.h index 87bac3715..ad9950bcf 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.h +++ b/arch/powerpc/cpu/mpc85xx/mp.h @@ -3,8 +3,7 @@ #include <asm/mp.h> -ulong get_spin_phys_addr(void); -ulong get_spin_virt_addr(void); +phys_addr_t get_spin_phys_addr(void); u32 get_my_id(void); int hold_cores_in_reset(int verbose); @@ -16,7 +15,7 @@ int hold_cores_in_reset(int verbose); #define BOOT_ENTRY_PIR 5 #define BOOT_ENTRY_R6_UPPER 6 #define BOOT_ENTRY_R6_LOWER 7 -#define NUM_BOOT_ENTRY 8 +#define NUM_BOOT_ENTRY 16 /* pad to 64 bytes */ #define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32)) #endif |