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| author | Wolfgang Denk <wd@denx.de> | 2011-12-01 23:58:11 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-12-01 23:58:11 +0100 |
| commit | d51e6d6de2b7dcba43fadcae2c89f7346d8bc301 (patch) | |
| tree | 49bedf2073e031a421c89644f62134bf9ee4f44b /arch/powerpc/cpu/mpc85xx/ddr-gen3.c | |
| parent | 22e0f5a9ecab85f36a0fe69892d950c1ac212c91 (diff) | |
| parent | 9839709ea3df89f6021034508f48b97cab33ebb8 (diff) | |
| download | olio-uboot-2014.01-d51e6d6de2b7dcba43fadcae2c89f7346d8bc301.tar.xz olio-uboot-2014.01-d51e6d6de2b7dcba43fadcae2c89f7346d8bc301.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
mpc85xx: support for Freescale COM Express P2020
arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warning
mpc85xx: support board-specific reset function
powerpc/85xx: verify the localbus device tree address before booting the OS
mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification
powerpc/p3060qds: Add board related support for P3060QDS platform
powerpc/85xx: clean up and document the QE/FMAN microcode macros
powerpc/85xx: always implement the work-around for Erratum SATA_A001
powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h
powerpc/85xx: Add workaround for erratum A-003474
powerpc/85xx: fixup flexcan device tree clock-frequency
powerpc/85xx: Add workaround for erratum CPU-A003999
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/ddr-gen3.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index c8c84a1f7..18e9cc5b8 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -115,6 +115,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, for (i = 0; i < 32; i++) out_be32(&ddr->debug[i], regs->debug[i]); +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 + out_be32(&ddr->debug[12], 0x00000015); + out_be32(&ddr->debug[21], 0x24000000); +#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */ + /* Set, but do not enable the memory */ temp_sdram_cfg = regs->ddr_sdram_cfg; temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); |