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| author | York Sun <yorksun@freescale.com> | 2013-06-25 11:37:41 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:38 -0700 |
| commit | cb93071bb6da21d17dd7d7d414a389b380f959b2 (patch) | |
| tree | ef8cc19e0c01b00baeda237802d4b6b383d5e5f7 /arch/powerpc/cpu/mpc85xx/ddr-gen3.c | |
| parent | 7adefb55adf3e55f3788c3b9682ba91d29da2595 (diff) | |
| download | olio-uboot-2014.01-cb93071bb6da21d17dd7d7d414a389b380f959b2.tar.xz olio-uboot-2014.01-cb93071bb6da21d17dd7d7d414a389b380f959b2.zip | |
mpc85xx: Base emulator support
Prepare for emulator support for mpc85xx parts.
Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers.
These two registers improve stability but not supported by emulator.
Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/ddr-gen3.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index c5b47200e..3e7a56489 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -123,10 +123,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); +#ifndef CONFIG_SYS_FSL_DDR_EMU + /* + * Skip these two registers if running on emulator + * because emulator doesn't have skew between bytes. + */ + if (regs->ddr_wrlvl_cntl_2) out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); if (regs->ddr_wrlvl_cntl_3) out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); +#endif out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); |